Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/i386/isa/if_sr.c
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /* 2 * Copyright (c) 1996 John Hay. 3 * Copyright (c) 1996 SDL Communications, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of the author nor the names of any co-contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD: src/sys/i386/isa/if_sr.c,v 1.4.2.2 1999/09/05 08:12:57 peter Exp $ 31 */ 32 33 /* 34 * Programming assumptions and other issues. 35 * 36 * Only a 16K window will be used. 37 * 38 * The descriptors of a DMA channel will fit in a 16K memory window. 39 * 40 * The buffers of a transmit DMA channel will fit in a 16K memory window. 41 * 42 * When interface is going up, handshaking is set and it is only cleared 43 * when the interface is down'ed. 44 * 45 * There should be a way to set/reset Raw HDLC/PPP, Loopback, DCE/DTE, 46 * internal/external clock, etc..... 47 * 48 */ 49 50 #include "sr.h" 51 #ifdef notyet 52 #include "fr.h" 53 #else 54 #define NFR 0 55 #endif 56 #include "pci.h" 57 #include "bpfilter.h" 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/kernel.h> 62 #include <sys/mbuf.h> 63 #include <sys/sockio.h> 64 #include <sys/socket.h> 65 66 #include <net/if.h> 67 #include <net/if_sppp.h> 68 69 #if NBPFILTER > 0 70 #include <net/bpf.h> 71 #endif 72 73 #include <machine/md_var.h> 74 75 #include <i386/isa/if_srregs.h> 76 #include <i386/isa/ic/hd64570.h> 77 78 #include "ioconf.h" 79 80 /* #define USE_MODEMCK */ 81 82 #ifndef BUGGY 83 #define BUGGY 0 84 #endif 85 86 #define PPP_HEADER_LEN 4 87 88 /* 89 * These macros are used to hide the difference between the way the 90 * ISA N2 cards and the PCI N2 cards access the Hitachi 64570 SCA. 91 */ 92 #define SRC_GET8(base,off) (*hc->src_get8)(base,(u_int)&off) 93 #define SRC_GET16(base,off) (*hc->src_get16)(base,(u_int)&off) 94 #define SRC_PUT8(base,off,d) (*hc->src_put8)(base,(u_int)&off,d) 95 #define SRC_PUT16(base,off,d) (*hc->src_put16)(base,(u_int)&off,d) 96 97 /* 98 * These macros enable/disable the DPRAM and select the correct 99 * DPRAM page. 100 */ 101 #define SRC_GET_WIN(addr) ((addr >> SRC_WIN_SHFT) & SR_PG_MSK) 102 103 #define SRC_SET_ON(iobase) outb(iobase+SR_PCR, \ 104 SR_PCR_MEM_WIN | inb(iobase+SR_PCR)) 105 #define SRC_SET_MEM(iobase,win) outb(iobase+SR_PSR, SRC_GET_WIN(win) | \ 106 (inb(iobase+SR_PSR) & ~SR_PG_MSK)) 107 #define SRC_SET_OFF(iobase) outb(iobase+SR_PCR, \ 108 ~SR_PCR_MEM_WIN & inb(iobase+SR_PCR)) 109 110 /* 111 * Define the hardware (card information) structure needed to keep 112 * track of the device itself... There is only one per card. 113 */ 114 struct sr_hardc { 115 struct sr_hardc *next; /* PCI card linkage */ 116 struct sr_softc *sc; /* software channels */ 117 int cunit; /* card w/in system */ 118 119 u_short iobase; /* I/O Base Address */ 120 int cardtype; 121 int numports; /* # of ports on cd */ 122 int mempages; 123 u_int memsize; /* DPRAM size: bytes */ 124 u_int winmsk; 125 vm_offset_t sca_base; 126 vm_offset_t mem_pstart; /* start of buffer */ 127 caddr_t mem_start; /* start of DP RAM */ 128 caddr_t mem_end; /* end of DP RAM */ 129 caddr_t plx_base; 130 131 sca_regs *sca; /* register array */ 132 133 /* 134 * We vectorize the following functions to allow re-use between the 135 * ISA card's needs and those of the PCI card. 136 */ 137 void (*src_put8)(u_int base, u_int off, u_int val); 138 void (*src_put16)(u_int base, u_int off, u_int val); 139 u_int (*src_get8)(u_int base, u_int off); 140 u_int (*src_get16)(u_int base, u_int off); 141 }; 142 143 static int next_sc_unit = 0; 144 static int sr_watcher = 0; 145 static struct sr_hardc sr_hardc[NSR]; 146 static struct sr_hardc *sr_hardc_pci; 147 148 /* 149 * Define the software interface for the card... There is one for 150 * every channel (port). 151 */ 152 struct sr_softc { 153 struct sppp ifsppp; /* PPP service w/in system */ 154 struct sr_hardc *hc; /* card-level information */ 155 156 int unit; /* With regard to all sr devices */ 157 int subunit; /* With regard to this card */ 158 159 int attached; /* attached to FR or PPP */ 160 int protocol; /* FR or PPP */ 161 #define N2_USE_FRP 2 /* Frame Relay Protocol */ 162 #define N2_USE_PPP 1 /* Point-to-Point Protocol */ 163 164 struct buf_block { 165 u_int txdesc; /* DPRAM offset */ 166 u_int txstart;/* DPRAM offset */ 167 u_int txend; /* DPRAM offset */ 168 u_int txtail; /* # of 1st free gran */ 169 u_int txmax; /* # of free grans */ 170 u_int txeda; /* err descr addr */ 171 } block[SR_TX_BLOCKS]; 172 173 char xmit_busy; /* Transmitter is busy */ 174 char txb_inuse; /* # of tx grans in use */ 175 u_int txb_new; /* ndx to new buffer */ 176 u_int txb_next_tx; /* ndx to next gran rdy tx */ 177 178 u_int rxdesc; /* DPRAM offset */ 179 u_int rxstart; /* DPRAM offset */ 180 u_int rxend; /* DPRAM offset */ 181 u_int rxhind; /* ndx to the hd of rx bufrs */ 182 u_int rxmax; /* # of avail grans */ 183 184 u_int clk_cfg; /* Clock configuration */ 185 186 int scachan; /* channel # on card */ 187 }; 188 189 /* 190 * List of valid interrupt numbers for the N2 ISA card. 191 */ 192 static int sr_irqtable[16] = { 193 0, /* 0 */ 194 0, /* 1 */ 195 0, /* 2 */ 196 1, /* 3 */ 197 1, /* 4 */ 198 1, /* 5 */ 199 0, /* 6 */ 200 1, /* 7 */ 201 0, /* 8 */ 202 0, /* 9 */ 203 1, /* 10 */ 204 1, /* 11 */ 205 1, /* 12 */ 206 0, /* 13 */ 207 0, /* 14 */ 208 1 /* 15 */ 209 }; 210 211 static int srprobe(struct isa_device *id); 212 static int srattach_isa(struct isa_device *id); 213 214 struct isa_driver srdriver = {srprobe, srattach_isa, "src"}; 215 216 /* 217 * Baud Rate table for Sync Mode. 218 * Each entry consists of 3 elements: 219 * Baud Rate (x100) , TMC, BR 220 * 221 * Baud Rate = FCLK / TMC / 2^BR 222 * Baud table for Crystal freq. of 9.8304 Mhz 223 */ 224 #ifdef N2_TEST_SPEED 225 struct rate_line { 226 int target; /* target rate/100 */ 227 int tmc_reg; /* TMC register value */ 228 int br_reg; /* BR (BaudRateClk) selector */ 229 } n2_rates[] = { 230 /* Baudx100 TMC BR */ 231 { 3, 128, 8 }, 232 { 6, 128, 7 }, 233 { 12, 128, 6 }, 234 { 24, 128, 5 }, 235 { 48, 128, 4 }, 236 { 96, 128, 3 }, 237 { 192, 128, 2 }, 238 { 384, 128, 1 }, 239 { 560, 88, 1 }, 240 { 640, 77, 1 }, 241 { 1280, 38, 1 }, 242 { 2560, 19, 1 }, 243 { 5120, 10, 1 }, 244 { 10000, 5, 1 }, 245 { 15000, 3, 1 }, 246 { 25000, 2, 1 }, 247 { 50000, 1, 1 }, 248 { 0, 0, 0 } 249 }; 250 251 int sr_test_speed[] = { 252 N2_TEST_SPEED, 253 N2_TEST_SPEED 254 }; 255 256 int etc0vals[] = { 257 SR_MCR_ETC0, /* ISA channel 0 */ 258 SR_MCR_ETC1, /* ISA channel 1 */ 259 SR_FECR_ETC0, /* PCI channel 0 */ 260 SR_FECR_ETC1 /* PCI channel 1 */ 261 }; 262 #endif 263 264 struct sr_hardc *srattach_pci(int unit, vm_offset_t plx_vaddr, 265 vm_offset_t sca_vaddr); 266 void srintr_hc(struct sr_hardc *hc); 267 268 static int srattach(struct sr_hardc *hc); 269 static void sr_xmit(struct sr_softc *sc); 270 static void srstart(struct ifnet *ifp); 271 static int srioctl(struct ifnet *ifp, int cmd, caddr_t data); 272 static void srwatchdog(struct ifnet *ifp); 273 static int sr_packet_avail(struct sr_softc *sc, int *len, u_char *rxstat); 274 static void sr_copy_rxbuf(struct mbuf *m, struct sr_softc *sc, int len); 275 static void sr_eat_packet(struct sr_softc *sc, int single); 276 static void sr_get_packets(struct sr_softc *sc); 277 278 static void sr_up(struct sr_softc *sc); 279 static void sr_down(struct sr_softc *sc); 280 static void src_init(struct sr_hardc *hc); 281 static void sr_init_sca(struct sr_hardc *hc); 282 static void sr_init_msci(struct sr_softc *sc); 283 static void sr_init_rx_dmac(struct sr_softc *sc); 284 static void sr_init_tx_dmac(struct sr_softc *sc); 285 static void sr_dmac_intr(struct sr_hardc *hc, u_char isr); 286 static void sr_msci_intr(struct sr_hardc *hc, u_char isr); 287 static void sr_timer_intr(struct sr_hardc *hc, u_char isr); 288 static void sr_modemck(void *x); 289 290 static u_int src_get8_io(u_int base, u_int off); 291 static u_int src_get16_io(u_int base, u_int off); 292 static void src_put8_io(u_int base, u_int off, u_int val); 293 static void src_put16_io(u_int base, u_int off, u_int val); 294 static u_int src_get8_mem(u_int base, u_int off); 295 static u_int src_get16_mem(u_int base, u_int off); 296 static void src_put8_mem(u_int base, u_int off, u_int val); 297 static void src_put16_mem(u_int base, u_int off, u_int val); 298 299 #if NFR > 0 300 extern void fr_detach(struct ifnet *); 301 extern int fr_attach(struct ifnet *); 302 extern int fr_ioctl(struct ifnet *, int, caddr_t); 303 extern void fr_flush(struct ifnet *); 304 extern int fr_input(struct ifnet *, struct mbuf *); 305 extern struct mbuf *fr_dequeue(struct ifnet *); 306 #endif 307 308 /* 309 * I/O for ISA N2 card(s) 310 */ 311 #define SRC_REG(iobase,y) ((((y) & 0xf) + (((y) & 0xf0) << 6) + \ 312 (iobase)) | 0x8000) 313 314 static u_int 315 src_get8_io(u_int base, u_int off) 316 { 317 return inb(SRC_REG(base, off)); 318 } 319 320 static u_int 321 src_get16_io(u_int base, u_int off) 322 { 323 return inw(SRC_REG(base, off)); 324 } 325 326 static void 327 src_put8_io(u_int base, u_int off, u_int val) 328 { 329 outb(SRC_REG(base, off), val); 330 } 331 332 static void 333 src_put16_io(u_int base, u_int off, u_int val) 334 { 335 outw(SRC_REG(base, off), val); 336 } 337 338 /* 339 * I/O for PCI N2 card(s) 340 */ 341 #define SRC_PCI_SCA_REG(y) ((y & 2) ? ((y & 0xfd) + 0x100) : y) 342 343 static u_int 344 src_get8_mem(u_int base, u_int off) 345 { 346 return *((u_char *)(base + SRC_PCI_SCA_REG(off))); 347 } 348 349 static u_int 350 src_get16_mem(u_int base, u_int off) 351 { 352 return *((u_short *)(base + SRC_PCI_SCA_REG(off))); 353 } 354 355 static void 356 src_put8_mem(u_int base, u_int off, u_int val) 357 { 358 *((u_char *)(base + SRC_PCI_SCA_REG(off))) = (u_char)val; 359 } 360 361 static void 362 src_put16_mem(u_int base, u_int off, u_int val) 363 { 364 *((u_short *)(base + SRC_PCI_SCA_REG(off))) = (u_short)val; 365 } 366 367 /* 368 * Probe for an ISA card. If it is there, size its memory. Then get the 369 * rest of its information and fill it in. 370 */ 371 static int 372 srprobe(struct isa_device *id) 373 { 374 struct sr_hardc *hc = &sr_hardc[id->id_unit]; 375 u_int pgs, i, tmp; 376 u_short port; 377 u_short *smem; 378 u_char mar; 379 sca_regs *sca = 0; 380 381 /* 382 * Now see if the card is realy there. 383 */ 384 hc->cardtype = SR_CRD_N2; 385 386 /* 387 * We have to fill these in early because the SRC_PUT* and SRC_GET* 388 * macros use them. 389 */ 390 hc->src_get8 = src_get8_io; 391 hc->src_get16 = src_get16_io; 392 hc->src_put8 = src_put8_io; 393 hc->src_put16 = src_put16_io; 394 395 hc->sca = 0; 396 port = id->id_iobase; 397 hc->numports = NCHAN; /* assumed # of channels on the card */ 398 399 if (id->id_flags & SR_FLAGS_NCHAN_MSK) 400 hc->numports = id->id_flags & SR_FLAGS_NCHAN_MSK; 401 402 outb(port + SR_PCR, 0); /* turn off the card */ 403 404 /* 405 * Next, we'll test the Base Address Register to retension of 406 * data... ... seeing if we're *really* talking to an N2. 407 */ 408 for (i = 0; i < 0x100; i++) { 409 outb(port + SR_BAR, i); 410 inb(port + SR_PCR); 411 tmp = inb(port + SR_BAR); 412 if (tmp != i) { 413 printf("sr%d: probe failed BAR %x, %x.\n", 414 id->id_unit, i, tmp); 415 return 0; 416 } 417 } 418 419 /* 420 * Now see if we can see the SCA. 421 */ 422 outb(port + SR_PCR, SR_PCR_SCARUN | inb(port + SR_PCR)); 423 SRC_PUT8(port, sca->wcrl, 0); 424 SRC_PUT8(port, sca->wcrm, 0); 425 SRC_PUT8(port, sca->wcrh, 0); 426 SRC_PUT8(port, sca->pcr, 0); 427 SRC_PUT8(port, sca->msci[0].tmc, 0); 428 inb(port); 429 430 tmp = SRC_GET8(port, sca->msci[0].tmc); 431 if (tmp != 0) { 432 printf("sr%d: Error reading SCA 0, %x\n", id->id_unit, tmp); 433 return 0; 434 } 435 SRC_PUT8(port, sca->msci[0].tmc, 0x5A); 436 inb(port); 437 438 tmp = SRC_GET8(port, sca->msci[0].tmc); 439 if (tmp != 0x5A) { 440 printf("sr%d: Error reading SCA 0x5A, %x\n", id->id_unit, tmp); 441 return 0; 442 } 443 SRC_PUT16(port, sca->dmac[0].cda, 0); 444 inb(port); 445 446 tmp = SRC_GET16(port, sca->dmac[0].cda); 447 if (tmp != 0) { 448 printf("sr%d: Error reading SCA 0, %x\n", id->id_unit, tmp); 449 return 0; 450 } 451 SRC_PUT16(port, sca->dmac[0].cda, 0x55AA); 452 inb(port); 453 454 tmp = SRC_GET16(port, sca->dmac[0].cda); 455 if (tmp != 0x55AA) { 456 printf("sr%d: Error reading SCA 0x55AA, %x\n", 457 id->id_unit, tmp); 458 return 0; 459 } 460 /* 461 * OK, the board's interface registers seem to work. Now we'll see 462 * if the Dual-Ported RAM is fully accessible... 463 */ 464 outb(port + SR_PCR, SR_PCR_EN_VPM | SR_PCR_ISA16); 465 outb(port + SR_PSR, SR_PSR_WIN_16K); 466 467 /* 468 * Take the kernel "virtual" address supplied to us and convert 469 * it to a "real" address. Then program the card to use that. 470 */ 471 mar = (kvtop(id->id_maddr) >> 16) & SR_PCR_16M_SEL; 472 outb(port + SR_PCR, mar | inb(port + SR_PCR)); 473 mar = kvtop(id->id_maddr) >> 12; 474 outb(port + SR_BAR, mar); 475 outb(port + SR_PCR, inb(port + SR_PCR) | SR_PCR_MEM_WIN); 476 smem = (u_short *)id->id_maddr; /* DP RAM Address */ 477 478 /* 479 * Here we will perform the memory scan to size the device. 480 * 481 * This is done by marking each potential page with a magic number. 482 * We then loop through the pages looking for that magic number. As 483 * soon as we no longer see that magic number, we'll quit the scan, 484 * knowing that no more memory is present. This provides the number 485 * of pages present on the card. 486 * 487 * Note: We're sizing 16K memory granules. 488 */ 489 for (i = 0; i <= SR_PSR_PG_SEL; i++) { 490 outb(port + SR_PSR, 491 (inb(port + SR_PSR) & ~SR_PSR_PG_SEL) | i); 492 493 *smem = 0xAA55; 494 } 495 496 for (i = 0; i <= SR_PSR_PG_SEL; i++) { 497 outb(port + SR_PSR, 498 (inb(port + SR_PSR) & ~SR_PSR_PG_SEL) | i); 499 500 if (*smem != 0xAA55) { 501 /* 502 * If we have less than 64k of memory, give up. That 503 * is 4 x 16k pages. 504 */ 505 if (i < 4) { 506 printf("sr%d: Bad mem page %d, mem %x, %x.\n", 507 id->id_unit, i, 0xAA55, *smem); 508 return 0; 509 } 510 break; 511 } 512 *smem = i; 513 } 514 515 hc->mempages = i; 516 hc->memsize = i * SRC_WIN_SIZ; 517 hc->winmsk = SRC_WIN_MSK; 518 pgs = i; /* final count of 16K pages */ 519 520 /* 521 * This next loop erases the contents of that page in DPRAM 522 */ 523 for (i = 0; i <= pgs; i++) { 524 outb(port + SR_PSR, 525 (inb(port + SR_PSR) & ~SR_PSR_PG_SEL) | i); 526 bzero(smem, SRC_WIN_SIZ); 527 } 528 529 SRC_SET_OFF(port); 530 531 /* 532 * We have a card here, fill in what we can. 533 */ 534 id->id_msize = SRC_WIN_SIZ; 535 hc->iobase = id->id_iobase; 536 hc->sca_base = id->id_iobase; 537 hc->mem_start = id->id_maddr; 538 hc->mem_end = (id->id_maddr + id->id_msize) - 1; 539 hc->mem_pstart = 0; 540 hc->cunit = id->id_unit; 541 542 /* 543 * Do a little sanity check. 544 */ 545 if (sr_irqtable[ffs(id->id_irq) - 1] == 0) 546 printf("sr%d: Warning: illegal interrupt %d chosen.\n", 547 id->id_unit, ffs(id->id_irq) - 1); 548 549 /* 550 * Bogus card configuration 551 */ 552 if ((hc->numports > NCHAN) /* only 2 ports/card */ 553 ||(hc->memsize > (512 * 1024))) /* no more than 256K */ 554 return 0; 555 556 return SRC_IO_SIZ; /* return the amount of IO addresses used. */ 557 } 558 559 /* 560 * srattach_isa and srattach_pci allocate memory for hardc, softc and 561 * data buffers. It also does any initialization that is bus specific. 562 * At the end they call the common srattach() function. 563 */ 564 static int 565 srattach_isa(struct isa_device *id) 566 { 567 u_char mar; 568 struct sr_hardc *hc = &sr_hardc[id->id_unit]; 569 570 outb(hc->iobase + SR_PCR, inb(hc->iobase + SR_PCR) | SR_PCR_SCARUN); 571 outb(hc->iobase + SR_PSR, inb(hc->iobase + SR_PSR) | SR_PSR_EN_SCA_DMA); 572 outb(hc->iobase + SR_MCR, 573 SR_MCR_DTR0 | SR_MCR_DTR1 | SR_MCR_TE0 | SR_MCR_TE1); 574 575 SRC_SET_ON(hc->iobase); 576 577 /* 578 * Configure the card. Mem address, irq, 579 */ 580 mar = (kvtop(id->id_maddr) >> 16) & SR_PCR_16M_SEL; 581 outb(hc->iobase + SR_PCR, 582 mar | (inb(hc->iobase + SR_PCR) & ~SR_PCR_16M_SEL)); 583 mar = kvtop(id->id_maddr) >> 12; 584 outb(hc->iobase + SR_BAR, mar); 585 586 /* 587 * Allocate the software interface table(s) 588 */ 589 hc->sc = malloc(hc->numports * sizeof(struct sr_softc), 590 M_DEVBUF, M_WAITOK); 591 bzero(hc->sc, hc->numports * sizeof(struct sr_softc)); 592 593 /* 594 * Get the TX clock direction and configuration. The default is a 595 * single external clock which is used by RX and TX. 596 */ 597 #ifdef N2_TEST_SPEED 598 if (sr_test_speed[0] > 0) 599 hc->sc[0].clk_cfg = SR_FLAGS_INT_CLK; 600 else if (id->id_flags & SR_FLAGS_0_CLK_MSK) 601 hc->sc[0].clk_cfg = 602 (id->id_flags & SR_FLAGS_0_CLK_MSK) 603 >> SR_FLAGS_CLK_SHFT; 604 #else 605 if (id->id_flags & SR_FLAGS_0_CLK_MSK) 606 hc->sc[0].clk_cfg = 607 (id->id_flags & SR_FLAGS_0_CLK_MSK) 608 >> SR_FLAGS_CLK_SHFT; 609 #endif 610 611 if (hc->numports == 2) 612 #ifdef N2_TEST_SPEED 613 if (sr_test_speed[1] > 0) 614 hc->sc[0].clk_cfg = SR_FLAGS_INT_CLK; 615 else 616 #endif 617 if (id->id_flags & SR_FLAGS_1_CLK_MSK) 618 hc->sc[1].clk_cfg = (id->id_flags & SR_FLAGS_1_CLK_MSK) 619 >> (SR_FLAGS_CLK_SHFT + SR_FLAGS_CLK_CHAN_SHFT); 620 621 return srattach(hc); 622 } 623 624 struct sr_hardc * 625 srattach_pci(int unit, vm_offset_t plx_vaddr, vm_offset_t sca_vaddr) 626 { 627 int numports, pndx; 628 u_int fecr, *fecrp = (u_int *)(sca_vaddr + SR_FECR); 629 struct sr_hardc *hc, **hcp; 630 631 /* 632 * Configure the PLX. This is magic. I'm doing it just like I'm told 633 * to. :-) 634 * 635 * offset 636 * 0x00 - Map Range - Mem-mapped to locate anywhere 637 * 0x04 - Re-Map - PCI address decode enable 638 * 0x18 - Bus Region - 32-bit bus, ready enable 639 * 0x1c - Master Range - include all 16 MB 640 * 0x20 - Master RAM - Map SCA Base at 0 641 * 0x28 - Master Remap - direct master memory enable 642 * 0x68 - Interrupt - Enable interrupt (0 to disable) 643 * 644 * Note: This is "cargo cult" stuff. - jrc 645 */ 646 *((u_int *)(plx_vaddr + 0x00)) = 0xfffff000; 647 *((u_int *)(plx_vaddr + 0x04)) = 1; 648 *((u_int *)(plx_vaddr + 0x18)) = 0x40030043; 649 *((u_int *)(plx_vaddr + 0x1c)) = 0xff000000; 650 *((u_int *)(plx_vaddr + 0x20)) = 0; 651 *((u_int *)(plx_vaddr + 0x28)) = 0xe9; 652 *((u_int *)(plx_vaddr + 0x68)) = 0x10900; 653 654 /* 655 * Get info from card. 656 * 657 * Only look for the second port if the first exists. Too many things 658 * will break if we have only a second port. 659 */ 660 fecr = *fecrp; 661 numports = 0; 662 663 if (((fecr & SR_FECR_ID0) >> SR_FE_ID0_SHFT) != SR_FE_ID_NONE) { 664 numports++; 665 if (((fecr & SR_FECR_ID1) >> SR_FE_ID1_SHFT) != SR_FE_ID_NONE) 666 numports++; 667 } 668 if (numports == 0) 669 return NULL; 670 671 hc = sr_hardc_pci; 672 hcp = &sr_hardc_pci; 673 674 while (hc) { 675 hcp = &hc->next; 676 hc = hc->next; 677 } 678 679 hc = malloc(sizeof(struct sr_hardc), M_DEVBUF, M_WAITOK); 680 *hcp = hc; 681 bzero(hc, sizeof(struct sr_hardc)); 682 683 hc->sc = malloc(numports * sizeof(struct sr_softc), 684 M_DEVBUF, M_WAITOK); 685 bzero(hc->sc, numports * sizeof(struct sr_softc)); 686 687 hc->numports = numports; 688 hc->cunit = unit; 689 hc->cardtype = SR_CRD_N2PCI; 690 hc->plx_base = (caddr_t)plx_vaddr; 691 hc->sca_base = sca_vaddr; 692 693 hc->src_put8 = src_put8_mem; 694 hc->src_put16 = src_put16_mem; 695 hc->src_get8 = src_get8_mem; 696 hc->src_get16 = src_get16_mem; 697 698 /* 699 * Malloc area for tx and rx buffers. For now allocate SRC_WIN_SIZ 700 * (16k) for each buffer. 701 * 702 * Allocate the block below 16M because the N2pci card can only access 703 * 16M memory at a time. 704 * 705 * (We could actually allocate a contiguous block above the 16MB limit, 706 * but this would complicate card programming more than we want to 707 * right now -jrc) 708 */ 709 hc->memsize = 2 * hc->numports * SRC_WIN_SIZ; 710 hc->mem_start = contigmalloc(hc->memsize, 711 M_DEVBUF, 712 M_NOWAIT, 713 0ul, 714 0xfffffful, 715 0x10000, 716 0x1000000); 717 718 if (hc->mem_start == NULL) { 719 printf("src%d: pci: failed to allocate buffer space.\n", unit); 720 return NULL; 721 } 722 hc->winmsk = 0xffffffff; 723 hc->mem_end = (caddr_t)((u_int)hc->mem_start + hc->memsize); 724 hc->mem_pstart = kvtop(hc->mem_start); 725 bzero(hc->mem_start, hc->memsize); 726 727 for (pndx = 0; pndx < numports; pndx++) { 728 int intf_sw; 729 struct sr_softc *sc; 730 731 sc = &hc->sc[pndx]; 732 733 switch (pndx) { 734 case 1: 735 intf_sw = fecr & SR_FECR_ID1 >> SR_FE_ID1_SHFT; 736 break; 737 case 0: 738 default: 739 intf_sw = fecr & SR_FECR_ID0 >> SR_FE_ID0_SHFT; 740 } 741 742 #ifdef N2_TEST_SPEED 743 if (sr_test_speed[pndx] > 0) 744 sc->clk_cfg = SR_FLAGS_INT_CLK; 745 else 746 #endif 747 switch (intf_sw) { 748 default: 749 case SR_FE_ID_RS232: 750 case SR_FE_ID_HSSI: 751 case SR_FE_ID_RS422: 752 case SR_FE_ID_TEST: 753 break; 754 755 case SR_FE_ID_V35: 756 sc->clk_cfg = SR_FLAGS_EXT_SEP_CLK; 757 break; 758 759 case SR_FE_ID_X21: 760 sc->clk_cfg = SR_FLAGS_EXT_CLK; 761 break; 762 } 763 } 764 765 *fecrp = SR_FECR_DTR0 766 | SR_FECR_DTR1 767 | SR_FECR_TE0 768 | SR_FECR_TE1; 769 770 srattach(hc); 771 772 return hc; 773 } 774 775 /* 776 * Register the ports on the adapter. 777 * Fill in the info for each port. 778 * Attach each port to sppp and bpf. 779 */ 780 static int 781 srattach(struct sr_hardc *hc) 782 { 783 struct sr_softc *sc = hc->sc; 784 struct ifnet *ifp; 785 int unit; /* index: channel w/in card */ 786 787 /* 788 * Report Card configuration information before we start configuring 789 * each channel on the card... 790 */ 791 printf("src%d: %uK RAM (%d mempages) @ %08x-%08x, %u ports.\n", 792 hc->cunit, hc->memsize / 1024, hc->mempages, 793 (u_int)hc->mem_start, (u_int)hc->mem_end, hc->numports); 794 795 src_init(hc); 796 sr_init_sca(hc); 797 798 /* 799 * Now configure each port on the card. 800 */ 801 for (unit = 0; unit < hc->numports; sc++, unit++) { 802 sc->hc = hc; 803 sc->subunit = unit; 804 sc->unit = next_sc_unit; 805 next_sc_unit++; 806 sc->scachan = unit % NCHAN; 807 808 sr_init_rx_dmac(sc); 809 sr_init_tx_dmac(sc); 810 sr_init_msci(sc); 811 812 ifp = &sc->ifsppp.pp_if; 813 ifp->if_softc = sc; 814 ifp->if_unit = sc->unit; 815 ifp->if_name = "sr"; 816 ifp->if_mtu = PP_MTU; 817 ifp->if_flags = IFF_POINTOPOINT | IFF_MULTICAST; 818 ifp->if_ioctl = srioctl; 819 ifp->if_start = srstart; 820 ifp->if_watchdog = srwatchdog; 821 822 printf("sr%d: Adapter %d, port %d.\n", 823 sc->unit, hc->cunit, sc->subunit); 824 825 /* 826 * Despite the fact that we want to allow both PPP *and* 827 * Frame Relay access to a channel, due to the architecture 828 * of the system, we'll have to do the attach here. 829 * 830 * At some point I'll defer the attach to the "up" call and 831 * have the attach/detach performed when the interface is 832 * up/downed... 833 */ 834 sc->attached = 0; 835 sc->protocol = N2_USE_PPP; /* default protocol */ 836 837 #if 0 838 sc->ifsppp.pp_flags = PP_KEEPALIVE; 839 sppp_attach((struct ifnet *)&sc->ifsppp); 840 #endif 841 842 if_attach(ifp); 843 844 #if NBPFILTER > 0 845 bpfattach(ifp, DLT_PPP, PPP_HEADER_LEN); 846 #endif 847 } 848 849 if (hc->mempages) 850 SRC_SET_OFF(hc->iobase); 851 852 return 1; 853 } 854 855 /* 856 * N2 Interrupt Service Routine 857 * 858 * First figure out which SCA gave the interrupt. 859 * Process it. 860 * See if there is other interrupts pending. 861 * Repeat until there no interrupts remain. 862 */ 863 void 864 srintr(int unit) 865 { 866 struct sr_hardc *hc; 867 868 hc = &sr_hardc[unit]; 869 srintr_hc(hc); 870 871 return; 872 } 873 874 void 875 srintr_hc(struct sr_hardc *hc) 876 { 877 sca_regs *sca = hc->sca; /* MSCI register tree */ 878 u_char isr0, isr1, isr2; /* interrupt statii captured */ 879 880 #if BUGGY > 1 881 printf("sr: srintr_hc(hc=%08x)\n", hc); 882 #endif 883 884 /* 885 * Since multiple interfaces may share this interrupt, we must loop 886 * until no interrupts are still pending service. 887 */ 888 while (1) { 889 /* 890 * Read all three interrupt status registers from the N2 891 * card... 892 */ 893 isr0 = SRC_GET8(hc->sca_base, sca->isr0); 894 isr1 = SRC_GET8(hc->sca_base, sca->isr1); 895 isr2 = SRC_GET8(hc->sca_base, sca->isr2); 896 897 /* 898 * If all three registers returned 0, we've finished 899 * processing interrupts from this device, so we can quit 900 * this loop... 901 */ 902 if ((isr0 | isr1 | isr2) == 0) 903 break; 904 905 #if BUGGY > 2 906 printf("src%d: srintr_hc isr0 %x, isr1 %x, isr2 %x\n", 907 unit, isr0, isr1, isr2); 908 #endif 909 910 /* 911 * Now we can dispatch the interrupts. Since we don't expect 912 * either MSCI or timer interrupts, we'll test for DMA 913 * interrupts first... 914 */ 915 if (isr1) /* DMA-initiated interrupt */ 916 sr_dmac_intr(hc, isr1); 917 918 if (isr0) /* serial part IRQ? */ 919 sr_msci_intr(hc, isr0); 920 921 if (isr2) /* timer-initiated interrupt */ 922 sr_timer_intr(hc, isr2); 923 } 924 } 925 926 /* 927 * This will only start the transmitter. It is assumed that the data 928 * is already there. 929 * It is normally called from srstart() or sr_dmac_intr(). 930 */ 931 static void 932 sr_xmit(struct sr_softc *sc) 933 { 934 u_short cda_value; /* starting descriptor */ 935 u_short eda_value; /* ending descriptor */ 936 struct sr_hardc *hc; 937 struct ifnet *ifp; /* O/S Network Services */ 938 dmac_channel *dmac; /* DMA channel registers */ 939 940 #if BUGGY > 0 941 printf("sr: sr_xmit( sc=%08x)\n", sc); 942 #endif 943 944 hc = sc->hc; 945 ifp = &sc->ifsppp.pp_if; 946 dmac = &hc->sca->dmac[DMAC_TXCH(sc->scachan)]; 947 948 /* 949 * Get the starting and ending addresses of the chain to be 950 * transmitted and pass these on to the DMA engine on-chip. 951 */ 952 cda_value = sc->block[sc->txb_next_tx].txdesc + hc->mem_pstart; 953 cda_value &= 0x00ffff; 954 eda_value = sc->block[sc->txb_next_tx].txeda + hc->mem_pstart; 955 eda_value &= 0x00ffff; 956 957 SRC_PUT16(hc->sca_base, dmac->cda, cda_value); 958 SRC_PUT16(hc->sca_base, dmac->eda, eda_value); 959 960 /* 961 * Now we'll let the DMA status register know about this change 962 */ 963 SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE); 964 965 sc->xmit_busy = 1; /* mark transmitter busy */ 966 967 #if BUGGY > 2 968 printf("sr%d: XMIT cda=%04x, eda=%4x, rcda=%08lx\n", 969 sc->unit, cda_value, eda_value, 970 sc->block[sc->txb_next_tx].txdesc + hc->mem_pstart); 971 #endif 972 973 sc->txb_next_tx++; /* update next transmit seq# */ 974 975 if (sc->txb_next_tx == SR_TX_BLOCKS) /* handle wrap... */ 976 sc->txb_next_tx = 0; 977 978 /* 979 * Finally, we'll set a timout (which will start srwatchdog()) 980 * within the O/S network services layer... 981 */ 982 ifp->if_timer = 2; /* Value in seconds. */ 983 } 984 985 /* 986 * This function will be called from the upper level when a user add a 987 * packet to be send, and from the interrupt handler after a finished 988 * transmit. 989 * 990 * NOTE: it should run at spl_imp(). 991 * 992 * This function only place the data in the oncard buffers. It does not 993 * start the transmition. sr_xmit() does that. 994 * 995 * Transmitter idle state is indicated by the IFF_OACTIVE flag. 996 * The function that clears that should ensure that the transmitter 997 * and it's DMA is in a "good" idle state. 998 */ 999 static void 1000 srstart(struct ifnet *ifp) 1001 { 1002 struct sr_softc *sc; /* channel control structure */ 1003 struct sr_hardc *hc; /* card control/config block */ 1004 int len; /* total length of a packet */ 1005 int pkts; /* packets placed in DPRAM */ 1006 int tlen; /* working length of pkt */ 1007 u_int i; 1008 struct mbuf *mtx; /* message buffer from O/S */ 1009 u_char *txdata; /* buffer address in DPRAM */ 1010 sca_descriptor *txdesc; /* working descriptor pointr */ 1011 struct buf_block *blkp; 1012 1013 #if BUGGY > 0 1014 printf("sr: srstart( ifp=%08x)\n", ifp); 1015 #endif 1016 1017 sc = ifp->if_softc; 1018 hc = sc->hc; 1019 1020 if ((ifp->if_flags & IFF_RUNNING) == 0) 1021 return; 1022 1023 /* 1024 * It is OK to set the memory window outside the loop because all tx 1025 * buffers and descriptors are assumed to be in the same 16K window. 1026 */ 1027 if (hc->mempages) { 1028 SRC_SET_ON(hc->iobase); 1029 SRC_SET_MEM(hc->iobase, sc->block[0].txdesc); 1030 } 1031 1032 /* 1033 * Loop to place packets into DPRAM. 1034 * 1035 * We stay in this loop until there is nothing in 1036 * the TX queue left or the tx buffers are full. 1037 */ 1038 top_srstart: 1039 1040 /* 1041 * See if we have space for more packets. 1042 */ 1043 if (sc->txb_inuse == SR_TX_BLOCKS) { /* out of space? */ 1044 ifp->if_flags |= IFF_OACTIVE; /* yes, mark active */ 1045 1046 if (hc->mempages) 1047 SRC_SET_OFF(hc->iobase); 1048 1049 #if BUGGY > 9 1050 printf("sr%d.srstart: sc->txb_inuse=%d; DPRAM full...\n", 1051 sc->unit, sc->txb_inuse); 1052 #endif 1053 return; 1054 } 1055 /* 1056 * OK, the card can take more traffic. Let's see if there's any 1057 * pending from the system... 1058 * 1059 * NOTE: 1060 * The architecture of the networking interface doesn't 1061 * actually call us like 'write()', providing an address. We get 1062 * started, a lot like a disk strategy routine, and we actually call 1063 * back out to the system to get traffic to send... 1064 * 1065 * NOTE: 1066 * If we were gonna run through another layer, we would use a 1067 * dispatch table to select the service we're getting a packet 1068 * from... 1069 */ 1070 switch (sc->protocol) { 1071 #if NFR > 0 1072 case N2_USE_FRP: 1073 mtx = fr_dequeue(ifp); 1074 break; 1075 #endif 1076 case N2_USE_PPP: 1077 default: 1078 mtx = sppp_dequeue(ifp); 1079 } 1080 1081 if (!mtx) { 1082 if (hc->mempages) 1083 SRC_SET_OFF(hc->iobase); 1084 return; 1085 } 1086 /* 1087 * OK, we got a packet from the network services of the O/S. Now we 1088 * can move it into the DPRAM (under control of the descriptors) and 1089 * fire it off... 1090 */ 1091 pkts = 0; 1092 i = 0; /* counts # of granules used */ 1093 1094 blkp = &sc->block[sc->txb_new]; /* address of free granule */ 1095 txdesc = (sca_descriptor *) 1096 (hc->mem_start + (blkp->txdesc & hc->winmsk)); 1097 1098 txdata = (u_char *)(hc->mem_start 1099 + (blkp->txstart & hc->winmsk)); 1100 1101 /* 1102 * Now we'll try to install as many packets as possible into the 1103 * card's DP RAM buffers. 1104 */ 1105 for (;;) { /* perform actual copy of packet */ 1106 len = mtx->m_pkthdr.len; /* length of message */ 1107 1108 #if BUGGY > 1 1109 printf("sr%d.srstart: mbuf @ %08lx, %d bytes\n", 1110 sc->unit, mtx, len); 1111 #endif 1112 1113 #if NBPFILTER > 0 1114 if (ifp->if_bpf) 1115 bpf_mtap(ifp, mtx); 1116 #endif 1117 1118 /* 1119 * We can perform a straight copy because the tranmit 1120 * buffers won't wrap. 1121 */ 1122 m_copydata(mtx, 0, len, txdata); 1123 1124 /* 1125 * Now we know how big the message is gonna be. We must now 1126 * construct the descriptors to drive this message out... 1127 */ 1128 tlen = len; 1129 while (tlen > SR_BUF_SIZ) { /* loop for full granules */ 1130 txdesc->stat = 0; /* reset bits */ 1131 txdesc->len = SR_BUF_SIZ; /* size of granule */ 1132 tlen -= SR_BUF_SIZ; 1133 1134 txdesc++; /* move to next dscr */ 1135 txdata += SR_BUF_SIZ; /* adjust data addr */ 1136 i++; 1137 } 1138 1139 /* 1140 * This section handles the setting of the final piece of a 1141 * message. 1142 */ 1143 txdesc->stat = SCA_DESC_EOM; 1144 txdesc->len = tlen; 1145 pkts++; 1146 1147 /* 1148 * prepare for subsequent packets (if any) 1149 */ 1150 txdesc++; 1151 txdata += SR_BUF_SIZ; /* next mem granule */ 1152 i++; /* count of granules */ 1153 1154 /* 1155 * OK, we've now placed the message into the DPRAM where it 1156 * can be transmitted. We'll now release the message memory 1157 * and update the statistics... 1158 */ 1159 m_freem(mtx); 1160 ++sc->ifsppp.pp_if.if_opackets; 1161 1162 /* 1163 * Check if we have space for another packet. XXX This is 1164 * hardcoded. A packet can't be larger than 3 buffers (3 x 1165 * 512). 1166 */ 1167 if ((i + 3) >= blkp->txmax) { /* enough remains? */ 1168 #if BUGGY > 9 1169 printf("sr%d.srstart: i=%d (%d pkts); card full.\n", 1170 sc->unit, i, pkts); 1171 #endif 1172 break; 1173 } 1174 /* 1175 * We'll pull the next message to be sent (if any) 1176 */ 1177 switch (sc->protocol) { 1178 #if NFR > 0 1179 case N2_USE_FRP: 1180 mtx = fr_dequeue(ifp); 1181 break; 1182 #endif 1183 case N2_USE_PPP: 1184 default: 1185 mtx = sppp_dequeue(ifp); 1186 } 1187 1188 if (!mtx) { /* no message? We're done! */ 1189 #if BUGGY > 9 1190 printf("sr%d.srstart: pending=0, pkts=%d\n", 1191 sc->unit, pkts); 1192 #endif 1193 break; 1194 } 1195 } 1196 1197 blkp->txtail = i; /* record next free granule */ 1198 1199 /* 1200 * Mark the last descriptor, so that the SCA know where to stop. 1201 */ 1202 txdesc--; /* back up to last descriptor in list */ 1203 txdesc->stat |= SCA_DESC_EOT; /* mark as end of list */ 1204 1205 /* 1206 * Now we'll reset the transmit granule's descriptor address so we 1207 * can record this in the structure and fire it off w/ the DMA 1208 * processor of the serial chip... 1209 */ 1210 txdesc = (sca_descriptor *)blkp->txdesc; 1211 blkp->txeda = (u_short)((u_int)&txdesc[i]); 1212 1213 sc->txb_inuse++; /* update inuse status */ 1214 sc->txb_new++; /* new traffic wuz added */ 1215 1216 if (sc->txb_new == SR_TX_BLOCKS) 1217 sc->txb_new = 0; 1218 1219 /* 1220 * If the tranmitter wasn't marked as "busy" we will force it to be 1221 * started... 1222 */ 1223 if (sc->xmit_busy == 0) { 1224 sr_xmit(sc); 1225 #if BUGGY > 9 1226 printf("sr%d.srstart: called sr_xmit()\n", sc->unit); 1227 #endif 1228 } 1229 goto top_srstart; 1230 } 1231 1232 /* 1233 * Handle ioctl's at the device level, though we *will* call up 1234 * a layer... 1235 */ 1236 #if BUGGY > 2 1237 static int bug_splats[] = {0, 0, 0, 0, 0, 0, 0, 0}; 1238 #endif 1239 1240 static int 1241 srioctl(struct ifnet *ifp, int cmd, caddr_t data) 1242 { 1243 int s, error, was_up, should_be_up; 1244 struct sppp *sp = (struct sppp *)ifp; 1245 struct sr_softc *sc = ifp->if_softc; 1246 1247 #if BUGGY > 0 1248 printf("sr%d: srioctl(ifp=%08x, cmd=%08x, data=%08x)\n", 1249 ifp->if_unit, ifp, cmd, data); 1250 #endif 1251 1252 was_up = ifp->if_flags & IFF_RUNNING; 1253 1254 if (cmd == SIOCSIFFLAGS) { 1255 /* 1256 * First, handle an apparent protocol switch 1257 */ 1258 #if NFR > 0 1259 if (was_up == 0)/* can only happen if DOWN */ 1260 if (ifp->if_flags & IFF_LINK1) 1261 sc->protocol = N2_USE_FRP; 1262 else 1263 sc->protocol = N2_USE_PPP; 1264 #else 1265 sc->protocol = N2_USE_PPP; 1266 ifp->if_flags &= ~IFF_LINK1; 1267 #endif 1268 1269 /* 1270 * Next we can handle minor protocol point(s) 1271 */ 1272 if (ifp->if_flags & IFF_LINK2) 1273 sp->pp_flags |= PP_CISCO; 1274 else 1275 sp->pp_flags &= ~PP_CISCO; 1276 } 1277 /* 1278 * Next, we'll allow the network service layer we've called process 1279 * the ioctl... 1280 */ 1281 if ((sc->attached != 0) 1282 && (sc->attached != sc->protocol)) { 1283 switch (sc->attached) { 1284 #if NFR > 0 1285 case N2_USE_FRP: 1286 fr_detach(ifp); 1287 break; 1288 #endif 1289 case N2_USE_PPP: 1290 default: 1291 sppp_detach(ifp); 1292 sc->ifsppp.pp_flags &= ~PP_KEEPALIVE; 1293 } 1294 1295 sc->attached = 0; 1296 } 1297 if (sc->attached == 0) { 1298 switch (sc->protocol) { 1299 #if NFR > 0 1300 case N2_USE_FRP: 1301 fr_attach(&sc->ifsppp.pp_if); 1302 break; 1303 #endif 1304 case N2_USE_PPP: 1305 default: 1306 sc->ifsppp.pp_flags |= PP_KEEPALIVE; 1307 sppp_attach(&sc->ifsppp.pp_if); 1308 } 1309 1310 sc->attached = sc->protocol; 1311 } 1312 switch (sc->protocol) { 1313 #if NFR > 0 1314 case N2_USE_FRP: 1315 error = fr_ioctl(ifp, cmd, data); 1316 break; 1317 #endif 1318 case N2_USE_PPP: 1319 default: 1320 error = sppp_ioctl(ifp, cmd, data); 1321 } 1322 1323 #if BUGGY > 1 1324 printf("sr%d: ioctl: ifsppp.pp_flags = %08x, if_flags %08x.\n", 1325 ifp->if_unit, ((struct sppp *)ifp)->pp_flags, ifp->if_flags); 1326 #endif 1327 1328 if (error) 1329 return error; 1330 1331 if ((cmd != SIOCSIFFLAGS) && (cmd != SIOCSIFADDR)) { 1332 #if BUGGY > 2 1333 if (bug_splats[sc->unit]++ < 2) { 1334 printf("sr(%d).if_addrlist = %08x\n", 1335 sc->unit, ifp->if_addrlist); 1336 printf("sr(%d).if_bpf = %08x\n", 1337 sc->unit, ifp->if_bpf); 1338 printf("sr(%d).if_init = %08x\n", 1339 sc->unit, ifp->if_init); 1340 printf("sr(%d).if_output = %08x\n", 1341 sc->unit, ifp->if_output); 1342 printf("sr(%d).if_start = %08x\n", 1343 sc->unit, ifp->if_start); 1344 printf("sr(%d).if_done = %08x\n", 1345 sc->unit, ifp->if_done); 1346 printf("sr(%d).if_ioctl = %08x\n", 1347 sc->unit, ifp->if_ioctl); 1348 printf("sr(%d).if_reset = %08x\n", 1349 sc->unit, ifp->if_reset); 1350 printf("sr(%d).if_watchdog = %08x\n", 1351 sc->unit, ifp->if_watchdog); 1352 } 1353 #endif 1354 return 0; 1355 } 1356 1357 s = splimp(); 1358 should_be_up = ifp->if_flags & IFF_RUNNING; 1359 1360 if (!was_up && should_be_up) { 1361 /* 1362 * Interface should be up -- start it. 1363 */ 1364 sr_up(sc); 1365 srstart(ifp); 1366 1367 /* 1368 * XXX Clear the IFF_UP flag so that the link will only go 1369 * up after sppp lcp and ipcp negotiation. 1370 */ 1371 ifp->if_flags &= ~IFF_UP; 1372 } else if (was_up && !should_be_up) { 1373 /* 1374 * Interface should be down -- stop it. 1375 */ 1376 sr_down(sc); 1377 switch (sc->protocol) { 1378 #if NFR > 0 1379 case N2_USE_FRP: 1380 fr_flush(ifp); 1381 break; 1382 #endif 1383 case N2_USE_PPP: 1384 default: 1385 sppp_flush(ifp); 1386 } 1387 } 1388 splx(s); 1389 1390 #if BUGGY > 2 1391 if (bug_splats[sc->unit]++ < 2) { 1392 printf("sr(%d).if_addrlist = %08x\n", 1393 sc->unit, ifp->if_addrlist); 1394 printf("sr(%d).if_bpf = %08x\n", 1395 sc->unit, ifp->if_bpf); 1396 printf("sr(%d).if_init = %08x\n", 1397 sc->unit, ifp->if_init); 1398 printf("sr(%d).if_output = %08x\n", 1399 sc->unit, ifp->if_output); 1400 printf("sr(%d).if_start = %08x\n", 1401 sc->unit, ifp->if_start); 1402 printf("sr(%d).if_done = %08x\n", 1403 sc->unit, ifp->if_done); 1404 printf("sr(%d).if_ioctl = %08x\n", 1405 sc->unit, ifp->if_ioctl); 1406 printf("sr(%d).if_reset = %08x\n", 1407 sc->unit, ifp->if_reset); 1408 printf("sr(%d).if_watchdog = %08x\n", 1409 sc->unit, ifp->if_watchdog); 1410 } 1411 #endif 1412 1413 return 0; 1414 } 1415 1416 /* 1417 * This is to catch lost tx interrupts. 1418 */ 1419 static void 1420 srwatchdog(struct ifnet *ifp) 1421 { 1422 int got_st0, got_st1, got_st3, got_dsr; 1423 struct sr_softc *sc = ifp->if_softc; 1424 struct sr_hardc *hc = sc->hc; 1425 msci_channel *msci = &hc->sca->msci[sc->scachan]; 1426 dmac_channel *dmac = &sc->hc->sca->dmac[sc->scachan]; 1427 1428 #if BUGGY > 0 1429 printf("srwatchdog(unit=%d)\n", unit); 1430 #endif 1431 1432 if (!(ifp->if_flags & IFF_RUNNING)) 1433 return; 1434 1435 ifp->if_oerrors++; /* update output error count */ 1436 1437 got_st0 = SRC_GET8(hc->sca_base, msci->st0); 1438 got_st1 = SRC_GET8(hc->sca_base, msci->st1); 1439 got_st3 = SRC_GET8(hc->sca_base, msci->st3); 1440 got_dsr = SRC_GET8(hc->sca_base, dmac->dsr); 1441 1442 #if 0 1443 if (ifp->if_flags & IFF_DEBUG) 1444 #endif 1445 printf("sr%d: transmit failed, " 1446 "ST0 %02x, ST1 %02x, ST3 %02x, DSR %02x.\n", 1447 sc->unit, 1448 got_st0, got_st1, got_st3, got_dsr); 1449 1450 if (SRC_GET8(hc->sca_base, msci->st1) & SCA_ST1_UDRN) { 1451 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXABORT); 1452 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXENABLE); 1453 SRC_PUT8(hc->sca_base, msci->st1, SCA_ST1_UDRN); 1454 } 1455 sc->xmit_busy = 0; 1456 ifp->if_flags &= ~IFF_OACTIVE; 1457 1458 if (sc->txb_inuse && --sc->txb_inuse) 1459 sr_xmit(sc); 1460 1461 srstart(ifp); /* restart transmitter */ 1462 } 1463 1464 static void 1465 sr_up(struct sr_softc *sc) 1466 { 1467 u_int *fecrp; 1468 struct sr_hardc *hc = sc->hc; 1469 sca_regs *sca = hc->sca; 1470 msci_channel *msci = &sca->msci[sc->scachan]; 1471 1472 #if BUGGY > 0 1473 printf("sr_up(sc=%08x)\n", sc); 1474 #endif 1475 1476 /* 1477 * This section should really do the attach to the appropriate 1478 * system service, be it frame relay or PPP... 1479 */ 1480 if (sc->attached == 0) { 1481 switch (sc->protocol) { 1482 #if NFR > 0 1483 case N2_USE_FRP: 1484 fr_attach(&sc->ifsppp.pp_if); 1485 break; 1486 #endif 1487 case N2_USE_PPP: 1488 default: 1489 sc->ifsppp.pp_flags |= PP_KEEPALIVE; 1490 sppp_attach(&sc->ifsppp.pp_if); 1491 } 1492 1493 sc->attached = sc->protocol; 1494 } 1495 1496 /* 1497 * Enable transmitter and receiver. Raise DTR and RTS. Enable 1498 * interrupts. 1499 * 1500 * XXX What about using AUTO mode in msci->md0 ??? 1501 */ 1502 SRC_PUT8(hc->sca_base, msci->ctl, 1503 SRC_GET8(hc->sca_base, msci->ctl) & ~SCA_CTL_RTS); 1504 1505 if (sc->scachan == 0) 1506 switch (hc->cardtype) { 1507 case SR_CRD_N2: 1508 outb(hc->iobase + SR_MCR, 1509 (inb(hc->iobase + SR_MCR) & ~SR_MCR_DTR0)); 1510 break; 1511 case SR_CRD_N2PCI: 1512 fecrp = (u_int *)(hc->sca_base + SR_FECR); 1513 *fecrp &= ~SR_FECR_DTR0; 1514 break; 1515 } 1516 else 1517 switch (hc->cardtype) { 1518 case SR_CRD_N2: 1519 outb(hc->iobase + SR_MCR, 1520 (inb(hc->iobase + SR_MCR) & ~SR_MCR_DTR1)); 1521 break; 1522 case SR_CRD_N2PCI: 1523 fecrp = (u_int *)(hc->sca_base + SR_FECR); 1524 *fecrp &= ~SR_FECR_DTR1; 1525 break; 1526 } 1527 1528 if (sc->scachan == 0) { 1529 SRC_PUT8(hc->sca_base, sca->ier0, 1530 SRC_GET8(hc->sca_base, sca->ier0) | 0x000F); 1531 SRC_PUT8(hc->sca_base, sca->ier1, 1532 SRC_GET8(hc->sca_base, sca->ier1) | 0x000F); 1533 } else { 1534 SRC_PUT8(hc->sca_base, sca->ier0, 1535 SRC_GET8(hc->sca_base, sca->ier0) | 0x00F0); 1536 SRC_PUT8(hc->sca_base, sca->ier1, 1537 SRC_GET8(hc->sca_base, sca->ier1) | 0x00F0); 1538 } 1539 1540 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXENABLE); 1541 inb(hc->iobase); /* XXX slow it down a bit. */ 1542 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXENABLE); 1543 1544 #ifdef USE_MODEMCK 1545 if (sr_watcher == 0) 1546 sr_modemck(NULL); 1547 #endif 1548 } 1549 1550 static void 1551 sr_down(struct sr_softc *sc) 1552 { 1553 u_int *fecrp; 1554 struct sr_hardc *hc = sc->hc; 1555 sca_regs *sca = hc->sca; 1556 msci_channel *msci = &sca->msci[sc->scachan]; 1557 1558 #if BUGGY > 0 1559 printf("sr_down(sc=%08x)\n", sc); 1560 #endif 1561 1562 /* 1563 * Disable transmitter and receiver. Lower DTR and RTS. Disable 1564 * interrupts. 1565 */ 1566 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXDISABLE); 1567 inb(hc->iobase); /* XXX slow it down a bit. */ 1568 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXDISABLE); 1569 1570 SRC_PUT8(hc->sca_base, msci->ctl, 1571 SRC_GET8(hc->sca_base, msci->ctl) | SCA_CTL_RTS); 1572 1573 if (sc->scachan == 0) 1574 switch (hc->cardtype) { 1575 case SR_CRD_N2: 1576 outb(hc->iobase + SR_MCR, 1577 (inb(hc->iobase + SR_MCR) | SR_MCR_DTR0)); 1578 break; 1579 case SR_CRD_N2PCI: 1580 fecrp = (u_int *)(hc->sca_base + SR_FECR); 1581 *fecrp |= SR_FECR_DTR0; 1582 break; 1583 } 1584 else 1585 switch (hc->cardtype) { 1586 case SR_CRD_N2: 1587 outb(hc->iobase + SR_MCR, 1588 (inb(hc->iobase + SR_MCR) | SR_MCR_DTR1)); 1589 break; 1590 case SR_CRD_N2PCI: 1591 fecrp = (u_int *)(hc->sca_base + SR_FECR); 1592 *fecrp |= SR_FECR_DTR1; 1593 break; 1594 } 1595 1596 if (sc->scachan == 0) { 1597 SRC_PUT8(hc->sca_base, sca->ier0, 1598 SRC_GET8(hc->sca_base, sca->ier0) & ~0x0F); 1599 SRC_PUT8(hc->sca_base, sca->ier1, 1600 SRC_GET8(hc->sca_base, sca->ier1) & ~0x0F); 1601 } else { 1602 SRC_PUT8(hc->sca_base, sca->ier0, 1603 SRC_GET8(hc->sca_base, sca->ier0) & ~0xF0); 1604 SRC_PUT8(hc->sca_base, sca->ier1, 1605 SRC_GET8(hc->sca_base, sca->ier1) & ~0xF0); 1606 } 1607 1608 /* 1609 * This section does the detach from the currently configured net 1610 * service, be it frame relay or PPP... 1611 */ 1612 switch (sc->protocol) { 1613 #if NFR > 0 1614 case N2_USE_FRP: 1615 fr_detach(&sc->ifsppp.pp_if); 1616 break; 1617 #endif 1618 case N2_USE_PPP: 1619 default: 1620 sppp_detach(&sc->ifsppp.pp_if); 1621 } 1622 1623 sc->attached = 0; 1624 } 1625 1626 /* 1627 * Initialize the card, allocate memory for the sr_softc structures 1628 * and fill in the pointers. 1629 */ 1630 static void 1631 src_init(struct sr_hardc *hc) 1632 { 1633 struct sr_softc *sc = hc->sc; 1634 int x; 1635 u_int chanmem; 1636 u_int bufmem; 1637 u_int next; 1638 u_int descneeded; 1639 1640 #if BUGGY > 0 1641 printf("src_init(hc=%08x)\n", hc); 1642 #endif 1643 1644 chanmem = hc->memsize / hc->numports; 1645 next = 0; 1646 1647 for (x = 0; x < hc->numports; x++, sc++) { 1648 int blk; 1649 1650 for (blk = 0; blk < SR_TX_BLOCKS; blk++) { 1651 sc->block[blk].txdesc = next; 1652 bufmem = (16 * 1024) / SR_TX_BLOCKS; 1653 descneeded = bufmem / SR_BUF_SIZ; 1654 1655 sc->block[blk].txstart = sc->block[blk].txdesc 1656 + ((((descneeded * sizeof(sca_descriptor)) 1657 / SR_BUF_SIZ) + 1) 1658 * SR_BUF_SIZ); 1659 1660 sc->block[blk].txend = next + bufmem; 1661 sc->block[blk].txmax = 1662 (sc->block[blk].txend - sc->block[blk].txstart) 1663 / SR_BUF_SIZ; 1664 next += bufmem; 1665 1666 #if BUGGY > 2 1667 printf("sr%d: blk %d: txdesc %08x, txstart %08x\n", 1668 sc->unit, blk, 1669 sc->block[blk].txdesc, sc->block[blk].txstart); 1670 #endif 1671 } 1672 1673 sc->rxdesc = next; 1674 bufmem = chanmem - (bufmem * SR_TX_BLOCKS); 1675 descneeded = bufmem / SR_BUF_SIZ; 1676 sc->rxstart = sc->rxdesc + 1677 ((((descneeded * sizeof(sca_descriptor)) / 1678 SR_BUF_SIZ) + 1) * SR_BUF_SIZ); 1679 sc->rxend = next + bufmem; 1680 sc->rxmax = (sc->rxend - sc->rxstart) / SR_BUF_SIZ; 1681 next += bufmem; 1682 } 1683 } 1684 1685 /* 1686 * The things done here are channel independent. 1687 * 1688 * Configure the sca waitstates. 1689 * Configure the global interrupt registers. 1690 * Enable master dma enable. 1691 */ 1692 static void 1693 sr_init_sca(struct sr_hardc *hc) 1694 { 1695 sca_regs *sca = hc->sca; 1696 1697 #if BUGGY > 0 1698 printf("sr_init_sca(hc=%08x)\n", hc); 1699 #endif 1700 1701 /* 1702 * Do the wait registers. Set everything to 0 wait states. 1703 */ 1704 SRC_PUT8(hc->sca_base, sca->pabr0, 0); 1705 SRC_PUT8(hc->sca_base, sca->pabr1, 0); 1706 SRC_PUT8(hc->sca_base, sca->wcrl, 0); 1707 SRC_PUT8(hc->sca_base, sca->wcrm, 0); 1708 SRC_PUT8(hc->sca_base, sca->wcrh, 0); 1709 1710 /* 1711 * Configure the interrupt registers. Most are cleared until the 1712 * interface is configured. 1713 */ 1714 SRC_PUT8(hc->sca_base, sca->ier0, 0x00); /* MSCI interrupts. */ 1715 SRC_PUT8(hc->sca_base, sca->ier1, 0x00); /* DMAC interrupts */ 1716 SRC_PUT8(hc->sca_base, sca->ier2, 0x00); /* TIMER interrupts. */ 1717 SRC_PUT8(hc->sca_base, sca->itcr, 0x00); /* Use ivr and no intr 1718 * ack */ 1719 SRC_PUT8(hc->sca_base, sca->ivr, 0x40); /* Interrupt vector. */ 1720 SRC_PUT8(hc->sca_base, sca->imvr, 0x40); 1721 1722 /* 1723 * Configure the timers. XXX Later 1724 */ 1725 1726 /* 1727 * Set the DMA channel priority to rotate between all four channels. 1728 * 1729 * Enable all dma channels. 1730 */ 1731 SRC_PUT8(hc->sca_base, sca->pcr, SCA_PCR_PR2); 1732 SRC_PUT8(hc->sca_base, sca->dmer, SCA_DMER_EN); 1733 } 1734 1735 /* 1736 * Configure the msci 1737 * 1738 * NOTE: The serial port configuration is hardcoded at the moment. 1739 */ 1740 static void 1741 sr_init_msci(struct sr_softc *sc) 1742 { 1743 int portndx; /* on-board port number */ 1744 u_int mcr_v; /* contents of modem control */ 1745 u_int *fecrp; /* pointer for PCI's MCR i/o */ 1746 struct sr_hardc *hc = sc->hc; 1747 msci_channel *msci = &hc->sca->msci[sc->scachan]; 1748 #ifdef N2_TEST_SPEED 1749 int br_v; /* contents for BR divisor */ 1750 int etcndx; /* index into ETC table */ 1751 int fifo_v, gotspeed; /* final tabled speed found */ 1752 int tmc_v; /* timer control register */ 1753 int wanted; /* speed (bitrate) wanted... */ 1754 struct rate_line *rtp; 1755 #endif 1756 1757 portndx = sc->scachan; 1758 1759 #if BUGGY > 0 1760 printf("sr: sr_init_msci( sc=%08x)\n", sc); 1761 #endif 1762 1763 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RESET); 1764 SRC_PUT8(hc->sca_base, msci->md0, SCA_MD0_CRC_1 | 1765 SCA_MD0_CRC_CCITT | 1766 SCA_MD0_CRC_ENABLE | 1767 SCA_MD0_MODE_HDLC); 1768 SRC_PUT8(hc->sca_base, msci->md1, SCA_MD1_NOADDRCHK); 1769 SRC_PUT8(hc->sca_base, msci->md2, SCA_MD2_DUPLEX | SCA_MD2_NRZ); 1770 1771 /* 1772 * According to the manual I should give a reset after changing the 1773 * mode registers. 1774 */ 1775 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXRESET); 1776 SRC_PUT8(hc->sca_base, msci->ctl, SCA_CTL_IDLPAT | 1777 SCA_CTL_UDRNC | 1778 SCA_CTL_RTS); 1779 1780 /* 1781 * XXX Later we will have to support different clock settings. 1782 */ 1783 switch (sc->clk_cfg) { 1784 default: 1785 #if BUGGY > 0 1786 printf("sr%: clk_cfg=%08x, selected default clock.\n", 1787 portndx, sc->clk_cfg); 1788 #endif 1789 /* FALLTHROUGH */ 1790 case SR_FLAGS_EXT_CLK: 1791 /* 1792 * For now all interfaces are programmed to use the RX clock 1793 * for the TX clock. 1794 */ 1795 1796 #if BUGGY > 0 1797 printf("sr%d: External Clock Selected.\n", portndx); 1798 #endif 1799 1800 SRC_PUT8(hc->sca_base, msci->rxs, 0); 1801 SRC_PUT8(hc->sca_base, msci->txs, 0); 1802 break; 1803 1804 case SR_FLAGS_EXT_SEP_CLK: 1805 #if BUGGY > 0 1806 printf("sr%d: Split Clocking Selected.\n", portndx); 1807 #endif 1808 1809 #if 1 1810 SRC_PUT8(hc->sca_base, msci->rxs, 0); 1811 SRC_PUT8(hc->sca_base, msci->txs, 0); 1812 #else 1813 SRC_PUT8(hc->sca_base, msci->rxs, 1814 SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1); 1815 1816 /* 1817 * We need to configure the internal bit clock for the 1818 * transmitter's channel... 1819 */ 1820 SRC_PUT8(hc->sca_base, msci->txs, 1821 SCA_TXS_CLK_RX | SCA_TXS_DIV1); 1822 #endif 1823 break; 1824 1825 case SR_FLAGS_INT_CLK: 1826 #if BUGGY > 0 1827 printf("sr%d: Internal Clocking selected.\n", portndx); 1828 #endif 1829 1830 /* 1831 * XXX I do need some code to set the baud rate here! 1832 */ 1833 #ifdef N2_TEST_SPEED 1834 switch (hc->cardtype) { 1835 case SR_CRD_N2PCI: 1836 fecrp = (u_int *)(hc->sca_base + SR_FECR); 1837 mcr_v = *fecrp; 1838 etcndx = 2; 1839 break; 1840 case SR_CRD_N2: 1841 default: 1842 mcr_v = inb(hc->iobase + SR_MCR); 1843 etcndx = 0; 1844 } 1845 1846 fifo_v = 0x10; /* stolen from Linux version */ 1847 1848 /* 1849 * search for appropriate speed in table, don't calc it: 1850 */ 1851 wanted = sr_test_speed[portndx]; 1852 rtp = &n2_rates[0]; /* point to first table item */ 1853 1854 while ((rtp->target > 0) /* search table for speed */ 1855 &&(rtp->target != wanted)) 1856 rtp++; 1857 1858 /* 1859 * We've searched the table for a matching speed. If we've 1860 * found the correct rate line, we'll get the pre-calc'd 1861 * values for the TMC and baud rate divisor for subsequent 1862 * use... 1863 */ 1864 if (rtp->target > 0) { /* use table-provided values */ 1865 gotspeed = wanted; 1866 tmc_v = rtp->tmc_reg; 1867 br_v = rtp->br_reg; 1868 } else { /* otherwise assume 1MBit comm rate */ 1869 gotspeed = 10000; 1870 tmc_v = 5; 1871 br_v = 1; 1872 } 1873 1874 /* 1875 * Now we mask in the enable clock output for the MCR: 1876 */ 1877 mcr_v |= etc0vals[etcndx + portndx]; 1878 1879 /* 1880 * Now we'll program the registers with these speed- related 1881 * contents... 1882 */ 1883 SRC_PUT8(hc->sca_base, msci->tmc, tmc_v); 1884 SRC_PUT8(hc->sca_base, msci->trc0, fifo_v); 1885 SRC_PUT8(hc->sca_base, msci->rxs, SCA_RXS_CLK_INT + br_v); 1886 SRC_PUT8(hc->sca_base, msci->txs, SCA_TXS_CLK_INT + br_v); 1887 1888 switch (hc->cardtype) { 1889 case SR_CRD_N2PCI: 1890 *fecrp = mcr_v; 1891 break; 1892 case SR_CRD_N2: 1893 default: 1894 outb(hc->iobase + SR_MCR, mcr_v); 1895 } 1896 1897 #if BUGGY > 0 1898 if (wanted != gotspeed) 1899 printf("sr%d: Speed wanted=%d, found=%d\n", 1900 wanted, gotspeed); 1901 1902 printf("sr%d: Internal Clock %dx100 BPS, tmc=%d, div=%d\n", 1903 portndx, gotspeed, tmc_v, br_v); 1904 #endif 1905 #else 1906 SRC_PUT8(hc->sca_base, msci->rxs, 1907 SCA_RXS_CLK_INT | SCA_RXS_DIV1); 1908 SRC_PUT8(hc->sca_base, msci->txs, 1909 SCA_TXS_CLK_INT | SCA_TXS_DIV1); 1910 1911 SRC_PUT8(hc->sca_base, msci->tmc, 5); 1912 1913 if (portndx == 0) 1914 switch (hc->cardtype) { 1915 case SR_CRD_N2PCI: 1916 fecrp = (u_int *)(hc->sca_base + SR_FECR); 1917 *fecrp |= SR_FECR_ETC0; 1918 break; 1919 case SR_CRD_N2: 1920 default: 1921 mcr_v = inb(hc->iobase + SR_MCR); 1922 mcr_v |= SR_MCR_ETC0; 1923 outb(hc->iobase + SR_MCR, mcr_v); 1924 } 1925 else 1926 switch (hc->cardtype) { 1927 case SR_CRD_N2: 1928 mcr_v = inb(hc->iobase + SR_MCR); 1929 mcr_v |= SR_MCR_ETC1; 1930 outb(hc->iobase + SR_MCR, mcr_v); 1931 break; 1932 case SR_CRD_N2PCI: 1933 fecrp = (u_int *)(hc->sca_base + SR_FECR); 1934 *fecrp |= SR_FECR_ETC1; 1935 break; 1936 } 1937 #endif 1938 } 1939 1940 /* 1941 * XXX Disable all interrupts for now. I think if you are using the 1942 * dmac you don't use these interrupts. 1943 */ 1944 SRC_PUT8(hc->sca_base, msci->ie0, 0); 1945 SRC_PUT8(hc->sca_base, msci->ie1, 0x0C); 1946 SRC_PUT8(hc->sca_base, msci->ie2, 0); 1947 SRC_PUT8(hc->sca_base, msci->fie, 0); 1948 1949 SRC_PUT8(hc->sca_base, msci->sa0, 0); 1950 SRC_PUT8(hc->sca_base, msci->sa1, 0); 1951 1952 SRC_PUT8(hc->sca_base, msci->idl, 0x7E); /* set flags value */ 1953 1954 SRC_PUT8(hc->sca_base, msci->rrc, 0x0E); 1955 SRC_PUT8(hc->sca_base, msci->trc0, 0x10); 1956 SRC_PUT8(hc->sca_base, msci->trc1, 0x1F); 1957 } 1958 1959 /* 1960 * Configure the rx dma controller. 1961 */ 1962 static void 1963 sr_init_rx_dmac(struct sr_softc *sc) 1964 { 1965 struct sr_hardc *hc; 1966 dmac_channel *dmac; 1967 sca_descriptor *rxd; 1968 u_int cda_v, sarb_v, rxbuf, rxda, rxda_d; 1969 1970 #if BUGGY > 0 1971 printf("sr_init_rx_dmac(sc=%08x)\n", sc); 1972 #endif 1973 1974 hc = sc->hc; 1975 dmac = &hc->sca->dmac[DMAC_RXCH(sc->scachan)]; 1976 1977 if (hc->mempages) 1978 SRC_SET_MEM(hc->iobase, sc->rxdesc); 1979 1980 /* 1981 * This phase initializes the contents of the descriptor table 1982 * needed to construct a circular buffer... 1983 */ 1984 rxd = (sca_descriptor *)(hc->mem_start + (sc->rxdesc & hc->winmsk)); 1985 rxda_d = (u_int) hc->mem_start - (sc->rxdesc & ~hc->winmsk); 1986 1987 for (rxbuf = sc->rxstart; 1988 rxbuf < sc->rxend; 1989 rxbuf += SR_BUF_SIZ, rxd++) { 1990 /* 1991 * construct the circular chain... 1992 */ 1993 rxda = (u_int) & rxd[1] - rxda_d + hc->mem_pstart; 1994 rxd->cp = (u_short)(rxda & 0xffff); 1995 1996 /* 1997 * set the on-card buffer address... 1998 */ 1999 rxd->bp = (u_short)((rxbuf + hc->mem_pstart) & 0xffff); 2000 rxd->bpb = (u_char)(((rxbuf + hc->mem_pstart) >> 16) & 0xff); 2001 2002 rxd->len = 0; /* bytes resident w/in granule */ 2003 rxd->stat = 0xff; /* The sca write here when finished */ 2004 } 2005 2006 /* 2007 * heal the chain so that the last entry points to the first... 2008 */ 2009 rxd--; 2010 rxd->cp = (u_short)((sc->rxdesc + hc->mem_pstart) & 0xffff); 2011 2012 /* 2013 * reset the reception handler's index... 2014 */ 2015 sc->rxhind = 0; 2016 2017 /* 2018 * We'll now configure the receiver's DMA logic... 2019 */ 2020 SRC_PUT8(hc->sca_base, dmac->dsr, 0); /* Disable DMA transfer */ 2021 SRC_PUT8(hc->sca_base, dmac->dcr, SCA_DCR_ABRT); 2022 2023 /* XXX maybe also SCA_DMR_CNTE */ 2024 SRC_PUT8(hc->sca_base, dmac->dmr, SCA_DMR_TMOD | SCA_DMR_NF); 2025 SRC_PUT16(hc->sca_base, dmac->bfl, SR_BUF_SIZ); 2026 2027 cda_v = (u_short)((sc->rxdesc + hc->mem_pstart) & 0xffff); 2028 sarb_v = (u_char)(((sc->rxdesc + hc->mem_pstart) >> 16) & 0xff); 2029 2030 SRC_PUT16(hc->sca_base, dmac->cda, cda_v); 2031 SRC_PUT8(hc->sca_base, dmac->sarb, sarb_v); 2032 2033 rxd = (sca_descriptor *)sc->rxstart; 2034 2035 SRC_PUT16(hc->sca_base, dmac->eda, 2036 (u_short)((u_int) & rxd[sc->rxmax - 1] & 0xffff)); 2037 2038 SRC_PUT8(hc->sca_base, dmac->dir, 0xF0); 2039 2040 2041 SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE); /* Enable DMA */ 2042 } 2043 2044 /* 2045 * Configure the TX DMA descriptors. 2046 * Initialize the needed values and chain the descriptors. 2047 */ 2048 static void 2049 sr_init_tx_dmac(struct sr_softc *sc) 2050 { 2051 int blk; 2052 u_int txbuf, txda, txda_d; 2053 struct sr_hardc *hc; 2054 sca_descriptor *txd; 2055 dmac_channel *dmac; 2056 struct buf_block *blkp; 2057 u_int x; 2058 u_int sarb_v; 2059 2060 #if BUGGY > 0 2061 printf("sr_init_tx_dmac(sc=%08x)\n", sc); 2062 #endif 2063 2064 hc = sc->hc; 2065 dmac = &hc->sca->dmac[DMAC_TXCH(sc->scachan)]; 2066 2067 if (hc->mempages) 2068 SRC_SET_MEM(hc->iobase, sc->block[0].txdesc); 2069 2070 /* 2071 * Initialize the array of descriptors for transmission 2072 */ 2073 for (blk = 0; blk < SR_TX_BLOCKS; blk++) { 2074 blkp = &sc->block[blk]; 2075 txd = (sca_descriptor *)(hc->mem_start 2076 + (blkp->txdesc & hc->winmsk)); 2077 txda_d = (u_int) hc->mem_start 2078 - (blkp->txdesc & ~hc->winmsk); 2079 2080 x = 0; 2081 txbuf = blkp->txstart; 2082 for (; txbuf < blkp->txend; txbuf += SR_BUF_SIZ, txd++) { 2083 txda = (u_int) & txd[1] - txda_d + hc->mem_pstart; 2084 txd->cp = (u_short)(txda & 0xffff); 2085 2086 txd->bp = (u_short)((txbuf + hc->mem_pstart) 2087 & 0xffff); 2088 txd->bpb = (u_char)(((txbuf + hc->mem_pstart) >> 16) 2089 & 0xff); 2090 txd->len = 0; 2091 txd->stat = 0; 2092 x++; 2093 } 2094 2095 txd--; 2096 txd->cp = (u_short)((blkp->txdesc + hc->mem_pstart) 2097 & 0xffff); 2098 2099 blkp->txtail = (u_int)txd - (u_int)hc->mem_start; 2100 } 2101 2102 SRC_PUT8(hc->sca_base, dmac->dsr, 0); /* Disable DMA */ 2103 SRC_PUT8(hc->sca_base, dmac->dcr, SCA_DCR_ABRT); 2104 SRC_PUT8(hc->sca_base, dmac->dmr, SCA_DMR_TMOD | SCA_DMR_NF); 2105 SRC_PUT8(hc->sca_base, dmac->dir, 2106 SCA_DIR_EOT | SCA_DIR_BOF | SCA_DIR_COF); 2107 2108 sarb_v = (sc->block[0].txdesc + hc->mem_pstart) >> 16; 2109 sarb_v &= 0x00ff; 2110 2111 SRC_PUT8(hc->sca_base, dmac->sarb, (u_char) sarb_v); 2112 } 2113 2114 /* 2115 * Look through the descriptors to see if there is a complete packet 2116 * available. Stop if we get to where the sca is busy. 2117 * 2118 * Return the length and status of the packet. 2119 * Return nonzero if there is a packet available. 2120 * 2121 * NOTE: 2122 * It seems that we get the interrupt a bit early. The updateing of 2123 * descriptor values is not always completed when this is called. 2124 */ 2125 static int 2126 sr_packet_avail(struct sr_softc *sc, int *len, u_char *rxstat) 2127 { 2128 int granules; /* count of granules in pkt */ 2129 int wki, wko; 2130 struct sr_hardc *hc; 2131 sca_descriptor *rxdesc; /* current descriptor */ 2132 sca_descriptor *endp; /* ending descriptor */ 2133 sca_descriptor *cda; /* starting descriptor */ 2134 2135 hc = sc->hc; /* get card's information */ 2136 2137 /* 2138 * set up starting descriptor by pulling that info from the DMA half 2139 * of the HD chip... 2140 */ 2141 wki = DMAC_RXCH(sc->scachan); 2142 wko = SRC_GET16(hc->sca_base, hc->sca->dmac[wki].cda); 2143 2144 cda = (sca_descriptor *)(hc->mem_start + (wko & hc->winmsk)); 2145 2146 #if BUGGY > 1 2147 printf("sr_packet_avail(): wki=%d, wko=%04x, cda=%08x\n", 2148 wki, wko, cda); 2149 #endif 2150 2151 /* 2152 * open the appropriate memory window and set our expectations... 2153 */ 2154 if (hc->mempages) { 2155 SRC_SET_MEM(hc->iobase, sc->rxdesc); 2156 SRC_SET_ON(hc->iobase); 2157 } 2158 rxdesc = (sca_descriptor *) 2159 (hc->mem_start + (sc->rxdesc & hc->winmsk)); 2160 endp = rxdesc; 2161 rxdesc = &rxdesc[sc->rxhind]; 2162 endp = &endp[sc->rxmax]; 2163 2164 *len = 0; /* reset result total length */ 2165 granules = 0; /* reset count of granules */ 2166 2167 /* 2168 * This loop will scan descriptors, but it *will* puke up if we wrap 2169 * around to our starting point... 2170 */ 2171 while (rxdesc != cda) { 2172 *len += rxdesc->len; /* increment result length */ 2173 granules++; 2174 2175 /* 2176 * If we hit a valid packet's completion we'll know we've 2177 * got a live one, and that we can deliver the packet. 2178 * Since we're only allowed to report a packet available, 2179 * somebody else does that... 2180 */ 2181 if (rxdesc->stat & SCA_DESC_EOM) { /* End Of Message */ 2182 *rxstat = rxdesc->stat; /* return closing */ 2183 #if BUGGY > 0 2184 printf("sr%d: PKT AVAIL len %d, %x, bufs %u.\n", 2185 sc->unit, *len, *rxstat, granules); 2186 #endif 2187 return 1; /* indicate success */ 2188 } 2189 /* 2190 * OK, this packet take up multiple granules. Move on to 2191 * the next descriptor so we can consider it... 2192 */ 2193 rxdesc++; 2194 2195 if (rxdesc == endp) /* recognize & act on wrap point */ 2196 rxdesc = (sca_descriptor *) 2197 (hc->mem_start + (sc->rxdesc & hc->winmsk)); 2198 } 2199 2200 /* 2201 * Nothing found in the DPRAM. Let the caller know... 2202 */ 2203 *len = 0; 2204 *rxstat = 0; 2205 2206 return 0; 2207 } 2208 2209 /* 2210 * Copy a packet from the on card memory into a provided mbuf. 2211 * Take into account that buffers wrap and that a packet may 2212 * be larger than a buffer. 2213 */ 2214 static void 2215 sr_copy_rxbuf(struct mbuf *m, struct sr_softc *sc, int len) 2216 { 2217 struct sr_hardc *hc; 2218 sca_descriptor *rxdesc; 2219 u_int rxdata; 2220 u_int rxmax; 2221 u_int off = 0; 2222 u_int tlen; 2223 2224 #if BUGGY > 0 2225 printf("sr_copy_rxbuf(m=%08x,sc=%08x,len=%d)\n", 2226 m, sc, len); 2227 #endif 2228 2229 hc = sc->hc; 2230 2231 rxdata = sc->rxstart + (sc->rxhind * SR_BUF_SIZ); 2232 rxmax = sc->rxstart + (sc->rxmax * SR_BUF_SIZ); 2233 2234 rxdesc = (sca_descriptor *) 2235 (hc->mem_start + (sc->rxdesc & hc->winmsk)); 2236 rxdesc = &rxdesc[sc->rxhind]; 2237 2238 /* 2239 * Using the count of bytes in the received packet, we decrement it 2240 * for each granule (controller by an SCA descriptor) to control the 2241 * looping... 2242 */ 2243 while (len) { 2244 /* 2245 * tlen gets the length of *this* granule... ...which is 2246 * then copied to the target buffer. 2247 */ 2248 tlen = (len < SR_BUF_SIZ) ? len : SR_BUF_SIZ; 2249 2250 if (hc->mempages) 2251 SRC_SET_MEM(hc->iobase, rxdata); 2252 2253 bcopy(hc->mem_start + (rxdata & hc->winmsk), 2254 mtod(m, caddr_t) +off, 2255 tlen); 2256 2257 off += tlen; 2258 len -= tlen; 2259 2260 /* 2261 * now, return to the descriptor's window in DPRAM and reset 2262 * the descriptor we've just suctioned... 2263 */ 2264 if (hc->mempages) 2265 SRC_SET_MEM(hc->iobase, sc->rxdesc); 2266 2267 rxdesc->len = 0; 2268 rxdesc->stat = 0xff; 2269 2270 /* 2271 * Move on to the next granule. If we've any remaining 2272 * bytes to process we'll just continue in our loop... 2273 */ 2274 rxdata += SR_BUF_SIZ; 2275 rxdesc++; 2276 2277 if (rxdata == rxmax) { /* handle the wrap point */ 2278 rxdata = sc->rxstart; 2279 rxdesc = (sca_descriptor *) 2280 (hc->mem_start + (sc->rxdesc & hc->winmsk)); 2281 } 2282 } 2283 } 2284 2285 /* 2286 * If single is set, just eat a packet. Otherwise eat everything up to 2287 * where cda points. Update pointers to point to the next packet. 2288 * 2289 * This handles "flushing" of a packet as received... 2290 * 2291 * If the "single" parameter is zero, all pending reeceive traffic will 2292 * be flushed out of existence. A non-zero value will only drop the 2293 * *next* (currently) pending packet... 2294 */ 2295 static void 2296 sr_eat_packet(struct sr_softc *sc, int single) 2297 { 2298 struct sr_hardc *hc; 2299 sca_descriptor *rxdesc; /* current descriptor being eval'd */ 2300 sca_descriptor *endp; /* last descriptor in chain */ 2301 sca_descriptor *cda; /* current start point */ 2302 u_int loopcnt = 0; /* count of packets flushed ??? */ 2303 u_char stat; /* captured status byte from descr */ 2304 2305 hc = sc->hc; 2306 cda = (sca_descriptor *)(hc->mem_start + 2307 (SRC_GET16(hc->sca_base, 2308 hc->sca->dmac[DMAC_RXCH(sc->scachan)].cda) & 2309 hc->winmsk)); 2310 2311 /* 2312 * loop until desc->stat == (0xff || EOM) Clear the status and 2313 * length in the descriptor. Increment the descriptor. 2314 */ 2315 if (hc->mempages) 2316 SRC_SET_MEM(hc->iobase, sc->rxdesc); 2317 2318 rxdesc = (sca_descriptor *) 2319 (hc->mem_start + (sc->rxdesc & hc->winmsk)); 2320 endp = rxdesc; 2321 rxdesc = &rxdesc[sc->rxhind]; 2322 endp = &endp[sc->rxmax]; 2323 2324 /* 2325 * allow loop, but abort it if we wrap completely... 2326 */ 2327 while (rxdesc != cda) { 2328 loopcnt++; 2329 2330 if (loopcnt > sc->rxmax) { 2331 printf("sr%d: eat pkt %d loop, cda %x, " 2332 "rxdesc %x, stat %x.\n", 2333 sc->unit, loopcnt, (u_int) cda, (u_int) rxdesc, 2334 rxdesc->stat); 2335 break; 2336 } 2337 stat = rxdesc->stat; 2338 2339 rxdesc->len = 0; 2340 rxdesc->stat = 0xff; 2341 2342 rxdesc++; 2343 sc->rxhind++; 2344 2345 if (rxdesc == endp) { 2346 rxdesc = (sca_descriptor *) 2347 (hc->mem_start + (sc->rxdesc & hc->winmsk)); 2348 sc->rxhind = 0; 2349 } 2350 if (single && (stat == SCA_DESC_EOM)) 2351 break; 2352 } 2353 2354 /* 2355 * Update the eda to the previous descriptor. 2356 */ 2357 rxdesc = (sca_descriptor *)sc->rxdesc; 2358 rxdesc = &rxdesc[(sc->rxhind + sc->rxmax - 2) % sc->rxmax]; 2359 2360 SRC_PUT16(hc->sca_base, 2361 hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda, 2362 (u_short)((u_int)(rxdesc + hc->mem_pstart) & 0xffff)); 2363 } 2364 2365 /* 2366 * While there is packets available in the rx buffer, read them out 2367 * into mbufs and ship them off. 2368 */ 2369 static void 2370 sr_get_packets(struct sr_softc *sc) 2371 { 2372 u_char rxstat; /* acquired status byte */ 2373 int i; 2374 int pkts; /* count of packets found */ 2375 int rxndx; /* rcv buffer index */ 2376 int tries; /* settling time counter */ 2377 u_int len; /* length of pending packet */ 2378 struct sr_hardc *hc; /* card-level information */ 2379 sca_descriptor *rxdesc; /* descriptor in memory */ 2380 struct ifnet *ifp; /* network intf ctl table */ 2381 struct mbuf *m = NULL; /* message buffer */ 2382 2383 #if BUGGY > 0 2384 printf("sr_get_packets(sc=%08x)\n", sc); 2385 #endif 2386 2387 hc = sc->hc; 2388 ifp = &sc->ifsppp.pp_if; 2389 2390 if (hc->mempages) { 2391 SRC_SET_MEM(hc->iobase, sc->rxdesc); 2392 SRC_SET_ON(hc->iobase); /* enable shared memory */ 2393 } 2394 pkts = 0; /* reset count of found packets */ 2395 2396 /* 2397 * for each complete packet in the receiving pool, process each 2398 * packet... 2399 */ 2400 while (sr_packet_avail(sc, &len, &rxstat)) { /* packet pending? */ 2401 /* 2402 * I have seen situations where we got the interrupt but the 2403 * status value wasn't deposited. This code should allow 2404 * the status byte's value to settle... 2405 */ 2406 2407 tries = 5; 2408 2409 while ((rxstat == 0x00ff) 2410 && --tries) 2411 sr_packet_avail(sc, &len, &rxstat); 2412 2413 #if BUGGY > 1 2414 printf("sr_packet_avail() returned len=%d, rxstat=%02ux\n", 2415 len, rxstat); 2416 #endif 2417 2418 pkts++; 2419 2420 /* 2421 * OK, we've settled the incoming message status. We can now 2422 * process it... 2423 */ 2424 if (((rxstat & SCA_DESC_ERRORS) == 0) && (len < MCLBYTES)) { 2425 #if BUGGY > 1 2426 printf("sr%d: sr_get_packet() rxstat=%02x, len=%d\n", 2427 sc->unit, rxstat, len); 2428 #endif 2429 2430 MGETHDR(m, M_DONTWAIT, MT_DATA); 2431 if (m == NULL) { 2432 /* 2433 * eat (flush) packet if get mbuf fail!! 2434 */ 2435 sr_eat_packet(sc, 1); 2436 continue; 2437 } 2438 /* 2439 * construct control information for pass-off 2440 */ 2441 m->m_pkthdr.rcvif = ifp; 2442 m->m_pkthdr.len = m->m_len = len; 2443 if (len > MHLEN) { 2444 MCLGET(m, M_DONTWAIT); 2445 if ((m->m_flags & M_EXT) == 0) { 2446 /* 2447 * We couldn't get a big enough 2448 * message packet, so we'll send the 2449 * packet to /dev/null... 2450 */ 2451 m_freem(m); 2452 sr_eat_packet(sc, 1); 2453 continue; 2454 } 2455 } 2456 /* 2457 * OK, we've got a good message buffer. Now we can 2458 * copy the received message into it 2459 */ 2460 sr_copy_rxbuf(m, sc, len); /* copy from DPRAM */ 2461 2462 #if NBPFILTER > 0 2463 if (ifp->if_bpf) 2464 bpf_mtap(ifp, m); 2465 #endif 2466 2467 #if BUGGY > 3 2468 { 2469 u_char *bp; 2470 2471 bp = (u_char *)m; 2472 printf("sr%d: rcvd=%02x%02x%02x%02x%02x%02x\n", 2473 sc->unit, 2474 bp[0], bp[1], bp[2], 2475 bp[4], bp[5], bp[6]); 2476 } 2477 #endif 2478 2479 /* 2480 * Pass off the message to PPP, connecting it it to 2481 * the system... 2482 */ 2483 switch (sc->protocol) { 2484 #if NFR > 0 2485 case N2_USE_FRP: 2486 fr_input(ifp, m); 2487 break; 2488 #endif 2489 case N2_USE_PPP: 2490 default: 2491 sppp_input(ifp, m); 2492 } 2493 2494 ifp->if_ipackets++; 2495 2496 /* 2497 * Update the eda to the previous descriptor. 2498 */ 2499 i = (len + SR_BUF_SIZ - 1) / SR_BUF_SIZ; 2500 sc->rxhind = (sc->rxhind + i) % sc->rxmax; 2501 2502 rxdesc = (sca_descriptor *)sc->rxdesc; 2503 rxndx = (sc->rxhind + sc->rxmax - 2) % sc->rxmax; 2504 rxdesc = &rxdesc[rxndx]; 2505 2506 SRC_PUT16(hc->sca_base, 2507 hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda, 2508 (u_short)((u_int)(rxdesc + hc->mem_pstart) 2509 & 0xffff)); 2510 2511 } else { 2512 int got_st3, got_cda, got_eda; 2513 int tries = 5; 2514 2515 while((rxstat == 0xff) && --tries) 2516 sr_packet_avail(sc, &len, &rxstat); 2517 2518 /* 2519 * It look like we get an interrupt early 2520 * sometimes and then the status is not 2521 * filled in yet. 2522 */ 2523 if(tries && (tries != 5)) 2524 continue; 2525 2526 /* 2527 * This chunk of code handles the error packets. 2528 * We'll log them for posterity... 2529 */ 2530 sr_eat_packet(sc, 1); 2531 2532 ifp->if_ierrors++; 2533 2534 got_st3 = SRC_GET8(hc->sca_base, 2535 hc->sca->msci[sc->scachan].st3); 2536 got_cda = SRC_GET16(hc->sca_base, 2537 hc->sca->dmac[DMAC_RXCH(sc->scachan)].cda); 2538 got_eda = SRC_GET16(hc->sca_base, 2539 hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda); 2540 2541 #if BUGGY > 0 2542 printf("sr%d: Receive error chan %d, " 2543 "stat %02x, msci st3 %02x," 2544 "rxhind %d, cda %04x, eda %04x.\n", 2545 sc->unit, sc->scachan, rxstat, 2546 got_st3, sc->rxhind, got_cda, got_eda); 2547 #endif 2548 } 2549 } 2550 2551 #if BUGGY > 0 2552 printf("sr%d: sr_get_packets() found %d packet(s)\n", 2553 sc->unit, pkts); 2554 #endif 2555 2556 if (hc->mempages) 2557 SRC_SET_OFF(hc->iobase); 2558 } 2559 2560 /* 2561 * All DMA interrupts come here. 2562 * 2563 * Each channel has two interrupts. 2564 * Interrupt A for errors and Interrupt B for normal stuff like end 2565 * of transmit or receive dmas. 2566 */ 2567 static void 2568 sr_dmac_intr(struct sr_hardc *hc, u_char isr1) 2569 { 2570 u_char dsr; /* contents of DMA Stat Reg */ 2571 u_char dotxstart; /* enables for tranmit part */ 2572 int mch; /* channel being processed */ 2573 struct sr_softc *sc; /* channel's softc structure */ 2574 sca_regs *sca = hc->sca; 2575 dmac_channel *dmac; /* dma structure of chip */ 2576 2577 #if BUGGY > 0 2578 printf("sr_dmac_intr(hc=%08x,isr1=%04x)\n", hc, isr1); 2579 #endif 2580 2581 mch = 0; /* assume chan0 on card */ 2582 dotxstart = isr1; /* copy for xmitter starts */ 2583 2584 /* 2585 * Shortcut if there is no interrupts for dma channel 0 or 1. 2586 * Skip processing for channel 0 if no incoming hit 2587 */ 2588 if ((isr1 & 0x0F) == 0) { 2589 mch = 1; 2590 isr1 >>= 4; 2591 } 2592 do { 2593 sc = &hc->sc[mch]; 2594 2595 /* 2596 * Transmit channel - DMA Status Register Evaluation 2597 */ 2598 if (isr1 & 0x0C) { 2599 dmac = &sca->dmac[DMAC_TXCH(mch)]; 2600 2601 /* 2602 * get the DMA Status Register contents and write 2603 * back to reset interrupt... 2604 */ 2605 dsr = SRC_GET8(hc->sca_base, dmac->dsr); 2606 SRC_PUT8(hc->sca_base, dmac->dsr, dsr); 2607 2608 /* 2609 * Check for (& process) a Counter overflow 2610 */ 2611 if (dsr & SCA_DSR_COF) { 2612 printf("sr%d: TX DMA Counter overflow, " 2613 "txpacket no %lu.\n", 2614 sc->unit, sc->ifsppp.pp_if.if_opackets); 2615 sc->ifsppp.pp_if.if_oerrors++; 2616 } 2617 /* 2618 * Check for (& process) a Buffer overflow 2619 */ 2620 if (dsr & SCA_DSR_BOF) { 2621 printf("sr%d: TX DMA Buffer overflow, " 2622 "txpacket no %lu, dsr %02x, " 2623 "cda %04x, eda %04x.\n", 2624 sc->unit, sc->ifsppp.pp_if.if_opackets, 2625 dsr, 2626 SRC_GET16(hc->sca_base, dmac->cda), 2627 SRC_GET16(hc->sca_base, dmac->eda)); 2628 sc->ifsppp.pp_if.if_oerrors++; 2629 } 2630 /* 2631 * Check for (& process) an End of Transfer (OK) 2632 */ 2633 if (dsr & SCA_DSR_EOT) { 2634 /* 2635 * This should be the most common case. 2636 * 2637 * Clear the IFF_OACTIVE flag. 2638 * 2639 * Call srstart to start a new transmit if 2640 * there is data to transmit. 2641 */ 2642 #if BUGGY > 0 2643 printf("sr%d: TX Completed OK\n", sc->unit); 2644 #endif 2645 sc->xmit_busy = 0; 2646 sc->ifsppp.pp_if.if_flags &= ~IFF_OACTIVE; 2647 sc->ifsppp.pp_if.if_timer = 0; 2648 2649 if (sc->txb_inuse && --sc->txb_inuse) 2650 sr_xmit(sc); 2651 } 2652 } 2653 /* 2654 * Receive channel processing of DMA Status Register 2655 */ 2656 if (isr1 & 0x03) { 2657 dmac = &sca->dmac[DMAC_RXCH(mch)]; 2658 2659 dsr = SRC_GET8(hc->sca_base, dmac->dsr); 2660 SRC_PUT8(hc->sca_base, dmac->dsr, dsr); 2661 2662 /* 2663 * End of frame processing (MSG OK?) 2664 */ 2665 if (dsr & SCA_DSR_EOM) { 2666 #if BUGGY > 0 2667 int tt, ind; 2668 2669 tt = sc->ifsppp.pp_if.if_ipackets; 2670 ind = sc->rxhind; 2671 #endif 2672 2673 sr_get_packets(sc); 2674 2675 #if BUGGY > 0 2676 if (tt == sc->ifsppp.pp_if.if_ipackets) { 2677 sca_descriptor *rxdesc; 2678 int i; 2679 2680 printf("SR: RXINTR isr1 %x, dsr %x, " 2681 "no data %d pkts, orxind %d.\n", 2682 dotxstart, dsr, tt, ind); 2683 printf("SR: rxdesc %x, rxstart %x, " 2684 "rxend %x, rxhind %d, " 2685 "rxmax %d.\n", 2686 sc->rxdesc, sc->rxstart, 2687 sc->rxend, sc->rxhind, 2688 sc->rxmax); 2689 printf("SR: cda %x, eda %x.\n", 2690 SRC_GET16(hc->sca_base, dmac->cda), 2691 SRC_GET16(hc->sca_base, dmac->eda)); 2692 2693 if (hc->mempages) { 2694 SRC_SET_ON(hc->iobase); 2695 SRC_SET_MEM(hc->iobase, sc->rxdesc); 2696 } 2697 rxdesc = (sca_descriptor *) 2698 (hc->mem_start + 2699 (sc->rxdesc & hc->winmsk)); 2700 rxdesc = &rxdesc[sc->rxhind]; 2701 2702 for (i = 0; i < 3; i++, rxdesc++) 2703 printf("SR: rxdesc->stat %x, " 2704 "len %d.\n", 2705 rxdesc->stat, 2706 rxdesc->len); 2707 2708 if (hc->mempages) 2709 SRC_SET_OFF(hc->iobase); 2710 } 2711 #endif 2712 } 2713 /* 2714 * Check for Counter overflow 2715 */ 2716 if (dsr & SCA_DSR_COF) { 2717 printf("sr%d: RX DMA Counter overflow, " 2718 "rxpkts %lu.\n", 2719 sc->unit, sc->ifsppp.pp_if.if_ipackets); 2720 sc->ifsppp.pp_if.if_ierrors++; 2721 } 2722 /* 2723 * Check for Buffer overflow 2724 */ 2725 if (dsr & SCA_DSR_BOF) { 2726 printf("sr%d: RX DMA Buffer overflow, " 2727 "rxpkts %lu, rxind %d, " 2728 "cda %x, eda %x, dsr %x.\n", 2729 sc->unit, sc->ifsppp.pp_if.if_ipackets, 2730 sc->rxhind, 2731 SRC_GET16(hc->sca_base, dmac->cda), 2732 SRC_GET16(hc->sca_base, dmac->eda), 2733 dsr); 2734 2735 /* 2736 * Make sure we eat as many as possible. 2737 * Then get the system running again. 2738 */ 2739 if (hc->mempages) 2740 SRC_SET_ON(hc->iobase); 2741 2742 sr_eat_packet(sc, 0); 2743 sc->ifsppp.pp_if.if_ierrors++; 2744 2745 SRC_PUT8(hc->sca_base, 2746 sca->msci[mch].cmd, 2747 SCA_CMD_RXMSGREJ); 2748 2749 SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE); 2750 2751 #if BUGGY > 0 2752 printf("sr%d: RX DMA Buffer overflow, " 2753 "rxpkts %lu, rxind %d, " 2754 "cda %x, eda %x, dsr %x. After\n", 2755 sc->unit, 2756 sc->ifsppp.pp_if.if_ipackets, 2757 sc->rxhind, 2758 SRC_GET16(hc->sca_base, dmac->cda), 2759 SRC_GET16(hc->sca_base, dmac->eda), 2760 SRC_GET8(hc->sca_base, dmac->dsr)); 2761 #endif 2762 2763 if (hc->mempages) 2764 SRC_SET_OFF(hc->iobase); 2765 } 2766 /* 2767 * End of Transfer 2768 */ 2769 if (dsr & SCA_DSR_EOT) { 2770 /* 2771 * If this happen, it means that we are 2772 * receiving faster than what the processor 2773 * can handle. 2774 * 2775 * XXX We should enable the dma again. 2776 */ 2777 printf("sr%d: RX End of xfer, rxpkts %lu.\n", 2778 sc->unit, 2779 sc->ifsppp.pp_if.if_ipackets); 2780 sc->ifsppp.pp_if.if_ierrors++; 2781 } 2782 } 2783 isr1 >>= 4; /* process next half of ISR */ 2784 mch++; /* and move to next channel */ 2785 } while ((mch < NCHAN) && isr1); /* loop for each chn */ 2786 2787 /* 2788 * Now that we have done all the urgent things, see if we can fill 2789 * the transmit buffers. 2790 */ 2791 for (mch = 0; mch < NCHAN; mch++) { 2792 if (dotxstart & 0x0C) { /* TX initiation enabled? */ 2793 sc = &hc->sc[mch]; 2794 srstart(&sc->ifsppp.pp_if); 2795 } 2796 dotxstart >>= 4;/* shift for next channel */ 2797 } 2798 } 2799 2800 /* 2801 * Perform timeout on an FR channel 2802 * 2803 * Establish a periodic check of open N2 ports; If 2804 * a port is open/active, it's DCD state is checked 2805 * and a loss of DCD is recognized (and eventually 2806 * processed). 2807 */ 2808 static void 2809 sr_modemck(void *arg) 2810 { 2811 u_int s; 2812 int card; /* card index in table */ 2813 int cards; /* card list index */ 2814 int mch; /* channel on card */ 2815 u_char dcd_v; /* Data Carrier Detect */ 2816 u_char got_st0; /* contents of ST0 */ 2817 u_char got_st1; /* contents of ST1 */ 2818 u_char got_st2; /* contents of ST2 */ 2819 u_char got_st3; /* contents of ST3 */ 2820 struct sr_hardc *hc; /* card's configuration */ 2821 struct sr_hardc *Card[16];/* up to 16 cards in system */ 2822 struct sr_softc *sc; /* channel's softc structure */ 2823 struct ifnet *ifp; /* interface control table */ 2824 msci_channel *msci; /* regs specific to channel */ 2825 2826 s = splimp(); 2827 2828 #if 0 2829 if (sr_opens == 0) { /* count of "up" channels */ 2830 sr_watcher = 0; /* indicate no watcher */ 2831 splx(s); 2832 return; 2833 } 2834 #endif 2835 2836 sr_watcher = 1; /* mark that we're online */ 2837 2838 /* 2839 * Now we'll need a list of cards to process. Since we can handle 2840 * both ISA and PCI cards (and I didn't think of making this logic 2841 * global YET) we'll generate a single table of card table 2842 * addresses. 2843 */ 2844 cards = 0; 2845 2846 for (card = 0; card < NSR; card++) { 2847 hc = &sr_hardc[card]; 2848 2849 if (hc->sc == (void *)0) 2850 continue; 2851 2852 Card[cards++] = hc; 2853 } 2854 2855 hc = sr_hardc_pci; 2856 2857 while (hc) { 2858 Card[cards++] = hc; 2859 hc = hc->next; 2860 } 2861 2862 /* 2863 * OK, we've got work we can do. Let's do it... (Please note that 2864 * this code _only_ deals w/ ISA cards) 2865 */ 2866 for (card = 0; card < cards; card++) { 2867 hc = Card[card];/* get card table */ 2868 2869 for (mch = 0; mch < hc->numports; mch++) { 2870 sc = &hc->sc[mch]; 2871 2872 if (sc->attached == 0) 2873 continue; 2874 2875 ifp = &sc->ifsppp.pp_if; 2876 2877 /* 2878 * if this channel isn't "up", skip it 2879 */ 2880 if ((ifp->if_flags & IFF_UP) == 0) 2881 continue; 2882 2883 /* 2884 * OK, now we can go looking at this channel's 2885 * actual register contents... 2886 */ 2887 msci = &hc->sca->msci[sc->scachan]; 2888 2889 /* 2890 * OK, now we'll look into the actual status of this 2891 * channel... 2892 * 2893 * I suck in more registers than strictly needed 2894 */ 2895 got_st0 = SRC_GET8(hc->sca_base, msci->st0); 2896 got_st1 = SRC_GET8(hc->sca_base, msci->st1); 2897 got_st2 = SRC_GET8(hc->sca_base, msci->st2); 2898 got_st3 = SRC_GET8(hc->sca_base, msci->st3); 2899 2900 /* 2901 * We want to see if the DCD signal is up (DCD is 2902 * true if zero) 2903 */ 2904 dcd_v = (got_st3 & SCA_ST3_DCD) == 0; 2905 2906 if (dcd_v == 0) 2907 printf("sr%d: DCD lost\n", sc->unit); 2908 } 2909 } 2910 2911 /* 2912 * OK, now set up for the next modem signal checking pass... 2913 */ 2914 timeout(sr_modemck, NULL, hz); 2915 2916 splx(s); 2917 } 2918 2919 static void 2920 sr_msci_intr(struct sr_hardc *hc, u_char isr0) 2921 { 2922 printf("src%d: SRINTR: MSCI\n", hc->cunit); 2923 } 2924 2925 static void 2926 sr_timer_intr(struct sr_hardc *hc, u_char isr2) 2927 { 2928 printf("src%d: SRINTR: TIMER\n", hc->cunit); 2929 } 2930 2931 /* 2932 ********************************* END ************************************ 2933 */
Cache object: cd4a4efdbc68a824cf7e159f6150c358
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]