The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/i386/isa/if_srregs.h

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    1 /*
    2  * Copyright (c) 1995 John Hay.
    3  * Copyright (c) 1996 SDL Communications, Inc.
    4  * All rights reserved.
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions
    8  * are met:
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  * 3. Neither the name of the author nor the names of any co-contributors
   15  *    may be used to endorse or promote products derived from this software
   16  *    without specific prior written permission.
   17  *
   18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   28  * SUCH DAMAGE.
   29  *
   30  * $FreeBSD: src/sys/i386/isa/if_srregs.h,v 1.2.2.1 1999/09/05 08:12:58 peter Exp $
   31  */
   32 #ifndef _IF_SRREGS_H_
   33 #define _IF_SRREGS_H_
   34 
   35 #define NCHAN                   2    /* A HD64570 chip have 2 channels */
   36 
   37 #define SR_BUF_SIZ              512
   38 #define SR_TX_BLOCKS            2    /* Sepperate sets of tx buffers */
   39 
   40 #define SR_CRD_N2               1
   41 #define SR_CRD_N2PCI            2
   42 
   43 /*
   44  * RISCom/N2 ISA card.
   45  */
   46 #define SRC_IO_SIZ              0x10 /* Actually a lie. It uses a lot more. */
   47 #define SRC_WIN_SIZ             0x00004000
   48 #define SRC_WIN_MSK             (SRC_WIN_SIZ - 1)
   49 #define SRC_WIN_SHFT            14
   50 
   51 #define SR_FLAGS_NCHAN_MSK      0x0000000F
   52 #define SR_FLAGS_0_CLK_MSK      0x00000030
   53 #define SR_FLAGS_0_EXT_CLK      0x00000000 /* External RX clock shared by TX */
   54 #define SR_FLAGS_0_EXT_SEP_CLK  0x00000010 /* Sepperate external clocks */
   55 #define SR_FLAGS_0_INT_CLK      0x00000020 /* Internal clock */
   56 #define SR_FLAGS_1_CLK_MSK      0x000000C0
   57 #define SR_FLAGS_1_EXT_CLK      0x00000000 /* External RX clock shared by TX */
   58 #define SR_FLAGS_1_EXT_SEP_CLK  0x00000040 /* Sepperate external clocks */
   59 #define SR_FLAGS_1_INT_CLK      0x00000080 /* Internal clock */
   60 
   61 #define SR_FLAGS_CLK_SHFT       4
   62 #define SR_FLAGS_CLK_CHAN_SHFT  2
   63 #define SR_FLAGS_EXT_CLK        0x00000000 /* External RX clock shared by TX */
   64 #define SR_FLAGS_EXT_SEP_CLK    0x00000001 /* Sepperate external clocks */
   65 #define SR_FLAGS_INT_CLK        0x00000002 /* Internal clock */
   66 
   67 #define SR_PCR                  0x00 /* RW, PC Control Register */
   68 #define SR_BAR                  0x02 /* RW, Base Address Register */
   69 #define SR_PSR                  0x04 /* RW, Page Scan Register */
   70 #define SR_MCR                  0x06 /* RW, Modem Control Register */
   71 
   72 #define SR_PCR_SCARUN           0x01 /* !Reset */
   73 #define SR_PCR_EN_VPM           0x02 /* Running above 1M */
   74 #define SR_PCR_MEM_WIN          0x04 /* Open memory window */
   75 #define SR_PCR_ISA16            0x08 /* 16 bit ISA mode */
   76 #define SR_PCR_16M_SEL          0xF0 /* A20-A23 Addresses */
   77 
   78 #define SR_PSR_PG_SEL           0x1F /* Page 0 - 31 select */
   79 #define SR_PG_MSK               0x1F
   80 #define SR_PSR_WIN_SIZ          0x60 /* Window size select */
   81 #define SR_PSR_WIN_16K          0x00
   82 #define SR_PSR_WIN_32K          0x20
   83 #define SR_PSR_WIN_64K          0x40
   84 #define SR_PSR_WIN_128K         0x60
   85 #define SR_PSR_EN_SCA_DMA       0x80 /* Enable the SCA DMA */
   86 
   87 #define SR_MCR_DTR0             0x01 /* Deactivate DTR0 */
   88 #define SR_MCR_DTR1             0x02 /* Deactivate DTR1 */
   89 #define SR_MCR_DSR0             0x04 /* DSR0 Status */
   90 #define SR_MCR_DSR1             0x08 /* DSR1 Status */
   91 #define SR_MCR_TE0              0x10 /* Enable RS422 TXD */
   92 #define SR_MCR_TE1              0x20 /* Enable RS422 TXD */
   93 #define SR_MCR_ETC0             0x40 /* Enable Ext Clock out */
   94 #define SR_MCR_ETC1             0x80 /* Enable Ext Clock out */
   95 
   96 /*
   97  * RISCom/N2 PCI card.
   98  */
   99 #define SR_FECR                 0x0200 /* Front End Control Register */
  100 #define SR_FECR_ETC0            0x0001 /* Enable Ext Clock out */
  101 #define SR_FECR_ETC1            0x0002 /* Enable Ext Clock out */
  102 #define SR_FECR_TE0             0x0004 /* Enable RS422 TXD */
  103 #define SR_FECR_TE1             0x0008 /* Enable RS422 TXD */
  104 #define SR_FECR_GPO0            0x0010 /* General Purpose Output */
  105 #define SR_FECR_GPO1            0x0020 /* General Purpose Output */
  106 #define SR_FECR_DTR0            0x0040 /* 0 for active, 1 for inactive */
  107 #define SR_FECR_DTR1            0x0080 /* 0 for active, 1 for inactive */
  108 #define SR_FECR_DSR0            0x0100 /* DSR0 Status */
  109 #define SR_FECR_ID0             0x0E00 /* ID of channel 0 */
  110 #define SR_FECR_DSR1            0x1000 /* DSR1 Status */
  111 #define SR_FECR_ID1             0xE000 /* ID of channel 1 */
  112 
  113 #define SR_FE_ID_V35            0x00   /* V.35 Interface */
  114 #define SR_FE_ID_RS232          0x01   /* RS232 Interface */
  115 #define SR_FE_ID_TEST           0x02   /* Test Board */
  116 #define SR_FE_ID_RS422          0x03   /* RS422 Interface */
  117 #define SR_FE_ID_HSSI           0x05   /* HSSI Interface */
  118 #define SR_FE_ID_X21            0x06   /* X.21 Interface */
  119 #define SR_FE_ID_NONE           0x07   /* No card present */
  120 #define SR_FE_ID0_SHFT             9
  121 #define SR_FE_ID1_SHFT            13
  122 
  123 #endif /* _IF_SRREGS_H_ */

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