if_zpreg.h

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    1 /*
    2  * Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca)
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. The name of the author may not be used to endorse or promote products
   11  *    derived from this software without specific prior written permission
   12  *
   13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   14  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   15  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   16  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   17  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   18  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   19  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   20  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   21  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   22  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   23  *
   24  * $FreeBSD$
   25  */
   26 /**************************************************************************
   27  *                                                                                *
   28  * These define the EEPROM data structure.  They are used in the probe
   29  * function to verify the existence of the adapter after having sent
   30  * the ID_Sequence.
   31  *
   32  * There are others but only the ones we use are defined here.
   33  *
   34  **************************************************************************/
   35 
   36 #define EEPROM_NODE_ADDR_0      0x0     /* Word */
   37 #define EEPROM_NODE_ADDR_1      0x1     /* Word */
   38 #define EEPROM_NODE_ADDR_2      0x2     /* Word */
   39 #define EEPROM_PROD_ID          0x3     /* 0x9[0-f]50 */
   40 #define EEPROM_MFG_ID           0x7     /* 0x6d50 */
   41 #define EEPROM_ADDR_CFG         0x8     /* Base addr */
   42 #define EEPROM_RESOURCE_CFG     0x9     /* IRQ. Bits 12-15 */
   43 
   44 /**************************************************************************
   45  *                                                                                *
   46  * These are the registers for the 3Com 3c509 and their bit patterns when *
   47  * applicable.  They have been taken out the the "EtherLink III Parallel  *
   48  * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual *
   49  * from 3com.                                                             *
   50  *                                                                                *
   51  **************************************************************************/
   52 
   53 #define EP_COMMAND              0x0e    /* Write. BASE+0x0e is always a command reg. */
   54 #define EP_STATUS               0x0e    /* Read. BASE+0x0e is always status reg. */
   55 #define EP_WINDOW               0x0f    /* Read. BASE+0x0f is always window reg. */
   56 /*
   57  * Window 0 registers. Setup.
   58  */
   59         /* Write */
   60 #define EP_W0_EEPROM_DATA       0x0c
   61 #define EP_W0_EEPROM_COMMAND    0x0a
   62 #define EP_W0_RESOURCE_CFG      0x08
   63 #define EP_W0_ADDRESS_CFG       0x06
   64 #define EP_W0_CONFIG_CTRL       0x04
   65         /* Read */
   66 #define EP_W0_PRODUCT_ID        0x02
   67 #define EP_W0_MFG_ID            0x00
   68 
   69 /*
   70  * Window 1 registers. Operating Set.
   71  */
   72         /* Write */
   73 #define EP_W1_TX_PIO_WR_2       0x02
   74 #define EP_W1_TX_PIO_WR_1       0x00
   75         /* Read */
   76 #define EP_W1_FREE_TX           0x0c
   77 #define EP_W1_TX_STATUS         0x0b    /* byte */
   78 #define EP_W1_TIMER             0x0a    /* byte */
   79 #define EP_W1_RX_STATUS         0x08
   80 #define EP_W1_RX_PIO_RD_2       0x02
   81 #define EP_W1_RX_PIO_RD_1       0x00
   82 
   83 /*
   84  * Window 2 registers. Station Address Setup/Read
   85  */
   86         /* Read/Write */
   87 #define EP_W2_ADDR_5            0x05
   88 #define EP_W2_ADDR_4            0x04
   89 #define EP_W2_ADDR_3            0x03
   90 #define EP_W2_ADDR_2            0x02
   91 #define EP_W2_ADDR_1            0x01
   92 #define EP_W2_ADDR_0            0x00
   93 
   94 /*
   95  * Window 3 registers.  FIFO Management.
   96  */
   97         /* Read */
   98 #define EP_W3_FREE_TX           0x0c
   99 #define EP_W3_FREE_RX           0x0a
  100 
  101 /*
  102  * Window 4 registers. Diagnostics.
  103  */
  104         /* Read/Write */
  105 #define EP_W4_MEDIA_TYPE        0x0a
  106 #define EP_W4_CTRLR_STATUS      0x08
  107 #define EP_W4_NET_DIAG          0x06
  108 #define EP_W4_FIFO_DIAG         0x04
  109 #define EP_W4_HOST_DIAG         0x02
  110 #define EP_W4_TX_DIAG           0x00
  111 
  112 /*
  113  * Window 5 Registers.  Results and Internal status.
  114  */
  115         /* Read */
  116 #define EP_W5_READ_0_MASK       0x0c
  117 #define EP_W5_INTR_MASK         0x0a
  118 #define EP_W5_RX_FILTER         0x08
  119 #define EP_W5_RX_EARLY_THRESH   0x06
  120 #define EP_W5_TX_AVAIL_THRESH   0x02
  121 #define EP_W5_TX_START_THRESH   0x00
  122 
  123 /*
  124  * Window 6 registers. Statistics.
  125  */
  126         /* Read/Write */
  127 #define TX_TOTAL_OK             0x0c
  128 #define RX_TOTAL_OK             0x0a
  129 #define TX_DEFERRALS            0x08
  130 #define RX_FRAMES_OK            0x07
  131 #define TX_FRAMES_OK            0x06
  132 #define RX_OVERRUNS             0x05
  133 #define TX_COLLISIONS           0x04
  134 #define TX_AFTER_1_COLLISION    0x03
  135 #define TX_AFTER_X_COLLISIONS   0x02
  136 #define TX_NO_SQE               0x01
  137 #define TX_CD_LOST              0x00
  138 
  139 /****************************************
  140  *
  141  * Register definitions.
  142  *
  143  ****************************************/
  144 
  145 /*
  146  * Command register. All windows.
  147  *
  148  * 16 bit register.
  149  *     15-11:  5-bit code for command to be executed.
  150  *     10-0:   11-bit arg if any. For commands with no args;
  151  *            this can be set to anything.
  152  */
  153 #define GLOBAL_RESET            (u_short) 0x0000   /* Wait at least 1ms after issuing */
  154 #define WINDOW_SELECT           (u_short) (0x1<<11)
  155 #define START_TRANSCEIVER       (u_short) (0x2<<11) /* Read ADDR_CFG reg to determine
  156                                                       whether this is needed. If so;
  157                                                       wait 800 uSec before using trans-
  158                                                       ceiver. */
  159 #define RX_DISABLE              (u_short) (0x3<<11) /* state disabled on power-up */
  160 #define RX_ENABLE               (u_short) (0x4<<11)
  161 #define RX_RESET                (u_short) (0x5<<11)
  162 #define RX_DISCARD_TOP_PACK     (u_short) (0x8<<11)
  163 #define TX_ENABLE               (u_short) (0x9<<11)
  164 #define TX_DISABLE              (u_short) (0xa<<11)
  165 #define TX_RESET                (u_short) (0xb<<11)
  166 #define REQ_INTR                (u_short) (0xc<<11)
  167    /*
  168     * The following C_* acknowledge the various interrupts.
  169     * Some of them don't do anything.  See the manual.
  170     */
  171 #define ACK_INTR                (u_short) (0x6800)
  172 #      define C_INTR_LATCH      (u_short) (ACK_INTR|0x1)
  173 #      define C_CARD_FAILURE    (u_short) (ACK_INTR|0x2)
  174 #      define C_TX_COMPLETE     (u_short) (ACK_INTR|0x4)
  175 #      define C_TX_AVAIL        (u_short) (ACK_INTR|0x8)
  176 #      define C_RX_COMPLETE     (u_short) (ACK_INTR|0x10)
  177 #      define C_RX_EARLY        (u_short) (ACK_INTR|0x20)
  178 #      define C_INT_RQD         (u_short) (ACK_INTR|0x40)
  179 #      define C_UPD_STATS       (u_short) (ACK_INTR|0x80)
  180 #define SET_INTR_MASK           (u_short) (0xe<<11)
  181 #define SET_RD_0_MASK           (u_short) (0xf<<11)
  182 #define SET_RX_FILTER           (u_short) (0x10<<11)
  183 #      define FIL_INDIVIDUAL    (u_short) (0x1)
  184 #      define FIL_GROUP         (u_short) (0x2)
  185 #      define FIL_BRDCST        (u_short) (0x4)
  186 #      define FIL_ALL           (u_short) (0x8)
  187 #define SET_RX_EARLY_THRESH     (u_short) (0x11<<11)
  188 #define SET_TX_AVAIL_THRESH     (u_short) (0x12<<11)
  189 #define SET_TX_START_THRESH     (u_short) (0x13<<11)
  190 #define STATS_ENABLE            (u_short) (0x15<<11)
  191 #define STATS_DISABLE           (u_short) (0x16<<11)
  192 #define STOP_TRANSCEIVER        (u_short) (0x17<<11)
  193 
  194 /*
  195  * Status register. All windows.
  196  *
  197  *     15-13:  Window number(0-7).
  198  *     12:     Command_in_progress.
  199  *     11:     reserved.
  200  *     10:     reserved.
  201  *     9:      reserved.
  202  *     8:      reserved.
  203  *     7:      Update Statistics.
  204  *     6:      Interrupt Requested.
  205  *     5:      RX Early.
  206  *     4:      RX Complete.
  207  *     3:      TX Available.
  208  *     2:      TX Complete.
  209  *     1:      Adapter Failure.
  210  *     0:      Interrupt Latch.
  211  */
  212 #define S_INTR_LATCH            (u_short) (0x1)
  213 #define S_CARD_FAILURE          (u_short) (0x2)
  214 #define S_TX_COMPLETE           (u_short) (0x4)
  215 #define S_TX_AVAIL              (u_short) (0x8)
  216 #define S_RX_COMPLETE           (u_short) (0x10)
  217 #define S_RX_EARLY              (u_short) (0x20)
  218 #define S_INT_RQD               (u_short) (0x40)
  219 #define S_UPD_STATS             (u_short) (0x80)
  220 #define S_COMMAND_IN_PROGRESS   (u_short) (0x1000)
  221 
  222 /*
  223  * FIFO Registers.  RX Status.
  224  *
  225  *     15:     Incomplete or FIFO empty.
  226  *     14:     1: Error in RX Packet   0: Incomplete or no error.
  227  *     13-11:  Type of error.
  228  *            1000 = Overrun.
  229  *            1011 = Run Packet Error.
  230  *            1100 = Alignment Error.
  231  *            1101 = CRC Error.
  232  *            1001 = Oversize Packet Error (>1514 bytes)
  233  *            0010 = Dribble Bits.
  234  *            (all other error codes, no errors.)
  235  *
  236  *     10-0:   RX Bytes (0-1514)
  237  */
  238 #define ERR_INCOMPLETE  (u_short) (0x8000)
  239 #define ERR_RX          (u_short) (0x4000)
  240 #define ERR_RX_PACKET   (u_short) (0x2000)
  241 #define ERR_OVERRUN     (u_short) (0x1000)
  242 #define ERR_RUNT        (u_short) (0x1300)
  243 #define ERR_ALIGNMENT   (u_short) (0x1400)
  244 #define ERR_CRC         (u_short) (0x1500)
  245 #define ERR_OVERSIZE    (u_short) (0x1100)
  246 #define ERR_DRIBBLE     (u_short) (0x200)
  247 
  248 /*
  249  * TX Status
  250  *
  251  *   Reports the transmit status of a completed transmission. Writing this
  252  *   register pops the transmit completion stack.
  253  *
  254  *   Window 1/Port 0x0b.
  255  *
  256  *     7:      Complete
  257  *     6:      Interrupt on successful transmission requested.
  258  *     5:      Jabber Error (TP Only, TX Reset required. )
  259  *     4:      Underrun (TX Reset required. )
  260  *     3:      Maximum Collisions.
  261  *     2:      TX Status Overflow.
  262  *     1-0:    Undefined.
  263  *
  264  */
  265 #define TXS_COMPLETE            0x80
  266 #define TXS_INTR_REQ            0x40
  267 #define TXS_JABBER              0x20
  268 #define TXS_UNDERRUN            0x10
  269 #define TXS_MAX_COLLISION       0x8
  270 #define TXS_STATUS_OVERFLOW     0x4
  271 
  272 /*
  273  * Misc defines for various things.
  274  */
  275 #define TAG_ADAPTER_0                   0xd0
  276 #define ACTIVATE_ADAPTER_TO_CONFIG      0xff
  277 #define ENABLE_DRQ_IRQ                  0x0001
  278 #define MFG_ID                          0x6d50
  279 #define PROD_ID                         0x9150
  280 #define BASE                            sc->ep_io_addr
  281 #define GO_WINDOW(x)                    outw(BASE+EP_COMMAND, WINDOW_SELECT|x)
  282 #define AUI                             0x1
  283 #define BNC                             0x2
  284 #define UTP                             0x4
  285 #define IS_AUI                          (1<<13)
  286 #define IS_BNC                          (1<<12)
  287 #define IS_UTP                          (1<<9)
  288 #define EEPROM_BUSY                     (1<<15)
  289 #define EEPROM_TST_MODE                 (1<<14)
  290 #define READ_EEPROM                     (1<<7)
  291 #define ENABLE_UTP                      0xc0
  292 #define DISABLE_UTP                     0x0
  293 #define RX_BYTES_MASK                   (u_short) (0x07ff)
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FreeBSD/Linux Kernel Cross Reference sys/i386/isa/if_zpreg.h

FreeBSD/Linux Kernel Cross Reference
sys/i386/isa/if_zpreg.h
