The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/i386/isa/intr_machdep.c

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    1 /*-
    2  * Copyright (c) 1991 The Regents of the University of California.
    3  * All rights reserved.
    4  *
    5  * This code is derived from software contributed to Berkeley by
    6  * William Jolitz.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  * 3. All advertising materials mentioning features or use of this software
   17  *    must display the following acknowledgement:
   18  *      This product includes software developed by the University of
   19  *      California, Berkeley and its contributors.
   20  * 4. Neither the name of the University nor the names of its contributors
   21  *    may be used to endorse or promote products derived from this software
   22  *    without specific prior written permission.
   23  *
   24  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   25  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   26  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   27  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   28  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   29  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   30  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   31  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   32  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   33  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   34  * SUCH DAMAGE.
   35  *
   36  *      from: @(#)isa.c 7.2 (Berkeley) 5/13/91
   37  * $FreeBSD: releng/5.0/sys/i386/isa/intr_machdep.c 105536 2002-10-20 18:02:46Z phk $
   38  */
   39 
   40 #include "opt_auto_eoi.h"
   41 #include "opt_isa.h"
   42 #include "opt_mca.h"
   43 
   44 #include <sys/param.h>
   45 #include <sys/bus.h> 
   46 #include <sys/errno.h>
   47 #include <sys/interrupt.h>
   48 #include <sys/kernel.h>
   49 #include <sys/kthread.h>
   50 #include <sys/lock.h>
   51 #include <sys/malloc.h>
   52 #include <sys/module.h>
   53 #include <sys/mutex.h>
   54 #include <sys/proc.h>
   55 #include <sys/syslog.h>
   56 #include <sys/systm.h>
   57 #include <sys/unistd.h>
   58 
   59 #include <machine/md_var.h>
   60 #include <machine/segments.h>
   61 
   62 #if defined(APIC_IO)
   63 #include <machine/smptests.h>                   /** FAST_HI */
   64 #include <machine/smp.h>
   65 #include <machine/resource.h>
   66 #endif /* APIC_IO */
   67 #ifdef PC98
   68 #include <pc98/pc98/pc98.h>
   69 #include <pc98/pc98/pc98_machdep.h>
   70 #include <pc98/pc98/epsonio.h>
   71 #else
   72 #include <i386/isa/isa.h>
   73 #endif
   74 #include <i386/isa/icu.h>
   75 
   76 #ifdef DEV_ISA
   77 #include <isa/isavar.h>
   78 #endif
   79 #include <i386/isa/intr_machdep.h>
   80 #include <sys/interrupt.h>
   81 #ifdef APIC_IO
   82 #include <machine/clock.h>
   83 #endif
   84 
   85 #ifdef DEV_MCA
   86 #include <i386/isa/mca_machdep.h>
   87 #endif
   88 
   89 /*
   90  * Per-interrupt data.
   91  */
   92 u_long  *intr_countp[ICU_LEN];          /* pointers to interrupt counters */
   93 driver_intr_t   *intr_handler[ICU_LEN]; /* first level interrupt handler */
   94 struct   ithd *ithds[ICU_LEN];          /* real interrupt handler */
   95 void    *intr_unit[ICU_LEN];
   96 
   97 static struct   mtx ithds_table_lock;   /* protect the ithds table */
   98 
   99 static inthand_t *fastintr[ICU_LEN] = {
  100         IDTVEC(fastintr0), IDTVEC(fastintr1),
  101         IDTVEC(fastintr2), IDTVEC(fastintr3),
  102         IDTVEC(fastintr4), IDTVEC(fastintr5),
  103         IDTVEC(fastintr6), IDTVEC(fastintr7),
  104         IDTVEC(fastintr8), IDTVEC(fastintr9),
  105         IDTVEC(fastintr10), IDTVEC(fastintr11),
  106         IDTVEC(fastintr12), IDTVEC(fastintr13),
  107         IDTVEC(fastintr14), IDTVEC(fastintr15),
  108 #if defined(APIC_IO)
  109         IDTVEC(fastintr16), IDTVEC(fastintr17),
  110         IDTVEC(fastintr18), IDTVEC(fastintr19),
  111         IDTVEC(fastintr20), IDTVEC(fastintr21),
  112         IDTVEC(fastintr22), IDTVEC(fastintr23),
  113         IDTVEC(fastintr24), IDTVEC(fastintr25),
  114         IDTVEC(fastintr26), IDTVEC(fastintr27),
  115         IDTVEC(fastintr28), IDTVEC(fastintr29),
  116         IDTVEC(fastintr30), IDTVEC(fastintr31),
  117 #endif /* APIC_IO */
  118 };
  119 
  120 static unpendhand_t *fastunpend[ICU_LEN] = {
  121         IDTVEC(fastunpend0), IDTVEC(fastunpend1),
  122         IDTVEC(fastunpend2), IDTVEC(fastunpend3),
  123         IDTVEC(fastunpend4), IDTVEC(fastunpend5),
  124         IDTVEC(fastunpend6), IDTVEC(fastunpend7),
  125         IDTVEC(fastunpend8), IDTVEC(fastunpend9),
  126         IDTVEC(fastunpend10), IDTVEC(fastunpend11),
  127         IDTVEC(fastunpend12), IDTVEC(fastunpend13),
  128         IDTVEC(fastunpend14), IDTVEC(fastunpend15),
  129 #if defined(APIC_IO)
  130         IDTVEC(fastunpend16), IDTVEC(fastunpend17),
  131         IDTVEC(fastunpend18), IDTVEC(fastunpend19),
  132         IDTVEC(fastunpend20), IDTVEC(fastunpend21),
  133         IDTVEC(fastunpend22), IDTVEC(fastunpend23),
  134         IDTVEC(fastunpend24), IDTVEC(fastunpend25),
  135         IDTVEC(fastunpend26), IDTVEC(fastunpend27),
  136         IDTVEC(fastunpend28), IDTVEC(fastunpend29),
  137         IDTVEC(fastunpend30), IDTVEC(fastunpend31),
  138 #endif /* APIC_IO */
  139 };
  140 
  141 static inthand_t *slowintr[ICU_LEN] = {
  142         IDTVEC(intr0), IDTVEC(intr1), IDTVEC(intr2), IDTVEC(intr3),
  143         IDTVEC(intr4), IDTVEC(intr5), IDTVEC(intr6), IDTVEC(intr7),
  144         IDTVEC(intr8), IDTVEC(intr9), IDTVEC(intr10), IDTVEC(intr11),
  145         IDTVEC(intr12), IDTVEC(intr13), IDTVEC(intr14), IDTVEC(intr15),
  146 #if defined(APIC_IO)
  147         IDTVEC(intr16), IDTVEC(intr17), IDTVEC(intr18), IDTVEC(intr19),
  148         IDTVEC(intr20), IDTVEC(intr21), IDTVEC(intr22), IDTVEC(intr23),
  149         IDTVEC(intr24), IDTVEC(intr25), IDTVEC(intr26), IDTVEC(intr27),
  150         IDTVEC(intr28), IDTVEC(intr29), IDTVEC(intr30), IDTVEC(intr31),
  151 #endif /* APIC_IO */
  152 };
  153 
  154 static driver_intr_t isa_strayintr;
  155 
  156 static void     ithds_init(void *dummy);
  157 static void     ithread_enable(int vector);
  158 static void     ithread_disable(int vector);
  159 static void     init_i8259(void);
  160 
  161 #ifdef PC98
  162 #define NMI_PARITY 0x04
  163 #define NMI_EPARITY 0x02
  164 #else
  165 #define NMI_PARITY (1 << 7)
  166 #define NMI_IOCHAN (1 << 6)
  167 #define ENMI_WATCHDOG (1 << 7)
  168 #define ENMI_BUSTIMER (1 << 6)
  169 #define ENMI_IOSTATUS (1 << 5)
  170 #endif
  171 
  172 #ifdef DEV_ISA
  173 /*
  174  * Bus attachment for the ISA PIC.
  175  */
  176 static struct isa_pnp_id atpic_ids[] = {
  177         { 0x0000d041 /* PNP0000 */, "AT interrupt controller" },
  178         { 0 }
  179 };
  180 
  181 static int
  182 atpic_probe(device_t dev)
  183 {
  184         int result;
  185         
  186         if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, atpic_ids)) <= 0)
  187                 device_quiet(dev);
  188         return(result);
  189 }
  190 
  191 /*
  192  * In the APIC_IO case we might be granted IRQ 2, as this is typically
  193  * consumed by chaining between the two PIC components.  If we're using
  194  * the APIC, however, this may not be the case, and as such we should
  195  * free the resource.  (XXX untested)
  196  *
  197  * The generic ISA attachment code will handle allocating any other resources
  198  * that we don't explicitly claim here.
  199  */
  200 static int
  201 atpic_attach(device_t dev)
  202 {
  203 #ifdef APIC_IO
  204         int             rid;
  205         struct resource *res;
  206 
  207         /* try to allocate our IRQ and then free it */
  208         rid = 0;
  209         res = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 0);
  210         if (res != NULL)
  211                 bus_release_resource(dev, SYS_RES_IRQ, rid, res);
  212 #endif
  213         return(0);
  214 }
  215 
  216 static device_method_t atpic_methods[] = {
  217         /* Device interface */
  218         DEVMETHOD(device_probe,         atpic_probe),
  219         DEVMETHOD(device_attach,        atpic_attach),
  220         DEVMETHOD(device_detach,        bus_generic_detach),
  221         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
  222         DEVMETHOD(device_suspend,       bus_generic_suspend),
  223         DEVMETHOD(device_resume,        bus_generic_resume),
  224         { 0, 0 }
  225 };
  226 
  227 static driver_t atpic_driver = {
  228         "atpic",
  229         atpic_methods,
  230         1,              /* no softc */
  231 };
  232 
  233 static devclass_t atpic_devclass;
  234 
  235 DRIVER_MODULE(atpic, isa, atpic_driver, atpic_devclass, 0, 0);
  236 DRIVER_MODULE(atpic, acpi, atpic_driver, atpic_devclass, 0, 0);
  237 #endif /* DEV_ISA */
  238 
  239 /*
  240  * Handle a NMI, possibly a machine check.
  241  * return true to panic system, false to ignore.
  242  */
  243 int
  244 isa_nmi(cd)
  245         int cd;
  246 {
  247         int retval = 0;
  248 #ifdef PC98
  249         int port = inb(0x33);
  250 
  251         log(LOG_CRIT, "NMI PC98 port = %x\n", port);
  252         if (epson_machine_id == 0x20)
  253                 epson_outb(0xc16, epson_inb(0xc16) | 0x1);
  254         if (port & NMI_PARITY) {
  255                 log(LOG_CRIT, "BASE RAM parity error, likely hardware failure.");
  256                 retval = 1;
  257         } else if (port & NMI_EPARITY) {
  258                 log(LOG_CRIT, "EXTENDED RAM parity error, likely hardware failure.");
  259                 retval = 1;
  260         } else {
  261                 log(LOG_CRIT, "\nNMI Resume ??\n");
  262         }
  263 #else /* IBM-PC */
  264         int isa_port = inb(0x61);
  265         int eisa_port = inb(0x461);
  266 
  267         log(LOG_CRIT, "NMI ISA %x, EISA %x\n", isa_port, eisa_port);
  268 #ifdef DEV_MCA
  269         if (MCA_system && mca_bus_nmi())
  270                 return(0);
  271 #endif
  272         
  273         if (isa_port & NMI_PARITY) {
  274                 log(LOG_CRIT, "RAM parity error, likely hardware failure.");
  275                 retval = 1;
  276         }
  277 
  278         if (isa_port & NMI_IOCHAN) {
  279                 log(LOG_CRIT, "I/O channel check, likely hardware failure.");
  280                 retval = 1;
  281         }
  282 
  283         /*
  284          * On a real EISA machine, this will never happen.  However it can
  285          * happen on ISA machines which implement XT style floating point
  286          * error handling (very rare).  Save them from a meaningless panic.
  287          */
  288         if (eisa_port == 0xff)
  289                 return(retval);
  290 
  291         if (eisa_port & ENMI_WATCHDOG) {
  292                 log(LOG_CRIT, "EISA watchdog timer expired, likely hardware failure.");
  293                 retval = 1;
  294         }
  295 
  296         if (eisa_port & ENMI_BUSTIMER) {
  297                 log(LOG_CRIT, "EISA bus timeout, likely hardware failure.");
  298                 retval = 1;
  299         }
  300 
  301         if (eisa_port & ENMI_IOSTATUS) {
  302                 log(LOG_CRIT, "EISA I/O port status error.");
  303                 retval = 1;
  304         }
  305 #endif
  306         return(retval);
  307 }
  308 
  309 /*
  310  *  ICU reinitialize when ICU configuration has lost.
  311  */
  312 void icu_reinit()
  313 {
  314         int i;
  315         register_t crit;
  316 
  317         crit = intr_disable();
  318         mtx_lock_spin(&icu_lock);
  319         init_i8259();
  320         for(i=0;i<ICU_LEN;i++)
  321                 if(intr_handler[i] != isa_strayintr)
  322                         INTREN(1<<i);
  323         mtx_unlock_spin(&icu_lock);
  324         intr_restore(crit);
  325 }
  326 
  327 /*
  328  * Create a default interrupt table to avoid problems caused by
  329  * spurious interrupts during configuration of kernel, then setup
  330  * interrupt control unit.
  331  */
  332 void
  333 isa_defaultirq()
  334 {
  335         int i;
  336         register_t crit;
  337 
  338         /* icu vectors */
  339         for (i = 0; i < ICU_LEN; i++)
  340                 icu_unset(i, (driver_intr_t *)NULL);
  341         crit = intr_disable();
  342         mtx_lock_spin(&icu_lock);
  343         init_i8259();
  344         mtx_unlock_spin(&icu_lock);
  345         intr_restore(crit);
  346 }
  347 
  348 
  349 /* 
  350  *initialize 8259's
  351  */
  352 static void init_i8259()
  353 {
  354 
  355 #ifdef DEV_MCA
  356         if (MCA_system)
  357                 outb(IO_ICU1, 0x19);            /* reset; program device, four bytes */
  358         else
  359 #endif
  360                 outb(IO_ICU1, 0x11);            /* reset; program device, four bytes */
  361 
  362         outb(IO_ICU1+ICU_IMR_OFFSET, NRSVIDT);  /* starting at this vector index */
  363         outb(IO_ICU1+ICU_IMR_OFFSET, IRQ_SLAVE);                /* slave on line 7 */
  364 #ifdef PC98
  365 #ifdef AUTO_EOI_1
  366         outb(IO_ICU1+ICU_IMR_OFFSET, 0x1f);             /* (master) auto EOI, 8086 mode */
  367 #else
  368         outb(IO_ICU1+ICU_IMR_OFFSET, 0x1d);             /* (master) 8086 mode */
  369 #endif
  370 #else /* IBM-PC */
  371 #ifdef AUTO_EOI_1
  372         outb(IO_ICU1+ICU_IMR_OFFSET, 2 | 1);            /* auto EOI, 8086 mode */
  373 #else
  374         outb(IO_ICU1+ICU_IMR_OFFSET, 1);                /* 8086 mode */
  375 #endif
  376 #endif /* PC98 */
  377         outb(IO_ICU1+ICU_IMR_OFFSET, 0xff);             /* leave interrupts masked */
  378         outb(IO_ICU1, 0x0a);            /* default to IRR on read */
  379 #ifndef PC98
  380         outb(IO_ICU1, 0xc0 | (3 - 1));  /* pri order 3-7, 0-2 (com2 first) */
  381 #endif /* !PC98 */
  382 
  383 #ifdef DEV_MCA
  384         if (MCA_system)
  385                 outb(IO_ICU2, 0x19);            /* reset; program device, four bytes */
  386         else
  387 #endif
  388                 outb(IO_ICU2, 0x11);            /* reset; program device, four bytes */
  389 
  390         outb(IO_ICU2+ICU_IMR_OFFSET, NRSVIDT+8); /* staring at this vector index */
  391         outb(IO_ICU2+ICU_IMR_OFFSET, ICU_SLAVEID);         /* my slave id is 7 */
  392 #ifdef PC98
  393         outb(IO_ICU2+ICU_IMR_OFFSET,9);              /* 8086 mode */
  394 #else /* IBM-PC */
  395 #ifdef AUTO_EOI_2
  396         outb(IO_ICU2+ICU_IMR_OFFSET, 2 | 1);            /* auto EOI, 8086 mode */
  397 #else
  398         outb(IO_ICU2+ICU_IMR_OFFSET,1);         /* 8086 mode */
  399 #endif
  400 #endif /* PC98 */
  401         outb(IO_ICU2+ICU_IMR_OFFSET, 0xff);          /* leave interrupts masked */
  402         outb(IO_ICU2, 0x0a);            /* default to IRR on read */
  403 }
  404 
  405 /*
  406  * Caught a stray interrupt, notify
  407  */
  408 static void
  409 isa_strayintr(vcookiep)
  410         void *vcookiep;
  411 {
  412         int intr = (void **)vcookiep - &intr_unit[0];
  413 
  414         /*
  415          * XXX TODO print a different message for #7 if it is for a
  416          * glitch.  Glitches can be distinguished from real #7's by
  417          * testing that the in-service bit is _not_ set.  The test
  418          * must be done before sending an EOI so it can't be done if
  419          * we are using AUTO_EOI_1.
  420          */
  421         if (intrcnt[1 + intr] <= 5)
  422                 log(LOG_ERR, "stray irq %d\n", intr);
  423         if (intrcnt[1 + intr] == 5)
  424                 log(LOG_CRIT,
  425                     "too many stray irq %d's; not logging any more\n", intr);
  426 }
  427 
  428 #ifdef DEV_ISA
  429 /*
  430  * Return a bitmap of the current interrupt requests.  This is 8259-specific
  431  * and is only suitable for use at probe time.
  432  */
  433 intrmask_t
  434 isa_irq_pending()
  435 {
  436         u_char irr1;
  437         u_char irr2;
  438 
  439         irr1 = inb(IO_ICU1);
  440         irr2 = inb(IO_ICU2);
  441         return ((irr2 << 8) | irr1);
  442 }
  443 #endif
  444 
  445 /*
  446  * Update intrnames array with the specified name.  This is used by
  447  * vmstat(8) and the like.
  448  */
  449 static void
  450 update_intrname(int intr, const char *name)
  451 {
  452         char buf[32];
  453         char *cp;
  454         int name_index, off, strayintr;
  455 
  456         /*
  457          * Initialise strings for bitbucket and stray interrupt counters.
  458          * These have statically allocated indices 0 and 1 through ICU_LEN.
  459          */
  460         if (intrnames[0] == '\0') {
  461                 off = sprintf(intrnames, "???") + 1;
  462                 for (strayintr = 0; strayintr < ICU_LEN; strayintr++)
  463                         off += sprintf(intrnames + off, "stray irq%d",
  464                             strayintr) + 1;
  465         }
  466 
  467         if (name == NULL)
  468                 name = "???";
  469         if (snprintf(buf, sizeof(buf), "%s irq%d", name, intr) >= sizeof(buf))
  470                 goto use_bitbucket;
  471 
  472         /*
  473          * Search for `buf' in `intrnames'.  In the usual case when it is
  474          * not found, append it to the end if there is enough space (the \0
  475          * terminator for the previous string, if any, becomes a separator).
  476          */
  477         for (cp = intrnames, name_index = 0;
  478             cp != eintrnames && name_index < NR_INTRNAMES;
  479             cp += strlen(cp) + 1, name_index++) {
  480                 if (*cp == '\0') {
  481                         if (strlen(buf) >= eintrnames - cp)
  482                                 break;
  483                         strcpy(cp, buf);
  484                         goto found;
  485                 }
  486                 if (strcmp(cp, buf) == 0)
  487                         goto found;
  488         }
  489 
  490 use_bitbucket:
  491         printf("update_intrname: counting %s irq%d as %s\n", name, intr,
  492             intrnames);
  493         name_index = 0;
  494 found:
  495         intr_countp[intr] = &intrcnt[name_index];
  496 }
  497 
  498 int
  499 icu_setup(int intr, driver_intr_t *handler, void *arg, int flags)
  500 {
  501 #ifdef FAST_HI
  502         int             select;         /* the select register is 8 bits */
  503         int             vector;
  504         u_int32_t       value;          /* the window register is 32 bits */
  505 #endif /* FAST_HI */
  506         register_t      crit;
  507 
  508 #if defined(APIC_IO)
  509         if ((u_int)intr >= ICU_LEN)     /* no 8259 SLAVE to ignore */
  510 #else
  511         if ((u_int)intr >= ICU_LEN || intr == ICU_SLAVEID)
  512 #endif /* APIC_IO */
  513                 return (EINVAL);
  514 #if 0
  515         if (intr_handler[intr] != isa_strayintr)
  516                 return (EBUSY);
  517 #endif
  518 
  519         crit = intr_disable();
  520         mtx_lock_spin(&icu_lock);
  521         intr_handler[intr] = handler;
  522         intr_unit[intr] = arg;
  523 #ifdef FAST_HI
  524         if (flags & INTR_FAST) {
  525                 vector = TPR_FAST_INTS + intr;
  526                 setidt(vector, fastintr[intr],
  527                        SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
  528         }
  529         else {
  530                 vector = TPR_SLOW_INTS + intr;
  531                 setidt(vector, slowintr[intr],
  532                        SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
  533         }
  534 #ifdef APIC_INTR_REORDER
  535         set_lapic_isrloc(intr, vector);
  536 #endif
  537         /*
  538          * Reprogram the vector in the IO APIC.
  539          */
  540         if (int_to_apicintpin[intr].ioapic >= 0) {
  541                 select = int_to_apicintpin[intr].redirindex;
  542                 value = io_apic_read(int_to_apicintpin[intr].ioapic, 
  543                                      select) & ~IOART_INTVEC;
  544                 io_apic_write(int_to_apicintpin[intr].ioapic, 
  545                               select, value | vector);
  546         }
  547 #else
  548         setidt(ICU_OFFSET + intr,
  549                flags & INTR_FAST ? fastintr[intr] : slowintr[intr],
  550                SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
  551 #endif /* FAST_HI */
  552         INTREN(1 << intr);
  553         mtx_unlock_spin(&icu_lock);
  554         intr_restore(crit);
  555         return (0);
  556 }
  557 
  558 /*
  559  * Dissociate an interrupt handler from an IRQ and set the handler to
  560  * the stray interrupt handler.  The 'handler' parameter is used only
  561  * for consistency checking.
  562  */
  563 int
  564 icu_unset(intr, handler)
  565         int     intr;
  566         driver_intr_t *handler;
  567 {
  568         register_t crit;
  569 
  570         if ((u_int)intr >= ICU_LEN || handler != intr_handler[intr])
  571                 return (EINVAL);
  572 
  573         crit = intr_disable();
  574         mtx_lock_spin(&icu_lock);
  575         INTRDIS(1 << intr);
  576         intr_countp[intr] = &intrcnt[1 + intr];
  577         intr_handler[intr] = isa_strayintr;
  578         intr_unit[intr] = &intr_unit[intr];
  579 #ifdef FAST_HI_XXX
  580         /* XXX how do I re-create dvp here? */
  581         setidt(flags & INTR_FAST ? TPR_FAST_INTS + intr : TPR_SLOW_INTS + intr,
  582             slowintr[intr], SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
  583 #else /* FAST_HI */
  584 #ifdef APIC_INTR_REORDER
  585         set_lapic_isrloc(intr, ICU_OFFSET + intr);
  586 #endif
  587         setidt(ICU_OFFSET + intr, slowintr[intr], SDT_SYS386IGT, SEL_KPL,
  588             GSEL(GCODE_SEL, SEL_KPL));
  589 #endif /* FAST_HI */
  590         mtx_unlock_spin(&icu_lock);
  591         intr_restore(crit);
  592         return (0);
  593 }
  594 
  595 static void
  596 ithds_init(void *dummy)
  597 {
  598 
  599         mtx_init(&ithds_table_lock, "ithread table lock", NULL, MTX_SPIN);
  600 }
  601 SYSINIT(ithds_init, SI_SUB_INTR, SI_ORDER_SECOND, ithds_init, NULL);
  602 
  603 static void
  604 ithread_enable(int vector)
  605 {
  606         register_t crit;
  607 
  608         crit = intr_disable();
  609         mtx_lock_spin(&icu_lock);
  610         INTREN(1 << vector);
  611         mtx_unlock_spin(&icu_lock);
  612         intr_restore(crit);
  613 }
  614 
  615 static void
  616 ithread_disable(int vector)
  617 {
  618         register_t crit;
  619 
  620         crit = intr_disable();
  621         mtx_lock_spin(&icu_lock);
  622         INTRDIS(1 << vector);
  623         mtx_unlock_spin(&icu_lock);
  624         intr_restore(crit);
  625 }
  626 
  627 int
  628 inthand_add(const char *name, int irq, driver_intr_t handler, void *arg,
  629     enum intr_type flags, void **cookiep)
  630 {
  631         struct ithd *ithd;              /* descriptor for the IRQ */
  632         int errcode = 0;
  633         int created_ithd = 0;
  634 
  635         /*
  636          * Work around a race where more than one CPU may be registering
  637          * handlers on the same IRQ at the same time.
  638          */
  639         mtx_lock_spin(&ithds_table_lock);
  640         ithd = ithds[irq];
  641         mtx_unlock_spin(&ithds_table_lock);
  642         if (ithd == NULL) {
  643                 errcode = ithread_create(&ithd, irq, 0, ithread_disable,
  644                     ithread_enable, "irq%d:", irq);
  645                 if (errcode)
  646                         return (errcode);
  647                 mtx_lock_spin(&ithds_table_lock);
  648                 if (ithds[irq] == NULL) {
  649                         ithds[irq] = ithd;
  650                         created_ithd++;
  651                         mtx_unlock_spin(&ithds_table_lock);
  652                 } else {
  653                         struct ithd *orphan;
  654 
  655                         orphan = ithd;
  656                         ithd = ithds[irq];
  657                         mtx_unlock_spin(&ithds_table_lock);
  658                         ithread_destroy(orphan);
  659                 }
  660         }
  661 
  662         errcode = ithread_add_handler(ithd, name, handler, arg,
  663             ithread_priority(flags), flags, cookiep);
  664         
  665         if ((flags & INTR_FAST) == 0 || errcode)
  666                 /*
  667                  * The interrupt process must be in place, but
  668                  * not necessarily schedulable, before we
  669                  * initialize the ICU, since it may cause an
  670                  * immediate interrupt.
  671                  */
  672                 if (icu_setup(irq, sched_ithd, arg, flags) != 0)
  673                         panic("inthand_add: Can't initialize ICU");
  674 
  675         if (errcode)
  676                 return (errcode);
  677         
  678         if (flags & INTR_FAST) {
  679                 errcode = icu_setup(irq, handler, arg, flags);
  680                 if (errcode && bootverbose)
  681                         printf("\tinthand_add(irq%d) failed, result=%d\n", 
  682                                irq, errcode);
  683                 if (errcode)
  684                         return (errcode);
  685         }
  686 
  687         update_intrname(irq, name);
  688         return (0);
  689 }
  690 
  691 /*
  692  * Deactivate and remove linked list the interrupt handler descriptor
  693  * data connected created by an earlier call of inthand_add(), then
  694  * adjust the interrupt masks if necessary.
  695  *
  696  * Return the memory held by the interrupt handler descriptor data
  697  * structure to the system.  First ensure the handler is not actively
  698  * in use.
  699  */
  700 int
  701 inthand_remove(void *cookie)
  702 {
  703 
  704         return (ithread_remove_handler(cookie));
  705 }
  706 
  707 void
  708 call_fast_unpend(int irq)
  709 {
  710         fastunpend[irq]();
  711 }
  712 

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