The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/i386/isa/intr_machdep.h

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    1 /*-
    2  * Copyright (c) 1991 The Regents of the University of California.
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  * 3. All advertising materials mentioning features or use of this software
   14  *    must display the following acknowledgement:
   15  *      This product includes software developed by the University of
   16  *      California, Berkeley and its contributors.
   17  * 4. Neither the name of the University nor the names of its contributors
   18  *    may be used to endorse or promote products derived from this software
   19  *    without specific prior written permission.
   20  *
   21  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   24  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   25  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   26  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   27  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   28  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   31  * SUCH DAMAGE.
   32  *
   33  * $FreeBSD: releng/5.0/sys/i386/isa/intr_machdep.h 99862 2002-07-12 07:56:11Z peter $
   34  */
   35 
   36 #ifndef _I386_ISA_INTR_MACHDEP_H_
   37 #define _I386_ISA_INTR_MACHDEP_H_
   38 
   39 /*
   40  * Low level interrupt code.
   41  */ 
   42 
   43 #ifdef _KERNEL
   44 
   45 #if defined(SMP) || defined(APIC_IO)
   46 /*
   47  * XXX FIXME: rethink location for all IPI vectors.
   48  */
   49 
   50 /*
   51     APIC TPR priority vector levels:
   52 
   53         0xff (255) +-------------+
   54                    |             | 15 (IPIs: Xspuriousint)
   55         0xf0 (240) +-------------+
   56                    |             | 14
   57         0xe0 (224) +-------------+
   58                    |             | 13
   59         0xd0 (208) +-------------+
   60                    |             | 12
   61         0xc0 (192) +-------------+
   62                    |             | 11
   63         0xb0 (176) +-------------+
   64                    |             | 10 (IPIs: Xcpustop)
   65         0xa0 (160) +-------------+
   66                    |             |  9 (IPIs: Xinvltlb)
   67         0x90 (144) +-------------+
   68                    |             |  8 (linux/BSD syscall, IGNORE FAST HW INTS)
   69         0x80 (128) +-------------+
   70                    |             |  7 (FAST_INTR 16-23)
   71         0x70 (112) +-------------+
   72                    |             |  6 (FAST_INTR 0-15)
   73         0x60 (96)  +-------------+
   74                    |             |  5 (IGNORE HW INTS)
   75         0x50 (80)  +-------------+
   76                    |             |  4 (2nd IO APIC)
   77         0x40 (64)  +------+------+
   78                    |      |      |  3 (upper APIC hardware INTs: PCI)
   79         0x30 (48)  +------+------+
   80                    |             |  2 (start of hardware INTs: ISA)
   81         0x20 (32)  +-------------+
   82                    |             |  1 (exceptions, traps, etc.)
   83         0x10 (16)  +-------------+
   84                    |             |  0 (exceptions, traps, etc.)
   85         0x00 (0)   +-------------+
   86  */
   87 
   88 /* IDT vector base for regular (aka. slow) and fast interrupts */
   89 #define TPR_SLOW_INTS           0x20
   90 #define TPR_FAST_INTS           0x60
   91 /* XXX note that the AST interrupt is at 0x50 */
   92 
   93 /* blocking values for local APIC Task Priority Register */
   94 #define TPR_BLOCK_HWI           0x4f            /* hardware INTs */
   95 #define TPR_IGNORE_HWI          0x5f            /* ignore INTs */
   96 #define TPR_BLOCK_FHWI          0x7f            /* hardware FAST INTs */
   97 #define TPR_IGNORE_FHWI         0x8f            /* ignore FAST INTs */
   98 #define TPR_BLOCK_XINVLTLB      0x9f            /*  */
   99 #define TPR_BLOCK_XCPUSTOP      0xaf            /*  */
  100 #define TPR_BLOCK_ALL           0xff            /* all INTs */
  101 
  102 #ifdef TEST_TEST1
  103 /* put a 'fake' HWI in top of APIC prio 0x3x, 32 + 31 = 63 = 0x3f */
  104 #define XTEST1_OFFSET           (ICU_OFFSET + 31)
  105 #endif /** TEST_TEST1 */
  106 
  107 /* TLB shootdowns */
  108 #define XINVLTLB_OFFSET         (ICU_OFFSET + 112)      /* 0x90 */
  109 #define XINVLPG_OFFSET          (ICU_OFFSET + 113)      /* 0x91 */
  110 #define XINVLRNG_OFFSET         (ICU_OFFSET + 114)      /* 0x92 */
  111 
  112 /* inter-cpu clock handling */
  113 #define XHARDCLOCK_OFFSET       (ICU_OFFSET + 120)      /* 0x98 */
  114 #define XSTATCLOCK_OFFSET       (ICU_OFFSET + 121)      /* 0x99 */
  115 
  116 /* inter-CPU rendezvous */
  117 #define XRENDEZVOUS_OFFSET      (ICU_OFFSET + 122)      /* 0x9A */
  118 
  119 /* IPI to generate an additional software trap at the target CPU */
  120 /* XXX in the middle of the interrupt range, overlapping IRQ48 */
  121 #define XCPUAST_OFFSET          (ICU_OFFSET +  48)      /* 0x50 */
  122 
  123 /* IPI to signal CPUs to stop and wait for another CPU to restart them */
  124 #define XCPUSTOP_OFFSET         (ICU_OFFSET + 128)      /* 0xA0 */
  125 
  126 /*
  127  * Note: this vector MUST be xxxx1111, 32 + 223 = 255 = 0xff:
  128  */
  129 #define XSPURIOUSINT_OFFSET     (ICU_OFFSET + 223)
  130 
  131 #endif /* SMP || APIC_IO */
  132 
  133 #ifdef LOCORE
  134 
  135 /*
  136  * Protects the IO APIC, 8259 PIC, imen, and apic_imen
  137  */
  138 #define ICU_LOCK        MTX_LOCK_SPIN(icu_lock, 0)
  139 #define ICU_UNLOCK      MTX_UNLOCK_SPIN(icu_lock)
  140 
  141 #else /* LOCORE */
  142 
  143 /*
  144  * Type of the first (asm) part of an interrupt handler.
  145  */
  146 typedef void inthand_t(u_int cs, u_int ef, u_int esp, u_int ss);
  147 typedef void unpendhand_t(void);
  148 
  149 #define IDTVEC(name)    __CONCAT(X,name)
  150 
  151 extern u_long *intr_countp[];   /* pointers into intrcnt[] */
  152 extern driver_intr_t *intr_handler[];   /* C entry points of intr handlers */
  153 extern struct ithd *ithds[];
  154 extern void *intr_unit[];       /* cookies to pass to intr handlers */
  155 extern struct mtx icu_lock;
  156 
  157 inthand_t
  158         IDTVEC(fastintr0), IDTVEC(fastintr1),
  159         IDTVEC(fastintr2), IDTVEC(fastintr3),
  160         IDTVEC(fastintr4), IDTVEC(fastintr5),
  161         IDTVEC(fastintr6), IDTVEC(fastintr7),
  162         IDTVEC(fastintr8), IDTVEC(fastintr9),
  163         IDTVEC(fastintr10), IDTVEC(fastintr11),
  164         IDTVEC(fastintr12), IDTVEC(fastintr13),
  165         IDTVEC(fastintr14), IDTVEC(fastintr15);
  166 inthand_t
  167         IDTVEC(intr0), IDTVEC(intr1), IDTVEC(intr2), IDTVEC(intr3),
  168         IDTVEC(intr4), IDTVEC(intr5), IDTVEC(intr6), IDTVEC(intr7),
  169         IDTVEC(intr8), IDTVEC(intr9), IDTVEC(intr10), IDTVEC(intr11),
  170         IDTVEC(intr12), IDTVEC(intr13), IDTVEC(intr14), IDTVEC(intr15);
  171 unpendhand_t
  172         IDTVEC(fastunpend0), IDTVEC(fastunpend1), IDTVEC(fastunpend2),
  173         IDTVEC(fastunpend3), IDTVEC(fastunpend4), IDTVEC(fastunpend5),
  174         IDTVEC(fastunpend6), IDTVEC(fastunpend7), IDTVEC(fastunpend8),
  175         IDTVEC(fastunpend9), IDTVEC(fastunpend10), IDTVEC(fastunpend11),
  176         IDTVEC(fastunpend12), IDTVEC(fastunpend13), IDTVEC(fastunpend14),
  177         IDTVEC(fastunpend15), IDTVEC(fastunpend16), IDTVEC(fastunpend17),
  178         IDTVEC(fastunpend18), IDTVEC(fastunpend19), IDTVEC(fastunpend20),
  179         IDTVEC(fastunpend21), IDTVEC(fastunpend22), IDTVEC(fastunpend23),
  180         IDTVEC(fastunpend24), IDTVEC(fastunpend25), IDTVEC(fastunpend26),
  181         IDTVEC(fastunpend27), IDTVEC(fastunpend28), IDTVEC(fastunpend29),
  182         IDTVEC(fastunpend30), IDTVEC(fastunpend31);
  183 
  184 #if defined(SMP) || defined(APIC_IO)
  185 inthand_t
  186         IDTVEC(fastintr16), IDTVEC(fastintr17),
  187         IDTVEC(fastintr18), IDTVEC(fastintr19),
  188         IDTVEC(fastintr20), IDTVEC(fastintr21),
  189         IDTVEC(fastintr22), IDTVEC(fastintr23),
  190         IDTVEC(fastintr24), IDTVEC(fastintr25),
  191         IDTVEC(fastintr26), IDTVEC(fastintr27),
  192         IDTVEC(fastintr28), IDTVEC(fastintr29),
  193         IDTVEC(fastintr30), IDTVEC(fastintr31);
  194 inthand_t
  195         IDTVEC(intr16), IDTVEC(intr17), IDTVEC(intr18), IDTVEC(intr19),
  196         IDTVEC(intr20), IDTVEC(intr21), IDTVEC(intr22), IDTVEC(intr23),
  197         IDTVEC(intr24), IDTVEC(intr25), IDTVEC(intr26), IDTVEC(intr27),
  198         IDTVEC(intr28), IDTVEC(intr29), IDTVEC(intr30), IDTVEC(intr31);
  199 
  200 inthand_t
  201         Xinvltlb,       /* TLB shootdowns - global */
  202         Xinvlpg,        /* TLB shootdowns - 1 page */
  203         Xinvlrng,       /* TLB shootdowns - page range */
  204         Xhardclock,     /* Forward hardclock() */
  205         Xstatclock,     /* Forward statclock() */
  206         Xcpuast,        /* Additional software trap on other cpu */ 
  207         Xcpustop,       /* CPU stops & waits for another CPU to restart it */
  208         Xspuriousint,   /* handle APIC "spurious INTs" */
  209         Xrendezvous;    /* handle CPU rendezvous */
  210 
  211 #ifdef TEST_TEST1
  212 inthand_t
  213         Xtest1;         /* 'fake' HWI at top of APIC prio 0x3x, 32+31 = 0x3f */
  214 #endif /** TEST_TEST1 */
  215 #endif /* SMP || APIC_IO */
  216 
  217 #ifdef APIC_IO
  218 /*
  219  * This is to accommodate "mixed-mode" programming for 
  220  * motherboards that don't connect the 8254 to the IO APIC.
  221  */
  222 #define AUTO_EOI_1      1
  223 #endif
  224 
  225 #define NR_INTRNAMES    (1 + ICU_LEN + 2 * ICU_LEN)
  226 
  227 void    isa_defaultirq(void);
  228 int     isa_nmi(int cd);
  229 int     icu_setup(int intr, driver_intr_t *func, void *arg, int flags);
  230 int     icu_unset(int intr, driver_intr_t *handler);
  231 void    icu_reinit(void);
  232 
  233 /*
  234  * WARNING: These are internal functions and not to be used by device drivers!
  235  * They are subject to change without notice. 
  236  */
  237 int     inthand_add(const char *name, int irq, driver_intr_t handler, void *arg,
  238             enum intr_type flags, void **cookiep);
  239 int     inthand_remove(void *cookie);
  240 void    sched_ithd(void *dummy);
  241 void    call_fast_unpend(int irq);
  242 
  243 #endif /* LOCORE */
  244 
  245 #endif /* _KERNEL */
  246 
  247 #endif /* !_I386_ISA_INTR_MACHDEP_H_ */

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