1 /*-
2 * Copyright (c) 1991 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by the University of
16 * California, Berkeley and its contributors.
17 * 4. Neither the name of the University nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 *
33 * $FreeBSD: releng/5.1/sys/i386/isa/intr_machdep.h 112993 2003-04-02 23:53:30Z peter $
34 */
35
36 #ifndef _I386_ISA_INTR_MACHDEP_H_
37 #define _I386_ISA_INTR_MACHDEP_H_
38
39 /*
40 * Low level interrupt code.
41 */
42
43 #ifdef _KERNEL
44
45 #if defined(SMP) || defined(APIC_IO)
46 /*
47 * XXX FIXME: rethink location for all IPI vectors.
48 */
49
50 /*
51 APIC TPR priority vector levels:
52
53 0xff (255) +-------------+
54 | | 15 (IPIs: Xspuriousint)
55 0xf0 (240) +-------------+
56 | | 14
57 0xe0 (224) +-------------+
58 | | 13
59 0xd0 (208) +-------------+
60 | | 12
61 0xc0 (192) +-------------+
62 | | 11
63 0xb0 (176) +-------------+
64 | | 10 (IPIs: Xcpustop)
65 0xa0 (160) +-------------+
66 | | 9 (IPIs: Xinvltlb)
67 0x90 (144) +-------------+
68 | | 8 (linux/BSD syscall, IGNORE FAST HW INTS)
69 0x80 (128) +-------------+
70 | | 7 (FAST_INTR 16-23)
71 0x70 (112) +-------------+
72 | | 6 (FAST_INTR 0-15)
73 0x60 (96) +-------------+
74 | | 5 (IGNORE HW INTS)
75 0x50 (80) +-------------+
76 | | 4 (2nd IO APIC)
77 0x40 (64) +------+------+
78 | | | 3 (upper APIC hardware INTs: PCI)
79 0x30 (48) +------+------+
80 | | 2 (start of hardware INTs: ISA)
81 0x20 (32) +-------------+
82 | | 1 (exceptions, traps, etc.)
83 0x10 (16) +-------------+
84 | | 0 (exceptions, traps, etc.)
85 0x00 (0) +-------------+
86 */
87
88 /* IDT vector base for regular (aka. slow) and fast interrupts */
89 #define TPR_SLOW_INTS 0x20
90 #define TPR_FAST_INTS 0x60
91 /* XXX note that the AST interrupt is at 0x50 */
92
93 /* blocking values for local APIC Task Priority Register */
94 #define TPR_BLOCK_HWI 0x4f /* hardware INTs */
95 #define TPR_IGNORE_HWI 0x5f /* ignore INTs */
96 #define TPR_BLOCK_FHWI 0x7f /* hardware FAST INTs */
97 #define TPR_IGNORE_FHWI 0x8f /* ignore FAST INTs */
98 #define TPR_BLOCK_XINVLTLB 0x9f /* */
99 #define TPR_BLOCK_XCPUSTOP 0xaf /* */
100 #define TPR_BLOCK_ALL 0xff /* all INTs */
101
102 #ifdef TEST_TEST1
103 /* put a 'fake' HWI in top of APIC prio 0x3x, 32 + 31 = 63 = 0x3f */
104 #define XTEST1_OFFSET (ICU_OFFSET + 31)
105 #endif /** TEST_TEST1 */
106
107 /* TLB shootdowns */
108 #define XINVLTLB_OFFSET (ICU_OFFSET + 112) /* 0x90 */
109 #define XINVLPG_OFFSET (ICU_OFFSET + 113) /* 0x91 */
110 #define XINVLRNG_OFFSET (ICU_OFFSET + 114) /* 0x92 */
111
112 /* inter-cpu clock handling */
113 #define XHARDCLOCK_OFFSET (ICU_OFFSET + 120) /* 0x98 */
114 #define XSTATCLOCK_OFFSET (ICU_OFFSET + 121) /* 0x99 */
115
116 /* inter-CPU rendezvous */
117 #define XRENDEZVOUS_OFFSET (ICU_OFFSET + 122) /* 0x9A */
118
119 /* lazy pmap release */
120 #define XLAZYPMAP_OFFSET (ICU_OFFSET + 123) /* 0x9B */
121
122 /* IPI to generate an additional software trap at the target CPU */
123 /* XXX in the middle of the interrupt range, overlapping IRQ48 */
124 #define XCPUAST_OFFSET (ICU_OFFSET + 48) /* 0x50 */
125
126 /* IPI to signal CPUs to stop and wait for another CPU to restart them */
127 #define XCPUSTOP_OFFSET (ICU_OFFSET + 128) /* 0xA0 */
128
129 /*
130 * Note: this vector MUST be xxxx1111, 32 + 223 = 255 = 0xff:
131 */
132 #define XSPURIOUSINT_OFFSET (ICU_OFFSET + 223)
133
134 #endif /* SMP || APIC_IO */
135
136 #ifdef LOCORE
137
138 /*
139 * Protects the IO APIC, 8259 PIC, imen, and apic_imen
140 */
141 #define ICU_LOCK MTX_LOCK_SPIN(icu_lock, 0)
142 #define ICU_UNLOCK MTX_UNLOCK_SPIN(icu_lock)
143
144 #else /* LOCORE */
145
146 /*
147 * Type of the first (asm) part of an interrupt handler.
148 */
149 typedef void inthand_t(u_int cs, u_int ef, u_int esp, u_int ss);
150 typedef void unpendhand_t(void);
151
152 #define IDTVEC(name) __CONCAT(X,name)
153
154 extern u_long *intr_countp[]; /* pointers into intrcnt[] */
155 extern driver_intr_t *intr_handler[]; /* C entry points of intr handlers */
156 extern struct ithd *ithds[];
157 extern void *intr_unit[]; /* cookies to pass to intr handlers */
158 extern struct mtx icu_lock;
159
160 inthand_t
161 IDTVEC(fastintr0), IDTVEC(fastintr1),
162 IDTVEC(fastintr2), IDTVEC(fastintr3),
163 IDTVEC(fastintr4), IDTVEC(fastintr5),
164 IDTVEC(fastintr6), IDTVEC(fastintr7),
165 IDTVEC(fastintr8), IDTVEC(fastintr9),
166 IDTVEC(fastintr10), IDTVEC(fastintr11),
167 IDTVEC(fastintr12), IDTVEC(fastintr13),
168 IDTVEC(fastintr14), IDTVEC(fastintr15);
169 inthand_t
170 IDTVEC(intr0), IDTVEC(intr1), IDTVEC(intr2), IDTVEC(intr3),
171 IDTVEC(intr4), IDTVEC(intr5), IDTVEC(intr6), IDTVEC(intr7),
172 IDTVEC(intr8), IDTVEC(intr9), IDTVEC(intr10), IDTVEC(intr11),
173 IDTVEC(intr12), IDTVEC(intr13), IDTVEC(intr14), IDTVEC(intr15);
174 unpendhand_t
175 IDTVEC(fastunpend0), IDTVEC(fastunpend1), IDTVEC(fastunpend2),
176 IDTVEC(fastunpend3), IDTVEC(fastunpend4), IDTVEC(fastunpend5),
177 IDTVEC(fastunpend6), IDTVEC(fastunpend7), IDTVEC(fastunpend8),
178 IDTVEC(fastunpend9), IDTVEC(fastunpend10), IDTVEC(fastunpend11),
179 IDTVEC(fastunpend12), IDTVEC(fastunpend13), IDTVEC(fastunpend14),
180 IDTVEC(fastunpend15), IDTVEC(fastunpend16), IDTVEC(fastunpend17),
181 IDTVEC(fastunpend18), IDTVEC(fastunpend19), IDTVEC(fastunpend20),
182 IDTVEC(fastunpend21), IDTVEC(fastunpend22), IDTVEC(fastunpend23),
183 IDTVEC(fastunpend24), IDTVEC(fastunpend25), IDTVEC(fastunpend26),
184 IDTVEC(fastunpend27), IDTVEC(fastunpend28), IDTVEC(fastunpend29),
185 IDTVEC(fastunpend30), IDTVEC(fastunpend31);
186
187 #if defined(SMP) || defined(APIC_IO)
188 inthand_t
189 IDTVEC(fastintr16), IDTVEC(fastintr17),
190 IDTVEC(fastintr18), IDTVEC(fastintr19),
191 IDTVEC(fastintr20), IDTVEC(fastintr21),
192 IDTVEC(fastintr22), IDTVEC(fastintr23),
193 IDTVEC(fastintr24), IDTVEC(fastintr25),
194 IDTVEC(fastintr26), IDTVEC(fastintr27),
195 IDTVEC(fastintr28), IDTVEC(fastintr29),
196 IDTVEC(fastintr30), IDTVEC(fastintr31);
197 inthand_t
198 IDTVEC(intr16), IDTVEC(intr17), IDTVEC(intr18), IDTVEC(intr19),
199 IDTVEC(intr20), IDTVEC(intr21), IDTVEC(intr22), IDTVEC(intr23),
200 IDTVEC(intr24), IDTVEC(intr25), IDTVEC(intr26), IDTVEC(intr27),
201 IDTVEC(intr28), IDTVEC(intr29), IDTVEC(intr30), IDTVEC(intr31);
202
203 inthand_t
204 Xinvltlb, /* TLB shootdowns - global */
205 Xinvlpg, /* TLB shootdowns - 1 page */
206 Xinvlrng, /* TLB shootdowns - page range */
207 Xhardclock, /* Forward hardclock() */
208 Xstatclock, /* Forward statclock() */
209 Xcpuast, /* Additional software trap on other cpu */
210 Xcpustop, /* CPU stops & waits for another CPU to restart it */
211 Xspuriousint, /* handle APIC "spurious INTs" */
212 Xrendezvous, /* handle CPU rendezvous */
213 Xlazypmap; /* handle lazy pmap release */
214
215 #ifdef TEST_TEST1
216 inthand_t
217 Xtest1; /* 'fake' HWI at top of APIC prio 0x3x, 32+31 = 0x3f */
218 #endif /** TEST_TEST1 */
219 #endif /* SMP || APIC_IO */
220
221 #ifdef APIC_IO
222 /*
223 * This is to accommodate "mixed-mode" programming for
224 * motherboards that don't connect the 8254 to the IO APIC.
225 */
226 #define AUTO_EOI_1 1
227 #endif
228
229 #define NR_INTRNAMES (1 + ICU_LEN + 2 * ICU_LEN)
230
231 void isa_defaultirq(void);
232 int isa_nmi(int cd);
233 int icu_setup(int intr, driver_intr_t *func, void *arg, int flags);
234 int icu_unset(int intr, driver_intr_t *handler);
235 void icu_reinit(void);
236
237 /*
238 * WARNING: These are internal functions and not to be used by device drivers!
239 * They are subject to change without notice.
240 */
241 int inthand_add(const char *name, int irq, driver_intr_t handler, void *arg,
242 enum intr_type flags, void **cookiep);
243 int inthand_remove(void *cookie);
244 void sched_ithd(void *dummy);
245 void call_fast_unpend(int irq);
246
247 #endif /* LOCORE */
248
249 #endif /* _KERNEL */
250
251 #endif /* !_I386_ISA_INTR_MACHDEP_H_ */
Cache object: 7266d2c504448b8e9cf644d82f880b8c
|