The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/i386/isa/isa_dma.c

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    1 /*-
    2  * Copyright (c) 1991 The Regents of the University of California.
    3  * All rights reserved.
    4  *
    5  * This code is derived from software contributed to Berkeley by
    6  * William Jolitz.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  * 3. All advertising materials mentioning features or use of this software
   17  *    must display the following acknowledgement:
   18  *      This product includes software developed by the University of
   19  *      California, Berkeley and its contributors.
   20  * 4. Neither the name of the University nor the names of its contributors
   21  *    may be used to endorse or promote products derived from this software
   22  *    without specific prior written permission.
   23  *
   24  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   25  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   26  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   27  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   28  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   29  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   30  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   31  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   32  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   33  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   34  * SUCH DAMAGE.
   35  *
   36  *      from: @(#)isa.c 7.2 (Berkeley) 5/13/91
   37  * $FreeBSD: releng/5.1/sys/i386/isa/isa_dma.c 112569 2003-03-25 00:07:06Z jake $
   38  */
   39 
   40 /*
   41  * code to manage AT bus
   42  *
   43  * 92/08/18  Frank P. MacLachlan (fpm@crash.cts.com):
   44  * Fixed uninitialized variable problem and added code to deal
   45  * with DMA page boundaries in isa_dmarangecheck().  Fixed word
   46  * mode DMA count compution and reorganized DMA setup code in
   47  * isa_dmastart()
   48  */
   49 
   50 #include <sys/param.h>
   51 #include <sys/systm.h>
   52 #include <sys/bus.h>
   53 #include <sys/kernel.h>
   54 #include <sys/malloc.h>
   55 #include <sys/lock.h>
   56 #include <sys/proc.h>
   57 #include <sys/mutex.h>
   58 #include <sys/module.h>
   59 #include <vm/vm.h>
   60 #include <vm/vm_param.h>
   61 #include <vm/pmap.h>
   62 #include <i386/isa/isa.h>
   63 #include <dev/ic/i8237.h>
   64 #include <isa/isavar.h>
   65 
   66 /*
   67 **  Register definitions for DMA controller 1 (channels 0..3):
   68 */
   69 #define DMA1_CHN(c)     (IO_DMA1 + 1*(2*(c)))   /* addr reg for channel c */
   70 #define DMA1_SMSK       (IO_DMA1 + 1*10)        /* single mask register */
   71 #define DMA1_MODE       (IO_DMA1 + 1*11)        /* mode register */
   72 #define DMA1_FFC        (IO_DMA1 + 1*12)        /* clear first/last FF */
   73 
   74 /*
   75 **  Register definitions for DMA controller 2 (channels 4..7):
   76 */
   77 #define DMA2_CHN(c)     (IO_DMA2 + 2*(2*(c)))   /* addr reg for channel c */
   78 #define DMA2_SMSK       (IO_DMA2 + 2*10)        /* single mask register */
   79 #define DMA2_MODE       (IO_DMA2 + 2*11)        /* mode register */
   80 #define DMA2_FFC        (IO_DMA2 + 2*12)        /* clear first/last FF */
   81 
   82 static int isa_dmarangecheck(caddr_t va, u_int length, int chan);
   83 
   84 static caddr_t  dma_bouncebuf[8];
   85 static u_int    dma_bouncebufsize[8];
   86 static u_int8_t dma_bounced = 0;
   87 static u_int8_t dma_busy = 0;           /* Used in isa_dmastart() */
   88 static u_int8_t dma_inuse = 0;          /* User for acquire/release */
   89 static u_int8_t dma_auto_mode = 0;
   90 
   91 #define VALID_DMA_MASK (7)
   92 
   93 /* high byte of address is stored in this port for i-th dma channel */
   94 static int dmapageport[8] = { 0x87, 0x83, 0x81, 0x82, 0x8f, 0x8b, 0x89, 0x8a };
   95 
   96 /*
   97  * Setup a DMA channel's bounce buffer.
   98  */
   99 void
  100 isa_dmainit(chan, bouncebufsize)
  101         int chan;
  102         u_int bouncebufsize;
  103 {
  104         void *buf;
  105 
  106 #ifdef DIAGNOSTIC
  107         if (chan & ~VALID_DMA_MASK)
  108                 panic("isa_dmainit: channel out of range");
  109 
  110         if (dma_bouncebuf[chan] != NULL)
  111                 panic("isa_dmainit: impossible request"); 
  112 #endif
  113 
  114         dma_bouncebufsize[chan] = bouncebufsize;
  115 
  116         /* Try malloc() first.  It works better if it works. */
  117         buf = malloc(bouncebufsize, M_DEVBUF, M_NOWAIT);
  118         if (buf != NULL) {
  119                 if (isa_dmarangecheck(buf, bouncebufsize, chan) == 0) {
  120                         dma_bouncebuf[chan] = buf;
  121                         return;
  122                 }
  123                 free(buf, M_DEVBUF);
  124         }
  125         buf = contigmalloc(bouncebufsize, M_DEVBUF, M_NOWAIT, 0ul, 0xfffffful,
  126                            1ul, chan & 4 ? 0x20000ul : 0x10000ul);
  127         if (buf == NULL)
  128                 printf("isa_dmainit(%d, %d) failed\n", chan, bouncebufsize);
  129         else
  130                 dma_bouncebuf[chan] = buf;
  131 }
  132 
  133 /*
  134  * Register a DMA channel's usage.  Usually called from a device driver
  135  * in open() or during its initialization.
  136  */
  137 int
  138 isa_dma_acquire(chan)
  139         int chan;
  140 {
  141 #ifdef DIAGNOSTIC
  142         if (chan & ~VALID_DMA_MASK)
  143                 panic("isa_dma_acquire: channel out of range");
  144 #endif
  145 
  146         if (dma_inuse & (1 << chan)) {
  147                 printf("isa_dma_acquire: channel %d already in use\n", chan);
  148                 return (EBUSY);
  149         }
  150         dma_inuse |= (1 << chan);
  151         dma_auto_mode &= ~(1 << chan);
  152 
  153         return (0);
  154 }
  155 
  156 /*
  157  * Unregister a DMA channel's usage.  Usually called from a device driver
  158  * during close() or during its shutdown.
  159  */
  160 void
  161 isa_dma_release(chan)
  162         int chan;
  163 {
  164 #ifdef DIAGNOSTIC
  165         if (chan & ~VALID_DMA_MASK)
  166                 panic("isa_dma_release: channel out of range");
  167 
  168         if ((dma_inuse & (1 << chan)) == 0)
  169                 printf("isa_dma_release: channel %d not in use\n", chan);
  170 #endif
  171 
  172         if (dma_busy & (1 << chan)) {
  173                 dma_busy &= ~(1 << chan);
  174                 /* 
  175                  * XXX We should also do "dma_bounced &= (1 << chan);"
  176                  * because we are acting on behalf of isa_dmadone() which
  177                  * was not called to end the last DMA operation.  This does
  178                  * not matter now, but it may in the future.
  179                  */
  180         }
  181 
  182         dma_inuse &= ~(1 << chan);
  183         dma_auto_mode &= ~(1 << chan);
  184 }
  185 
  186 /*
  187  * isa_dmacascade(): program 8237 DMA controller channel to accept
  188  * external dma control by a board.
  189  */
  190 void
  191 isa_dmacascade(chan)
  192         int chan;
  193 {
  194 #ifdef DIAGNOSTIC
  195         if (chan & ~VALID_DMA_MASK)
  196                 panic("isa_dmacascade: channel out of range");
  197 #endif
  198 
  199         /* set dma channel mode, and set dma channel mode */
  200         if ((chan & 4) == 0) {
  201                 outb(DMA1_MODE, DMA37MD_CASCADE | chan);
  202                 outb(DMA1_SMSK, chan);
  203         } else {
  204                 outb(DMA2_MODE, DMA37MD_CASCADE | (chan & 3));
  205                 outb(DMA2_SMSK, chan & 3);
  206         }
  207 }
  208 
  209 /*
  210  * isa_dmastart(): program 8237 DMA controller channel, avoid page alignment
  211  * problems by using a bounce buffer.
  212  */
  213 void
  214 isa_dmastart(int flags, caddr_t addr, u_int nbytes, int chan)
  215 {
  216         vm_paddr_t phys;
  217         int waport;
  218         caddr_t newaddr;
  219 
  220         GIANT_REQUIRED;
  221 
  222 #ifdef DIAGNOSTIC
  223         if (chan & ~VALID_DMA_MASK)
  224                 panic("isa_dmastart: channel out of range");
  225 
  226         if ((chan < 4 && nbytes > (1<<16))
  227             || (chan >= 4 && (nbytes > (1<<17) || (u_int)addr & 1)))
  228                 panic("isa_dmastart: impossible request");
  229 
  230         if ((dma_inuse & (1 << chan)) == 0)
  231                 printf("isa_dmastart: channel %d not acquired\n", chan);
  232 #endif
  233 
  234 #if 0
  235         /*
  236          * XXX This should be checked, but drivers like ad1848 only call
  237          * isa_dmastart() once because they use Auto DMA mode.  If we
  238          * leave this in, drivers that do this will print this continuously.
  239          */
  240         if (dma_busy & (1 << chan))
  241                 printf("isa_dmastart: channel %d busy\n", chan);
  242 #endif
  243 
  244         dma_busy |= (1 << chan);
  245 
  246         if (isa_dmarangecheck(addr, nbytes, chan)) {
  247                 if (dma_bouncebuf[chan] == NULL
  248                     || dma_bouncebufsize[chan] < nbytes)
  249                         panic("isa_dmastart: bad bounce buffer"); 
  250                 dma_bounced |= (1 << chan);
  251                 newaddr = dma_bouncebuf[chan];
  252 
  253                 /* copy bounce buffer on write */
  254                 if (!(flags & ISADMA_READ))
  255                         bcopy(addr, newaddr, nbytes);
  256                 addr = newaddr;
  257         }
  258 
  259         /* translate to physical */
  260         phys = pmap_extract(kernel_pmap, (vm_offset_t)addr);
  261 
  262         if (flags & ISADMA_RAW) {
  263             dma_auto_mode |= (1 << chan);
  264         } else { 
  265             dma_auto_mode &= ~(1 << chan);
  266         }
  267 
  268         if ((chan & 4) == 0) {
  269                 /*
  270                  * Program one of DMA channels 0..3.  These are
  271                  * byte mode channels.
  272                  */
  273                 /* set dma channel mode, and reset address ff */
  274 
  275                 /* If ISADMA_RAW flag is set, then use autoinitialise mode */
  276                 if (flags & ISADMA_RAW) {
  277                   if (flags & ISADMA_READ)
  278                         outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_WRITE|chan);
  279                   else
  280                         outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_READ|chan);
  281                 }
  282                 else
  283                 if (flags & ISADMA_READ)
  284                         outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|chan);
  285                 else
  286                         outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_READ|chan);
  287                 outb(DMA1_FFC, 0);
  288 
  289                 /* send start address */
  290                 waport =  DMA1_CHN(chan);
  291                 outb(waport, phys);
  292                 outb(waport, phys>>8);
  293                 outb(dmapageport[chan], phys>>16);
  294 
  295                 /* send count */
  296                 outb(waport + 1, --nbytes);
  297                 outb(waport + 1, nbytes>>8);
  298 
  299                 /* unmask channel */
  300                 outb(DMA1_SMSK, chan);
  301         } else {
  302                 /*
  303                  * Program one of DMA channels 4..7.  These are
  304                  * word mode channels.
  305                  */
  306                 /* set dma channel mode, and reset address ff */
  307 
  308                 /* If ISADMA_RAW flag is set, then use autoinitialise mode */
  309                 if (flags & ISADMA_RAW) {
  310                   if (flags & ISADMA_READ)
  311                         outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_WRITE|(chan&3));
  312                   else
  313                         outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_READ|(chan&3));
  314                 }
  315                 else
  316                 if (flags & ISADMA_READ)
  317                         outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|(chan&3));
  318                 else
  319                         outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_READ|(chan&3));
  320                 outb(DMA2_FFC, 0);
  321 
  322                 /* send start address */
  323                 waport = DMA2_CHN(chan - 4);
  324                 outb(waport, phys>>1);
  325                 outb(waport, phys>>9);
  326                 outb(dmapageport[chan], phys>>16);
  327 
  328                 /* send count */
  329                 nbytes >>= 1;
  330                 outb(waport + 2, --nbytes);
  331                 outb(waport + 2, nbytes>>8);
  332 
  333                 /* unmask channel */
  334                 outb(DMA2_SMSK, chan & 3);
  335         }
  336 }
  337 
  338 void
  339 isa_dmadone(int flags, caddr_t addr, int nbytes, int chan)
  340 {  
  341 #ifdef DIAGNOSTIC
  342         if (chan & ~VALID_DMA_MASK)
  343                 panic("isa_dmadone: channel out of range");
  344 
  345         if ((dma_inuse & (1 << chan)) == 0)
  346                 printf("isa_dmadone: channel %d not acquired\n", chan);
  347 #endif
  348 
  349         if (((dma_busy & (1 << chan)) == 0) && 
  350             (dma_auto_mode & (1 << chan)) == 0 )
  351                 printf("isa_dmadone: channel %d not busy\n", chan);
  352 
  353         if ((dma_auto_mode & (1 << chan)) == 0)
  354                 outb(chan & 4 ? DMA2_SMSK : DMA1_SMSK, (chan & 3) | 4);
  355 
  356         if (dma_bounced & (1 << chan)) {
  357                 /* copy bounce buffer on read */
  358                 if (flags & ISADMA_READ)
  359                         bcopy(dma_bouncebuf[chan], addr, nbytes);
  360 
  361                 dma_bounced &= ~(1 << chan);
  362         }
  363         dma_busy &= ~(1 << chan);
  364 }
  365 
  366 /*
  367  * Check for problems with the address range of a DMA transfer
  368  * (non-contiguous physical pages, outside of bus address space,
  369  * crossing DMA page boundaries).
  370  * Return true if special handling needed.
  371  */
  372 
  373 static int
  374 isa_dmarangecheck(caddr_t va, u_int length, int chan)
  375 {
  376         vm_paddr_t phys, priorpage = 0;
  377         vm_offset_t endva;
  378         u_int dma_pgmsk = (chan & 4) ?  ~(128*1024-1) : ~(64*1024-1);
  379 
  380         GIANT_REQUIRED;
  381 
  382         endva = (vm_offset_t)round_page((vm_offset_t)va + length);
  383         for (; va < (caddr_t) endva ; va += PAGE_SIZE) {
  384                 phys = trunc_page(pmap_extract(kernel_pmap, (vm_offset_t)va));
  385 #define ISARAM_END      RAM_END
  386                 if (phys == 0)
  387                         panic("isa_dmacheck: no physical page present");
  388                 if (phys >= ISARAM_END)
  389                         return (1);
  390                 if (priorpage) {
  391                         if (priorpage + PAGE_SIZE != phys)
  392                                 return (1);
  393                         /* check if crossing a DMA page boundary */
  394                         if (((u_int)priorpage ^ (u_int)phys) & dma_pgmsk)
  395                                 return (1);
  396                 }
  397                 priorpage = phys;
  398         }
  399         return (0);
  400 }
  401 
  402 /*
  403  * Query the progress of a transfer on a DMA channel.
  404  *
  405  * To avoid having to interrupt a transfer in progress, we sample
  406  * each of the high and low databytes twice, and apply the following
  407  * logic to determine the correct count.
  408  *
  409  * Reads are performed with interrupts disabled, thus it is to be
  410  * expected that the time between reads is very small.  At most
  411  * one rollover in the low count byte can be expected within the
  412  * four reads that are performed.
  413  *
  414  * There are three gaps in which a rollover can occur :
  415  *
  416  * - read low1
  417  *              gap1
  418  * - read high1
  419  *              gap2
  420  * - read low2
  421  *              gap3
  422  * - read high2
  423  *
  424  * If a rollover occurs in gap1 or gap2, the low2 value will be
  425  * greater than the low1 value.  In this case, low2 and high2 are a
  426  * corresponding pair. 
  427  *
  428  * In any other case, low1 and high1 can be considered to be correct.
  429  *
  430  * The function returns the number of bytes remaining in the transfer,
  431  * or -1 if the channel requested is not active.
  432  *
  433  */
  434 int
  435 isa_dmastatus(int chan)
  436 {
  437         u_long  cnt = 0;
  438         int     ffport, waport;
  439         u_long  low1, high1, low2, high2;
  440 
  441         /* channel active? */
  442         if ((dma_inuse & (1 << chan)) == 0) {
  443                 printf("isa_dmastatus: channel %d not active\n", chan);
  444                 return(-1);
  445         }
  446         /* channel busy? */
  447 
  448         if (((dma_busy & (1 << chan)) == 0) &&
  449             (dma_auto_mode & (1 << chan)) == 0 ) {
  450             printf("chan %d not busy\n", chan);
  451             return -2 ;
  452         }       
  453         if (chan < 4) {                 /* low DMA controller */
  454                 ffport = DMA1_FFC;
  455                 waport = DMA1_CHN(chan) + 1;
  456         } else {                        /* high DMA controller */
  457                 ffport = DMA2_FFC;
  458                 waport = DMA2_CHN(chan - 4) + 2;
  459         }
  460 
  461         disable_intr();                 /* no interrupts Mr Jones! */
  462         outb(ffport, 0);                /* clear register LSB flipflop */
  463         low1 = inb(waport);
  464         high1 = inb(waport);
  465         outb(ffport, 0);                /* clear again */
  466         low2 = inb(waport);
  467         high2 = inb(waport);
  468         enable_intr();                  /* enable interrupts again */
  469 
  470         /* 
  471          * Now decide if a wrap has tried to skew our results.
  472          * Note that after TC, the count will read 0xffff, while we want 
  473          * to return zero, so we add and then mask to compensate.
  474          */
  475         if (low1 >= low2) {
  476                 cnt = (low1 + (high1 << 8) + 1) & 0xffff;
  477         } else {
  478                 cnt = (low2 + (high2 << 8) + 1) & 0xffff;
  479         }
  480 
  481         if (chan >= 4)                  /* high channels move words */
  482                 cnt *= 2;
  483         return(cnt);
  484 }
  485 
  486 /*
  487  * Stop a DMA transfer currently in progress.
  488  */
  489 int
  490 isa_dmastop(int chan) 
  491 {
  492         if ((dma_inuse & (1 << chan)) == 0)
  493                 printf("isa_dmastop: channel %d not acquired\n", chan);  
  494 
  495         if (((dma_busy & (1 << chan)) == 0) &&
  496             ((dma_auto_mode & (1 << chan)) == 0)) {
  497                 printf("chan %d not busy\n", chan);
  498                 return -2 ;
  499         }
  500     
  501         if ((chan & 4) == 0) {
  502                 outb(DMA1_SMSK, (chan & 3) | 4 /* disable mask */);
  503         } else {
  504                 outb(DMA2_SMSK, (chan & 3) | 4 /* disable mask */);
  505         }
  506         return(isa_dmastatus(chan));
  507 }
  508 
  509 /*
  510  * Attach to the ISA PnP descriptor for the AT DMA controller
  511  */
  512 static struct isa_pnp_id atdma_ids[] = {
  513         { 0x0002d041 /* PNP0200 */, "AT DMA controller" },
  514         { 0 }
  515 };
  516 
  517 static int
  518 atdma_probe(device_t dev)
  519 {
  520         int result;
  521         
  522         if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, atdma_ids)) <= 0)
  523                 device_quiet(dev);
  524         return(result);
  525 }
  526 
  527 static int
  528 atdma_attach(device_t dev)
  529 {
  530         return(0);
  531 }
  532 
  533 static device_method_t atdma_methods[] = {
  534         /* Device interface */
  535         DEVMETHOD(device_probe,         atdma_probe),
  536         DEVMETHOD(device_attach,        atdma_attach),
  537         DEVMETHOD(device_detach,        bus_generic_detach),
  538         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
  539         DEVMETHOD(device_suspend,       bus_generic_suspend),
  540         DEVMETHOD(device_resume,        bus_generic_resume),
  541         { 0, 0 }
  542 };
  543 
  544 static driver_t atdma_driver = {
  545         "atdma",
  546         atdma_methods,
  547         1,              /* no softc */
  548 };
  549 
  550 static devclass_t atdma_devclass;
  551 
  552 DRIVER_MODULE(atdma, isa, atdma_driver, atdma_devclass, 0, 0);
  553 DRIVER_MODULE(atdma, acpi, atdma_driver, atdma_devclass, 0, 0);

Cache object: 0c20243dd6c7420e506b34f53c3d023a


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