Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/i386/isa/loran.c
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1 /* 2 * ---------------------------------------------------------------------------- 3 * "THE BEER-WARE LICENSE" (Revision 42): 4 * <phk@FreeBSD.org> wrote this file. As long as you retain this notice you 5 * can do whatever you want with this stuff. If we meet some day, and you think 6 * this stuff is worth it, you can buy me a beer in return. Poul-Henning Kamp 7 * ---------------------------------------------------------------------------- 8 * 9 * $FreeBSD: releng/5.1/sys/i386/isa/loran.c 112037 2003-03-09 11:03:45Z phk $ 10 * 11 * This device-driver helps the userland controlprogram for a LORAN-C 12 * receiver avoid monopolizing the CPU. 13 * 14 * This is clearly a candidate for the "most weird hardware support in 15 * FreeBSD" prize. At this time only two copies of the receiver are 16 * known to exist in the entire world. 17 * 18 * Details can be found at: 19 * ftp://ftp.eecis.udel.edu/pub/ntp/loran.tar.Z 20 * 21 */ 22 23 #ifdef _KERNEL 24 #include <sys/param.h> 25 #include <sys/systm.h> 26 #include <sys/sysctl.h> 27 #include <sys/conf.h> 28 #include <sys/kernel.h> 29 #include <sys/uio.h> 30 #include <sys/bus.h> 31 #include <sys/malloc.h> 32 #include <sys/timetc.h> 33 34 #include <i386/isa/isa_device.h> 35 #endif /* _KERNEL */ 36 37 typedef TAILQ_HEAD(, datapoint) dphead_t; 38 39 struct datapoint { 40 /* Fields used by kernel */ 41 u_int64_t scheduled; 42 u_int code; 43 u_int fri; 44 u_int agc; 45 u_int phase; 46 u_int width; 47 u_int par; 48 u_int isig; 49 u_int qsig; 50 u_int ssig; 51 u_int64_t epoch; 52 TAILQ_ENTRY(datapoint) list; 53 int vco; 54 int bounce; 55 pid_t pid; 56 struct timespec when; 57 58 int priority; 59 dphead_t *home; 60 61 /* Fields used only in userland */ 62 void (*proc)(struct datapoint *); 63 void *ident; 64 int index; 65 char *name; 66 67 68 /* Fields used only in userland */ 69 double ival; 70 double qval; 71 double sval; 72 double mval; 73 74 }; 75 76 /* 77 * Mode register (PAR) hardware definitions 78 */ 79 #define INTEG 0x03 /* integrator mask */ 80 #define INTEG_1000us 0 81 #define INTEG_264us 1 82 #define INTEG_36us 2 83 #define INTEG_SHORT 3 84 #define GATE 0x0C /* gate source mask */ 85 #define GATE_OPEN 0x0 86 #define GATE_GRI 0x4 87 #define GATE_PCI 0x8 88 #define GATE_STB 0xc 89 #define MSB 0x10 /* load dac high-order bits */ 90 #define IEN 0x20 /* enable interrupt bit */ 91 #define EN5 0x40 /* enable counter 5 bit */ 92 #define ENG 0x80 /* enable gri bit */ 93 94 #define VCO_SHIFT 8 /* bits of fraction on VCO value */ 95 #define VCO (2048 << VCO_SHIFT) /* initial vco dac (0 V)*/ 96 97 98 #define PGUARD 990 /* program guard time (cycle) (990!) */ 99 100 #ifdef _KERNEL 101 102 #define NLORAN 10 /* Allow ten minor devices */ 103 104 #define NDUMMY 4 /* How many idlers we want */ 105 106 #define PORT 0x0300 /* controller port address */ 107 108 109 #define GRI 800 /* pulse-group gate (cycle) */ 110 111 /* 112 * Analog/digital converter (ADC) hardware definitions 113 */ 114 #define ADC PORT+2 /* adc buffer (r)/address (w) */ 115 #define ADCGO PORT+3 /* adc status (r)/adc start (w) */ 116 #define ADC_START 0x01 /* converter start bit (w) */ 117 #define ADC_BUSY 0x01 /* converter busy bit (r) */ 118 #define ADC_DONE 0x80 /* converter done bit (r) */ 119 #define ADC_I 0 /* i channel (phase) */ 120 #define ADC_Q 1 /* q channel (amplitude) */ 121 #define ADC_S 2 /* s channel (agc) */ 122 123 /* 124 * Digital/analog converter (DAC) hardware definitions 125 * Note: output voltage increases with value programmed; the buffer 126 * is loaded in two 8-bit bytes, the lsb 8 bits with the MSB bit off in 127 * the PAR register, the msb 4 bits with the MSB on. 128 */ 129 #define DACA PORT+4 /* vco (dac a) buffer (w) */ 130 #define DACB PORT+5 /* agc (dac b) buffer (w) */ 131 132 #define LOAD_DAC(dac, val) if (0) { } else { \ 133 par &= ~MSB; outb(PAR, par); outb((dac), (val) & 0xff); \ 134 par |= MSB; outb(PAR, par); outb((dac), ((val) >> 8) & 0xff); \ 135 } 136 137 /* 138 * Pulse-code generator (CODE) hardware definitions 139 * Note: bits are shifted out from the lsb first 140 */ 141 #define CODE PORT+6 /* pulse-code buffer (w) */ 142 #define MPCA 0xCA /* LORAN-C master pulse code group a */ 143 #define MPCB 0x9F /* LORAN-C master pulse code group b */ 144 #define SPCA 0xF9 /* LORAN-C slave pulse code group a */ 145 #define SPCB 0xAC /* LORAN-C slave pulse code group b */ 146 147 /* 148 * Mode register (PAR) hardware definitions 149 */ 150 #define PAR PORT+7 /* parameter buffer (w) */ 151 152 #define TGC PORT+0 /* stc control port (r/w) */ 153 #define TGD PORT+1 /* stc data port (r/w) */ 154 155 /* 156 * Timing generator (STC) hardware commands 157 */ 158 /* argument sssss = counter numbers 5-1 */ 159 #define TG_LOADDP 0x00 /* load data pointer */ 160 /* argument ee = element (all groups except ggg = 000 or 111) */ 161 #define MODEREG 0x00 /* mode register */ 162 #define LOADREG 0x08 /* load register */ 163 #define HOLDREG 0x10 /* hold register */ 164 #define HOLDINC 0x18 /* hold register (hold cycle increm) */ 165 /* argument ee = element (group ggg = 111) */ 166 #define ALARM1 0x07 /* alarm register 1 */ 167 #define ALARM2 0x0F /* alarm register 2 */ 168 #define MASTER 0x17 /* master mode register */ 169 #define STATUS 0x1F /* status register */ 170 #define ARM 0x20 /* arm counters */ 171 #define LOAD 0x40 /* load counters */ 172 #define TG_LOADARM 0x60 /* load and arm counters */ 173 #define DISSAVE 0x80 /* disarm and save counters */ 174 #define TG_SAVE 0xA0 /* save counters */ 175 #define DISARM 0xC0 /* disarm counters */ 176 /* argument nnn = counter number */ 177 #define SETTOG 0xE8 /* set toggle output HIGH for counter */ 178 #define CLRTOG 0xE0 /* set toggle output LOW for counter */ 179 #define STEP 0xF0 /* step counter */ 180 /* argument eeggg, where ee = element, ggg - counter group */ 181 /* no arguments */ 182 #define ENABDPS 0xE0 /* enable data pointer sequencing */ 183 #define ENABFOUT 0xE6 /* enable fout */ 184 #define ENAB8 0xE7 /* enable 8-bit data bus */ 185 #define DSABDPS 0xE8 /* disable data pointer sequencing */ 186 #define ENAB16 0xEF /* enable 16-bit data bus */ 187 #define DSABFOUT 0xEE /* disable fout */ 188 #define ENABPFW 0xF8 /* enable prefetch for write */ 189 #define DSABPFW 0xF9 /* disable prefetch for write */ 190 #define TG_RESET 0xFF /* master reset */ 191 192 #define LOAD_9513(index, val) if (0) {} else { \ 193 outb(TGC, TG_LOADDP + (index)); \ 194 outb(TGD, (val) & 0xff); \ 195 outb(TGD, ((val) >> 8) & 0xff); \ 196 } 197 198 #define NENV 40 /* size of envelope filter */ 199 #define CLOCK 50 /* clock period (clock) */ 200 #define CYCLE 10 /* carrier period (us) */ 201 #define PCX (NENV * CLOCK) /* envelope gate (clock) */ 202 #define STROBE 50 /* strobe gate (clock) */ 203 204 /**********************************************************************/ 205 206 extern struct cdevsw loran_cdevsw; 207 208 static dphead_t minors[NLORAN + 1], working; 209 210 static struct datapoint dummy[NDUMMY], *first, *second; 211 212 static u_int64_t ticker; 213 214 static u_char par; 215 216 static MALLOC_DEFINE(M_LORAN, "Loran", "Loran datapoints"); 217 218 static int loranerror; 219 static char lorantext[160]; 220 221 static u_int vco_is; 222 static u_int vco_should; 223 static u_int vco_want; 224 static u_int64_t vco_when; 225 static int64_t vco_error; 226 227 /**********************************************************************/ 228 229 static int loranprobe (struct isa_device *dvp); 230 static void init_tgc (void); 231 static int loranattach (struct isa_device *isdp); 232 static void loranenqueue (struct datapoint *); 233 static d_open_t loranopen; 234 static d_close_t loranclose; 235 static d_read_t loranread; 236 static d_write_t loranwrite; 237 static ointhand2_t loranintr; 238 extern struct timecounter loran_timecounter; 239 240 /**********************************************************************/ 241 242 static int 243 loranprobe(struct isa_device *dvp) 244 { 245 246 dvp->id_iobase = PORT; 247 return (8); 248 } 249 250 static u_short tg_init[] = { /* stc initialization vector */ 251 0x0562, 12, 13, /* counter 1 (p0) Mode J */ 252 0x0262, PGUARD, GRI, /* counter 2 (gri) Mode J */ 253 0x8562, PCX, 5000 - PCX, /* counter 3 (pcx) */ 254 0xc562, 0, STROBE, /* counter 4 (stb) Mode L */ 255 0x052a, 0, 0 /* counter 5 (out) */ 256 }; 257 258 static void 259 init_tgc(void) 260 { 261 int i; 262 263 /* Initialize the 9513A */ 264 outb(TGC, TG_RESET); outb(TGC, LOAD+0x1f); /* reset STC chip */ 265 LOAD_9513(MASTER, 0x8af0); 266 outb(TGC, TG_LOADDP+1); 267 tg_init[4] = 7499 - GRI; 268 for (i = 0; i < 5*3; i++) { 269 outb(TGD, tg_init[i]); 270 outb(TGD, tg_init[i] >> 8); 271 } 272 outb(TGC, TG_LOADARM+0x1f); /* let the good times roll */ 273 } 274 275 static int 276 loranattach(struct isa_device *isdp) 277 { 278 int i; 279 280 isdp->id_ointr = loranintr; 281 282 /* We need to be a "fast-intr" */ 283 /* isdp->id_ri_flags |= RI_FAST; XXX unimplemented - use newbus! */ 284 285 printf("loran0: LORAN-C Receiver\n"); 286 287 vco_want = vco_should = VCO; 288 vco_is = vco_should >> VCO_SHIFT; 289 LOAD_DAC(DACA, vco_is); 290 291 init_tgc(); 292 293 tc_init(&loran_timecounter); 294 295 TAILQ_INIT(&working); 296 for (i = 0; i < NLORAN + 1; i++) { 297 TAILQ_INIT(&minors[i]); 298 make_dev(&loran_cdevsw, i, UID_ROOT, GID_WHEEL, 0600, "loran%d", i); 299 } 300 301 for (i = 0; i < NDUMMY; i++) { 302 dummy[i].agc = 4095; 303 dummy[i].code = 0xac; 304 dummy[i].fri = PGUARD; 305 dummy[i].scheduled = PGUARD * 2 * i; 306 dummy[i].phase = 50; 307 dummy[i].width = 50; 308 dummy[i].priority = NLORAN * 256; 309 dummy[i].home = &minors[NLORAN]; 310 if (i == 0) 311 first = &dummy[i]; 312 else if (i == 1) 313 second = &dummy[i]; 314 else 315 TAILQ_INSERT_TAIL(&working, &dummy[i], list); 316 } 317 318 inb(ADC); /* Flush any old result */ 319 outb(ADC, ADC_S); 320 321 par = ENG|IEN; 322 outb(PAR, par); 323 324 return (1); 325 } 326 327 static int 328 loranopen (dev_t dev, int flags, int fmt, struct thread *td) 329 { 330 int idx; 331 332 idx = minor(dev); 333 if (idx >= NLORAN) 334 return (ENODEV); 335 336 return(0); 337 } 338 339 static int 340 loranclose(dev_t dev, int flags, int fmt, struct thread *td) 341 { 342 return(0); 343 } 344 345 static int 346 loranread(dev_t dev, struct uio * uio, int ioflag) 347 { 348 u_long ef; 349 struct datapoint *this; 350 int err, c; 351 int idx; 352 353 idx = minor(dev); 354 355 if (loranerror) { 356 printf("Loran0: %s", lorantext); 357 loranerror = 0; 358 return(EIO); 359 } 360 if (TAILQ_EMPTY(&minors[idx])) 361 tsleep (&minors[idx], (PZERO + 8) |PCATCH, "loranrd", hz*2); 362 if (TAILQ_EMPTY(&minors[idx])) 363 return(0); 364 this = TAILQ_FIRST(&minors[idx]); 365 ef = read_eflags(); 366 disable_intr(); 367 TAILQ_REMOVE(&minors[idx], this, list); 368 write_eflags(ef); 369 370 c = imin(uio->uio_resid, (int)sizeof *this); 371 err = uiomove((caddr_t)this, c, uio); 372 FREE(this, M_LORAN); 373 return(err); 374 } 375 376 static void 377 loranenqueue(struct datapoint *dp) 378 { 379 struct datapoint *dpp; 380 381 TAILQ_FOREACH(dpp, &working, list) { 382 if (dpp->priority <= dp->priority) 383 continue; 384 TAILQ_INSERT_BEFORE(dpp, dp, list); 385 return; 386 } 387 TAILQ_INSERT_TAIL(&working, dp, list); 388 } 389 390 static int 391 loranwrite(dev_t dev, struct uio * uio, int ioflag) 392 { 393 u_long ef; 394 int err = 0, c; 395 struct datapoint *this; 396 int idx; 397 u_int64_t dt; 398 u_int64_t when; 399 400 idx = minor(dev); 401 402 MALLOC(this, struct datapoint *, sizeof *this, M_LORAN, M_WAITOK); 403 c = imin(uio->uio_resid, (int)sizeof *this); 404 err = uiomove((caddr_t)this, c, uio); 405 if (err) { 406 FREE(this, M_LORAN); 407 return (err); 408 } 409 if (this->fri == 0) { 410 FREE(this, M_LORAN); 411 return (EINVAL); 412 } 413 this->par &= INTEG|GATE; 414 /* XXX more checks needed! */ 415 this->home = &minors[idx]; 416 this->priority &= 0xff; 417 this->priority += idx * 256; 418 this->bounce = 0; 419 when = second->scheduled + PGUARD; 420 if (when > this->scheduled) { 421 dt = when - this->scheduled; 422 dt -= dt % this->fri; 423 this->scheduled += dt; 424 } 425 ef = read_eflags(); 426 disable_intr(); 427 loranenqueue(this); 428 write_eflags(ef); 429 if (this->vco >= 0) 430 vco_want = this->vco; 431 return(err); 432 } 433 434 static void 435 loranintr(int unit) 436 { 437 u_long ef; 438 int status = 0, i; 439 #if 0 440 int count = 0; 441 #endif 442 int delay; 443 u_int64_t when; 444 struct timespec there, then; 445 struct datapoint *dp, *done; 446 447 ef = read_eflags(); 448 disable_intr(); 449 450 /* 451 * Pick up the measurement which just completed, and setup 452 * the next measurement. We have 1100 microseconds for this 453 * of which some eaten by the A/D of the S channel and the 454 * interrupt to get us here. 455 */ 456 457 done = first; 458 459 nanotime(&there); 460 done->ssig = inb(ADC); 461 462 par &= ~(ENG | IEN); 463 outb(PAR, par); 464 465 outb(ADC, ADC_I); 466 outb(ADCGO, ADC_START); 467 468 /* Interlude: while we wait: setup the next measurement */ 469 LOAD_DAC(DACB, second->agc); 470 outb(CODE, second->code); 471 par &= ~(INTEG|GATE); 472 par |= second->par; 473 par |= ENG | IEN; 474 475 while (!(inb(ADCGO) & ADC_DONE)) 476 continue; 477 done->isig = inb(ADC); 478 479 outb(ADC, ADC_Q); 480 outb(ADCGO, ADC_START); 481 /* Interlude: while we wait: setup the next measurement */ 482 /* 483 * We need to load this from the opposite register due to some 484 * weirdness which you can read about in in the 9513 manual on 485 * page 1-26 under "LOAD" 486 */ 487 LOAD_9513(0x0c, second->phase); 488 LOAD_9513(0x14, second->phase); 489 outb(TGC, TG_LOADARM + 0x08); 490 LOAD_9513(0x14, second->width); 491 while (!(inb(ADCGO) & ADC_DONE)) 492 continue; 493 done->qsig = inb(ADC); 494 495 outb(ADC, ADC_S); 496 497 outb(PAR, par); 498 499 /* 500 * End of VERY time critical stuff, we have 8 msec to find 501 * the next measurement and program the delay. 502 */ 503 status = inb(TGC); 504 nanotime(&then); 505 506 first = second; 507 second = 0; 508 when = first->scheduled + PGUARD; 509 TAILQ_FOREACH(dp, &working, list) { 510 while (dp->scheduled < when) 511 dp->scheduled += dp->fri; 512 if (second && dp->scheduled + PGUARD >= second->scheduled) 513 continue; 514 second = dp; 515 } 516 517 delay = (second->scheduled - first->scheduled) - GRI; 518 519 LOAD_9513(0x0a, delay); 520 521 /* Done, the rest is leisure work */ 522 523 vco_error += ((vco_is << VCO_SHIFT) - vco_should) * 524 (ticker - vco_when); 525 vco_should = vco_want; 526 i = vco_should >> VCO_SHIFT; 527 if (vco_error < 0) 528 i++; 529 530 if (vco_is != i) { 531 LOAD_DAC(DACA, i); 532 vco_is = i; 533 } 534 vco_when = ticker; 535 536 /* Check if we overran */ 537 status &= 0x0c; 538 #if 0 539 540 if (status) { 541 outb(TGC, TG_SAVE + 2); /* save counter #2 */ 542 outb(TGC, TG_LOADDP + 0x12); /* hold counter #2 */ 543 count = inb(TGD); 544 count |= inb(TGD) << 8; 545 LOAD_9513(0x12, GRI) 546 } 547 #endif 548 549 if (status) { 550 printf( "Missed: %02x %d first:%p second:%p %.09ld\n", 551 status, delay, first, second, 552 then.tv_nsec - there.tv_nsec); 553 first->bounce++; 554 } 555 556 TAILQ_REMOVE(&working, second, list); 557 558 if (done->bounce) { 559 done->bounce = 0; 560 loranenqueue(done); 561 } else { 562 done->epoch = ticker; 563 done->vco = vco_is; 564 done->when = there; 565 TAILQ_INSERT_TAIL(done->home, done, list); 566 wakeup(done->home); 567 } 568 569 ticker = first->scheduled; 570 571 while ((dp = TAILQ_FIRST(&minors[NLORAN])) != NULL) { 572 TAILQ_REMOVE(&minors[NLORAN], dp, list); 573 TAILQ_INSERT_TAIL(&working, dp, list); 574 } 575 576 when = second->scheduled + PGUARD; 577 578 TAILQ_FOREACH(dp, &working, list) { 579 while (dp->scheduled < when) 580 dp->scheduled += dp->fri; 581 } 582 write_eflags(ef); 583 } 584 585 /**********************************************************************/ 586 587 static unsigned 588 loran_get_timecount(struct timecounter *tc) 589 { 590 unsigned count; 591 u_long ef; 592 593 ef = read_eflags(); 594 disable_intr(); 595 596 outb(TGC, TG_SAVE + 0x10); /* save counter #5 */ 597 outb(TGC, TG_LOADDP +0x15); /* hold counter #5 */ 598 count = inb(TGD); 599 count |= inb(TGD) << 8; 600 601 write_eflags(ef); 602 return (count); 603 } 604 605 static struct timecounter loran_timecounter = { 606 loran_get_timecount, /* get_timecount */ 607 0, /* no pps_poll */ 608 0xffff, /* counter_mask */ 609 5000000, /* frequency */ 610 "loran" /* name */ 611 }; 612 613 614 /**********************************************************************/ 615 616 struct isa_driver lorandriver = { 617 INTR_TYPE_TTY | INTR_FAST, 618 loranprobe, 619 loranattach, 620 "loran" 621 }; 622 COMPAT_ISA_DRIVER(loran, lorandriver); 623 624 static struct cdevsw loran_cdevsw = { 625 .d_open = loranopen, 626 .d_close = loranclose, 627 .d_read = loranread, 628 .d_write = loranwrite, 629 .d_name = "loran", 630 }; 631 632 #endif /* _KERNEL */
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