FreeBSD/Linux Kernel Cross Reference
sys/i386/isa/npx.c
1 /*-
2 * Copyright (c) 1990 William Jolitz.
3 * Copyright (c) 1991 The Regents of the University of California.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 4. Neither the name of the University nor the names of its contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91
31 */
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD: releng/11.0/sys/i386/isa/npx.c 294313 2016-01-19 08:09:09Z kib $");
35
36 #include "opt_cpu.h"
37 #include "opt_isa.h"
38 #include "opt_npx.h"
39
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #include <sys/bus.h>
43 #include <sys/kernel.h>
44 #include <sys/lock.h>
45 #include <sys/malloc.h>
46 #include <sys/module.h>
47 #include <sys/mutex.h>
48 #include <sys/mutex.h>
49 #include <sys/proc.h>
50 #include <sys/smp.h>
51 #include <sys/sysctl.h>
52 #include <machine/bus.h>
53 #include <sys/rman.h>
54 #ifdef NPX_DEBUG
55 #include <sys/syslog.h>
56 #endif
57 #include <sys/signalvar.h>
58 #include <vm/uma.h>
59
60 #include <machine/asmacros.h>
61 #include <machine/cputypes.h>
62 #include <machine/frame.h>
63 #include <machine/md_var.h>
64 #include <machine/pcb.h>
65 #include <machine/psl.h>
66 #include <machine/resource.h>
67 #include <machine/specialreg.h>
68 #include <machine/segments.h>
69 #include <machine/ucontext.h>
70
71 #include <machine/intr_machdep.h>
72
73 #ifdef DEV_ISA
74 #include <isa/isavar.h>
75 #endif
76
77 #if !defined(CPU_DISABLE_SSE) && defined(I686_CPU)
78 #define CPU_ENABLE_SSE
79 #endif
80
81 /*
82 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver.
83 */
84
85 #if defined(__GNUCLIKE_ASM) && !defined(lint)
86
87 #define fldcw(cw) __asm __volatile("fldcw %0" : : "m" (cw))
88 #define fnclex() __asm __volatile("fnclex")
89 #define fninit() __asm __volatile("fninit")
90 #define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr)))
91 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr)))
92 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=am" (*(addr)))
93 #define fp_divide_by_0() __asm __volatile( \
94 "fldz; fld1; fdiv %st,%st(1); fnop")
95 #define frstor(addr) __asm __volatile("frstor %0" : : "m" (*(addr)))
96 #ifdef CPU_ENABLE_SSE
97 #define fxrstor(addr) __asm __volatile("fxrstor %0" : : "m" (*(addr)))
98 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr)))
99 #define ldmxcsr(csr) __asm __volatile("ldmxcsr %0" : : "m" (csr))
100 #define stmxcsr(addr) __asm __volatile("stmxcsr %0" : : "m" (*(addr)))
101
102 static __inline void
103 xrstor(char *addr, uint64_t mask)
104 {
105 uint32_t low, hi;
106
107 low = mask;
108 hi = mask >> 32;
109 __asm __volatile("xrstor %0" : : "m" (*addr), "a" (low), "d" (hi));
110 }
111
112 static __inline void
113 xsave(char *addr, uint64_t mask)
114 {
115 uint32_t low, hi;
116
117 low = mask;
118 hi = mask >> 32;
119 __asm __volatile("xsave %0" : "=m" (*addr) : "a" (low), "d" (hi) :
120 "memory");
121 }
122
123 static __inline void
124 xsaveopt(char *addr, uint64_t mask)
125 {
126 uint32_t low, hi;
127
128 low = mask;
129 hi = mask >> 32;
130 __asm __volatile("xsaveopt %0" : "=m" (*addr) : "a" (low), "d" (hi) :
131 "memory");
132 }
133 #endif
134 #else /* !(__GNUCLIKE_ASM && !lint) */
135
136 void fldcw(u_short cw);
137 void fnclex(void);
138 void fninit(void);
139 void fnsave(caddr_t addr);
140 void fnstcw(caddr_t addr);
141 void fnstsw(caddr_t addr);
142 void fp_divide_by_0(void);
143 void frstor(caddr_t addr);
144 #ifdef CPU_ENABLE_SSE
145 void fxsave(caddr_t addr);
146 void fxrstor(caddr_t addr);
147 void ldmxcsr(u_int csr);
148 void stmxcsr(u_int *csr);
149 void xrstor(char *addr, uint64_t mask);
150 void xsave(char *addr, uint64_t mask);
151 void xsaveopt(char *addr, uint64_t mask);
152 #endif
153
154 #endif /* __GNUCLIKE_ASM && !lint */
155
156 #define start_emulating() load_cr0(rcr0() | CR0_TS)
157 #define stop_emulating() clts()
158
159 #ifdef CPU_ENABLE_SSE
160 #define GET_FPU_CW(thread) \
161 (cpu_fxsr ? \
162 (thread)->td_pcb->pcb_save->sv_xmm.sv_env.en_cw : \
163 (thread)->td_pcb->pcb_save->sv_87.sv_env.en_cw)
164 #define GET_FPU_SW(thread) \
165 (cpu_fxsr ? \
166 (thread)->td_pcb->pcb_save->sv_xmm.sv_env.en_sw : \
167 (thread)->td_pcb->pcb_save->sv_87.sv_env.en_sw)
168 #define SET_FPU_CW(savefpu, value) do { \
169 if (cpu_fxsr) \
170 (savefpu)->sv_xmm.sv_env.en_cw = (value); \
171 else \
172 (savefpu)->sv_87.sv_env.en_cw = (value); \
173 } while (0)
174 #else /* CPU_ENABLE_SSE */
175 #define GET_FPU_CW(thread) \
176 (thread->td_pcb->pcb_save->sv_87.sv_env.en_cw)
177 #define GET_FPU_SW(thread) \
178 (thread->td_pcb->pcb_save->sv_87.sv_env.en_sw)
179 #define SET_FPU_CW(savefpu, value) \
180 (savefpu)->sv_87.sv_env.en_cw = (value)
181 #endif /* CPU_ENABLE_SSE */
182
183 #ifdef CPU_ENABLE_SSE
184 CTASSERT(sizeof(union savefpu) == 512);
185 CTASSERT(sizeof(struct xstate_hdr) == 64);
186 CTASSERT(sizeof(struct savefpu_ymm) == 832);
187
188 /*
189 * This requirement is to make it easier for asm code to calculate
190 * offset of the fpu save area from the pcb address. FPU save area
191 * must be 64-byte aligned.
192 */
193 CTASSERT(sizeof(struct pcb) % XSAVE_AREA_ALIGN == 0);
194
195 /*
196 * Ensure the copy of XCR0 saved in a core is contained in the padding
197 * area.
198 */
199 CTASSERT(X86_XSTATE_XCR0_OFFSET >= offsetof(struct savexmm, sv_pad) &&
200 X86_XSTATE_XCR0_OFFSET + sizeof(uint64_t) <= sizeof(struct savexmm));
201
202 static void fpu_clean_state(void);
203 #endif
204
205 static void fpusave(union savefpu *);
206 static void fpurstor(union savefpu *);
207
208 int hw_float;
209
210 SYSCTL_INT(_hw, HW_FLOATINGPT, floatingpoint, CTLFLAG_RD,
211 &hw_float, 0, "Floating point instructions executed in hardware");
212
213 #ifdef CPU_ENABLE_SSE
214 int use_xsave;
215 uint64_t xsave_mask;
216 #endif
217 static uma_zone_t fpu_save_area_zone;
218 static union savefpu *npx_initialstate;
219
220 #ifdef CPU_ENABLE_SSE
221 struct xsave_area_elm_descr {
222 u_int offset;
223 u_int size;
224 } *xsave_area_desc;
225
226 static int use_xsaveopt;
227 #endif
228
229 static volatile u_int npx_traps_while_probing;
230
231 alias_for_inthand_t probetrap;
232 __asm(" \n\
233 .text \n\
234 .p2align 2,0x90 \n\
235 .type " __XSTRING(CNAME(probetrap)) ",@function \n\
236 " __XSTRING(CNAME(probetrap)) ": \n\
237 ss \n\
238 incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\
239 fnclex \n\
240 iret \n\
241 ");
242
243 /*
244 * Determine if an FPU is present and how to use it.
245 */
246 static int
247 npx_probe(void)
248 {
249 struct gate_descriptor save_idt_npxtrap;
250 u_short control, status;
251
252 /*
253 * Modern CPUs all have an FPU that uses the INT16 interface
254 * and provide a simple way to verify that, so handle the
255 * common case right away.
256 */
257 if (cpu_feature & CPUID_FPU) {
258 hw_float = 1;
259 return (1);
260 }
261
262 save_idt_npxtrap = idt[IDT_MF];
263 setidt(IDT_MF, probetrap, SDT_SYS386TGT, SEL_KPL,
264 GSEL(GCODE_SEL, SEL_KPL));
265
266 /*
267 * Don't trap while we're probing.
268 */
269 stop_emulating();
270
271 /*
272 * Finish resetting the coprocessor, if any. If there is an error
273 * pending, then we may get a bogus IRQ13, but npx_intr() will handle
274 * it OK. Bogus halts have never been observed, but we enabled
275 * IRQ13 and cleared the BUSY# latch early to handle them anyway.
276 */
277 fninit();
278
279 /*
280 * Don't use fwait here because it might hang.
281 * Don't use fnop here because it usually hangs if there is no FPU.
282 */
283 DELAY(1000); /* wait for any IRQ13 */
284 #ifdef DIAGNOSTIC
285 if (npx_traps_while_probing != 0)
286 printf("fninit caused %u bogus npx trap(s)\n",
287 npx_traps_while_probing);
288 #endif
289 /*
290 * Check for a status of mostly zero.
291 */
292 status = 0x5a5a;
293 fnstsw(&status);
294 if ((status & 0xb8ff) == 0) {
295 /*
296 * Good, now check for a proper control word.
297 */
298 control = 0x5a5a;
299 fnstcw(&control);
300 if ((control & 0x1f3f) == 0x033f) {
301 /*
302 * We have an npx, now divide by 0 to see if exception
303 * 16 works.
304 */
305 control &= ~(1 << 2); /* enable divide by 0 trap */
306 fldcw(control);
307 #ifdef FPU_ERROR_BROKEN
308 /*
309 * FPU error signal doesn't work on some CPU
310 * accelerator board.
311 */
312 hw_float = 1;
313 return (1);
314 #endif
315 npx_traps_while_probing = 0;
316 fp_divide_by_0();
317 if (npx_traps_while_probing != 0) {
318 /*
319 * Good, exception 16 works.
320 */
321 hw_float = 1;
322 goto cleanup;
323 }
324 printf(
325 "FPU does not use exception 16 for error reporting\n");
326 goto cleanup;
327 }
328 }
329
330 /*
331 * Probe failed. Floating point simply won't work.
332 * Notify user and disable FPU/MMX/SSE instruction execution.
333 */
334 printf("WARNING: no FPU!\n");
335 __asm __volatile("smsw %%ax; orb %0,%%al; lmsw %%ax" : :
336 "n" (CR0_EM | CR0_MP) : "ax");
337
338 cleanup:
339 idt[IDT_MF] = save_idt_npxtrap;
340 return (hw_float);
341 }
342
343 #ifdef CPU_ENABLE_SSE
344 /*
345 * Enable XSAVE if supported and allowed by user.
346 * Calculate the xsave_mask.
347 */
348 static void
349 npxinit_bsp1(void)
350 {
351 u_int cp[4];
352 uint64_t xsave_mask_user;
353
354 if (cpu_fxsr && (cpu_feature2 & CPUID2_XSAVE) != 0) {
355 use_xsave = 1;
356 TUNABLE_INT_FETCH("hw.use_xsave", &use_xsave);
357 }
358 if (!use_xsave)
359 return;
360
361 cpuid_count(0xd, 0x0, cp);
362 xsave_mask = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE;
363 if ((cp[0] & xsave_mask) != xsave_mask)
364 panic("CPU0 does not support X87 or SSE: %x", cp[0]);
365 xsave_mask = ((uint64_t)cp[3] << 32) | cp[0];
366 xsave_mask_user = xsave_mask;
367 TUNABLE_QUAD_FETCH("hw.xsave_mask", &xsave_mask_user);
368 xsave_mask_user |= XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE;
369 xsave_mask &= xsave_mask_user;
370 if ((xsave_mask & XFEATURE_AVX512) != XFEATURE_AVX512)
371 xsave_mask &= ~XFEATURE_AVX512;
372 if ((xsave_mask & XFEATURE_MPX) != XFEATURE_MPX)
373 xsave_mask &= ~XFEATURE_MPX;
374
375 cpuid_count(0xd, 0x1, cp);
376 if ((cp[0] & CPUID_EXTSTATE_XSAVEOPT) != 0)
377 use_xsaveopt = 1;
378 }
379 #endif
380 /*
381
382 * Calculate the fpu save area size.
383 */
384 static void
385 npxinit_bsp2(void)
386 {
387 #ifdef CPU_ENABLE_SSE
388 u_int cp[4];
389
390 if (use_xsave) {
391 cpuid_count(0xd, 0x0, cp);
392 cpu_max_ext_state_size = cp[1];
393
394 /*
395 * Reload the cpu_feature2, since we enabled OSXSAVE.
396 */
397 do_cpuid(1, cp);
398 cpu_feature2 = cp[2];
399 } else
400 #endif
401 cpu_max_ext_state_size = sizeof(union savefpu);
402 }
403
404 /*
405 * Initialize floating point unit.
406 */
407 void
408 npxinit(bool bsp)
409 {
410 static union savefpu dummy;
411 register_t saveintr;
412 #ifdef CPU_ENABLE_SSE
413 u_int mxcsr;
414 #endif
415 u_short control;
416
417 if (bsp) {
418 if (!npx_probe())
419 return;
420 #ifdef CPU_ENABLE_SSE
421 npxinit_bsp1();
422 #endif
423 }
424
425 #ifdef CPU_ENABLE_SSE
426 if (use_xsave) {
427 load_cr4(rcr4() | CR4_XSAVE);
428 load_xcr(XCR0, xsave_mask);
429 }
430 #endif
431
432 /*
433 * XCR0 shall be set up before CPU can report the save area size.
434 */
435 if (bsp)
436 npxinit_bsp2();
437
438 /*
439 * fninit has the same h/w bugs as fnsave. Use the detoxified
440 * fnsave to throw away any junk in the fpu. fpusave() initializes
441 * the fpu.
442 *
443 * It is too early for critical_enter() to work on AP.
444 */
445 saveintr = intr_disable();
446 stop_emulating();
447 #ifdef CPU_ENABLE_SSE
448 if (cpu_fxsr)
449 fninit();
450 else
451 #endif
452 fnsave(&dummy);
453 control = __INITIAL_NPXCW__;
454 fldcw(control);
455 #ifdef CPU_ENABLE_SSE
456 if (cpu_fxsr) {
457 mxcsr = __INITIAL_MXCSR__;
458 ldmxcsr(mxcsr);
459 }
460 #endif
461 start_emulating();
462 intr_restore(saveintr);
463 }
464
465 /*
466 * On the boot CPU we generate a clean state that is used to
467 * initialize the floating point unit when it is first used by a
468 * process.
469 */
470 static void
471 npxinitstate(void *arg __unused)
472 {
473 register_t saveintr;
474 #ifdef CPU_ENABLE_SSE
475 int cp[4], i, max_ext_n;
476 #endif
477
478 if (!hw_float)
479 return;
480
481 npx_initialstate = malloc(cpu_max_ext_state_size, M_DEVBUF,
482 M_WAITOK | M_ZERO);
483 saveintr = intr_disable();
484 stop_emulating();
485
486 fpusave(npx_initialstate);
487 #ifdef CPU_ENABLE_SSE
488 if (cpu_fxsr) {
489 if (npx_initialstate->sv_xmm.sv_env.en_mxcsr_mask)
490 cpu_mxcsr_mask =
491 npx_initialstate->sv_xmm.sv_env.en_mxcsr_mask;
492 else
493 cpu_mxcsr_mask = 0xFFBF;
494
495 /*
496 * The fninit instruction does not modify XMM
497 * registers or x87 registers (MM/ST). The fpusave
498 * call dumped the garbage contained in the registers
499 * after reset to the initial state saved. Clear XMM
500 * and x87 registers file image to make the startup
501 * program state and signal handler XMM/x87 register
502 * content predictable.
503 */
504 bzero(npx_initialstate->sv_xmm.sv_fp,
505 sizeof(npx_initialstate->sv_xmm.sv_fp));
506 bzero(npx_initialstate->sv_xmm.sv_xmm,
507 sizeof(npx_initialstate->sv_xmm.sv_xmm));
508 } else
509 #endif
510 bzero(npx_initialstate->sv_87.sv_ac,
511 sizeof(npx_initialstate->sv_87.sv_ac));
512
513 #ifdef CPU_ENABLE_SSE
514 /*
515 * Create a table describing the layout of the CPU Extended
516 * Save Area.
517 */
518 if (use_xsave) {
519 if (xsave_mask >> 32 != 0)
520 max_ext_n = fls(xsave_mask >> 32) + 32;
521 else
522 max_ext_n = fls(xsave_mask);
523 xsave_area_desc = malloc(max_ext_n * sizeof(struct
524 xsave_area_elm_descr), M_DEVBUF, M_WAITOK | M_ZERO);
525 /* x87 state */
526 xsave_area_desc[0].offset = 0;
527 xsave_area_desc[0].size = 160;
528 /* XMM */
529 xsave_area_desc[1].offset = 160;
530 xsave_area_desc[1].size = 288 - 160;
531
532 for (i = 2; i < max_ext_n; i++) {
533 cpuid_count(0xd, i, cp);
534 xsave_area_desc[i].offset = cp[1];
535 xsave_area_desc[i].size = cp[0];
536 }
537 }
538 #endif
539
540 fpu_save_area_zone = uma_zcreate("FPU_save_area",
541 cpu_max_ext_state_size, NULL, NULL, NULL, NULL,
542 XSAVE_AREA_ALIGN - 1, 0);
543
544 start_emulating();
545 intr_restore(saveintr);
546 }
547 SYSINIT(npxinitstate, SI_SUB_DRIVERS, SI_ORDER_ANY, npxinitstate, NULL);
548
549 /*
550 * Free coprocessor (if we have it).
551 */
552 void
553 npxexit(td)
554 struct thread *td;
555 {
556
557 critical_enter();
558 if (curthread == PCPU_GET(fpcurthread)) {
559 stop_emulating();
560 fpusave(curpcb->pcb_save);
561 start_emulating();
562 PCPU_SET(fpcurthread, NULL);
563 }
564 critical_exit();
565 #ifdef NPX_DEBUG
566 if (hw_float) {
567 u_int masked_exceptions;
568
569 masked_exceptions = GET_FPU_CW(td) & GET_FPU_SW(td) & 0x7f;
570 /*
571 * Log exceptions that would have trapped with the old
572 * control word (overflow, divide by 0, and invalid operand).
573 */
574 if (masked_exceptions & 0x0d)
575 log(LOG_ERR,
576 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n",
577 td->td_proc->p_pid, td->td_proc->p_comm,
578 masked_exceptions);
579 }
580 #endif
581 }
582
583 int
584 npxformat()
585 {
586
587 if (!hw_float)
588 return (_MC_FPFMT_NODEV);
589 #ifdef CPU_ENABLE_SSE
590 if (cpu_fxsr)
591 return (_MC_FPFMT_XMM);
592 #endif
593 return (_MC_FPFMT_387);
594 }
595
596 /*
597 * The following mechanism is used to ensure that the FPE_... value
598 * that is passed as a trapcode to the signal handler of the user
599 * process does not have more than one bit set.
600 *
601 * Multiple bits may be set if the user process modifies the control
602 * word while a status word bit is already set. While this is a sign
603 * of bad coding, we have no choise than to narrow them down to one
604 * bit, since we must not send a trapcode that is not exactly one of
605 * the FPE_ macros.
606 *
607 * The mechanism has a static table with 127 entries. Each combination
608 * of the 7 FPU status word exception bits directly translates to a
609 * position in this table, where a single FPE_... value is stored.
610 * This FPE_... value stored there is considered the "most important"
611 * of the exception bits and will be sent as the signal code. The
612 * precedence of the bits is based upon Intel Document "Numerical
613 * Applications", Chapter "Special Computational Situations".
614 *
615 * The macro to choose one of these values does these steps: 1) Throw
616 * away status word bits that cannot be masked. 2) Throw away the bits
617 * currently masked in the control word, assuming the user isn't
618 * interested in them anymore. 3) Reinsert status word bit 7 (stack
619 * fault) if it is set, which cannot be masked but must be presered.
620 * 4) Use the remaining bits to point into the trapcode table.
621 *
622 * The 6 maskable bits in order of their preference, as stated in the
623 * above referenced Intel manual:
624 * 1 Invalid operation (FP_X_INV)
625 * 1a Stack underflow
626 * 1b Stack overflow
627 * 1c Operand of unsupported format
628 * 1d SNaN operand.
629 * 2 QNaN operand (not an exception, irrelavant here)
630 * 3 Any other invalid-operation not mentioned above or zero divide
631 * (FP_X_INV, FP_X_DZ)
632 * 4 Denormal operand (FP_X_DNML)
633 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL)
634 * 6 Inexact result (FP_X_IMP)
635 */
636 static char fpetable[128] = {
637 0,
638 FPE_FLTINV, /* 1 - INV */
639 FPE_FLTUND, /* 2 - DNML */
640 FPE_FLTINV, /* 3 - INV | DNML */
641 FPE_FLTDIV, /* 4 - DZ */
642 FPE_FLTINV, /* 5 - INV | DZ */
643 FPE_FLTDIV, /* 6 - DNML | DZ */
644 FPE_FLTINV, /* 7 - INV | DNML | DZ */
645 FPE_FLTOVF, /* 8 - OFL */
646 FPE_FLTINV, /* 9 - INV | OFL */
647 FPE_FLTUND, /* A - DNML | OFL */
648 FPE_FLTINV, /* B - INV | DNML | OFL */
649 FPE_FLTDIV, /* C - DZ | OFL */
650 FPE_FLTINV, /* D - INV | DZ | OFL */
651 FPE_FLTDIV, /* E - DNML | DZ | OFL */
652 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */
653 FPE_FLTUND, /* 10 - UFL */
654 FPE_FLTINV, /* 11 - INV | UFL */
655 FPE_FLTUND, /* 12 - DNML | UFL */
656 FPE_FLTINV, /* 13 - INV | DNML | UFL */
657 FPE_FLTDIV, /* 14 - DZ | UFL */
658 FPE_FLTINV, /* 15 - INV | DZ | UFL */
659 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */
660 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */
661 FPE_FLTOVF, /* 18 - OFL | UFL */
662 FPE_FLTINV, /* 19 - INV | OFL | UFL */
663 FPE_FLTUND, /* 1A - DNML | OFL | UFL */
664 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */
665 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */
666 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */
667 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */
668 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */
669 FPE_FLTRES, /* 20 - IMP */
670 FPE_FLTINV, /* 21 - INV | IMP */
671 FPE_FLTUND, /* 22 - DNML | IMP */
672 FPE_FLTINV, /* 23 - INV | DNML | IMP */
673 FPE_FLTDIV, /* 24 - DZ | IMP */
674 FPE_FLTINV, /* 25 - INV | DZ | IMP */
675 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */
676 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */
677 FPE_FLTOVF, /* 28 - OFL | IMP */
678 FPE_FLTINV, /* 29 - INV | OFL | IMP */
679 FPE_FLTUND, /* 2A - DNML | OFL | IMP */
680 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */
681 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */
682 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */
683 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */
684 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */
685 FPE_FLTUND, /* 30 - UFL | IMP */
686 FPE_FLTINV, /* 31 - INV | UFL | IMP */
687 FPE_FLTUND, /* 32 - DNML | UFL | IMP */
688 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */
689 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */
690 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */
691 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */
692 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */
693 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */
694 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */
695 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */
696 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */
697 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */
698 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */
699 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */
700 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */
701 FPE_FLTSUB, /* 40 - STK */
702 FPE_FLTSUB, /* 41 - INV | STK */
703 FPE_FLTUND, /* 42 - DNML | STK */
704 FPE_FLTSUB, /* 43 - INV | DNML | STK */
705 FPE_FLTDIV, /* 44 - DZ | STK */
706 FPE_FLTSUB, /* 45 - INV | DZ | STK */
707 FPE_FLTDIV, /* 46 - DNML | DZ | STK */
708 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */
709 FPE_FLTOVF, /* 48 - OFL | STK */
710 FPE_FLTSUB, /* 49 - INV | OFL | STK */
711 FPE_FLTUND, /* 4A - DNML | OFL | STK */
712 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */
713 FPE_FLTDIV, /* 4C - DZ | OFL | STK */
714 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */
715 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */
716 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */
717 FPE_FLTUND, /* 50 - UFL | STK */
718 FPE_FLTSUB, /* 51 - INV | UFL | STK */
719 FPE_FLTUND, /* 52 - DNML | UFL | STK */
720 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */
721 FPE_FLTDIV, /* 54 - DZ | UFL | STK */
722 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */
723 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */
724 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */
725 FPE_FLTOVF, /* 58 - OFL | UFL | STK */
726 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */
727 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */
728 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */
729 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */
730 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */
731 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */
732 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */
733 FPE_FLTRES, /* 60 - IMP | STK */
734 FPE_FLTSUB, /* 61 - INV | IMP | STK */
735 FPE_FLTUND, /* 62 - DNML | IMP | STK */
736 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */
737 FPE_FLTDIV, /* 64 - DZ | IMP | STK */
738 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */
739 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */
740 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */
741 FPE_FLTOVF, /* 68 - OFL | IMP | STK */
742 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */
743 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */
744 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */
745 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */
746 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */
747 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */
748 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */
749 FPE_FLTUND, /* 70 - UFL | IMP | STK */
750 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */
751 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */
752 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */
753 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */
754 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */
755 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */
756 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */
757 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */
758 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */
759 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */
760 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */
761 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */
762 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */
763 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */
764 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */
765 };
766
767 /*
768 * Read the FP status and control words, then generate si_code value
769 * for SIGFPE. The error code chosen will be one of the
770 * FPE_... macros. It will be sent as the second argument to old
771 * BSD-style signal handlers and as "siginfo_t->si_code" (second
772 * argument) to SA_SIGINFO signal handlers.
773 *
774 * Some time ago, we cleared the x87 exceptions with FNCLEX there.
775 * Clearing exceptions was necessary mainly to avoid IRQ13 bugs. The
776 * usermode code which understands the FPU hardware enough to enable
777 * the exceptions, can also handle clearing the exception state in the
778 * handler. The only consequence of not clearing the exception is the
779 * rethrow of the SIGFPE on return from the signal handler and
780 * reexecution of the corresponding instruction.
781 *
782 * For XMM traps, the exceptions were never cleared.
783 */
784 int
785 npxtrap_x87(void)
786 {
787 u_short control, status;
788
789 if (!hw_float) {
790 printf(
791 "npxtrap_x87: fpcurthread = %p, curthread = %p, hw_float = %d\n",
792 PCPU_GET(fpcurthread), curthread, hw_float);
793 panic("npxtrap from nowhere");
794 }
795 critical_enter();
796
797 /*
798 * Interrupt handling (for another interrupt) may have pushed the
799 * state to memory. Fetch the relevant parts of the state from
800 * wherever they are.
801 */
802 if (PCPU_GET(fpcurthread) != curthread) {
803 control = GET_FPU_CW(curthread);
804 status = GET_FPU_SW(curthread);
805 } else {
806 fnstcw(&control);
807 fnstsw(&status);
808 }
809 critical_exit();
810 return (fpetable[status & ((~control & 0x3f) | 0x40)]);
811 }
812
813 #ifdef CPU_ENABLE_SSE
814 int
815 npxtrap_sse(void)
816 {
817 u_int mxcsr;
818
819 if (!hw_float) {
820 printf(
821 "npxtrap_sse: fpcurthread = %p, curthread = %p, hw_float = %d\n",
822 PCPU_GET(fpcurthread), curthread, hw_float);
823 panic("npxtrap from nowhere");
824 }
825 critical_enter();
826 if (PCPU_GET(fpcurthread) != curthread)
827 mxcsr = curthread->td_pcb->pcb_save->sv_xmm.sv_env.en_mxcsr;
828 else
829 stmxcsr(&mxcsr);
830 critical_exit();
831 return (fpetable[(mxcsr & (~mxcsr >> 7)) & 0x3f]);
832 }
833 #endif
834
835 /*
836 * Implement device not available (DNA) exception
837 *
838 * It would be better to switch FP context here (if curthread != fpcurthread)
839 * and not necessarily for every context switch, but it is too hard to
840 * access foreign pcb's.
841 */
842
843 static int err_count = 0;
844
845 int
846 npxdna(void)
847 {
848
849 if (!hw_float)
850 return (0);
851 critical_enter();
852 if (PCPU_GET(fpcurthread) == curthread) {
853 printf("npxdna: fpcurthread == curthread %d times\n",
854 ++err_count);
855 stop_emulating();
856 critical_exit();
857 return (1);
858 }
859 if (PCPU_GET(fpcurthread) != NULL) {
860 printf("npxdna: fpcurthread = %p (%d), curthread = %p (%d)\n",
861 PCPU_GET(fpcurthread),
862 PCPU_GET(fpcurthread)->td_proc->p_pid,
863 curthread, curthread->td_proc->p_pid);
864 panic("npxdna");
865 }
866 stop_emulating();
867 /*
868 * Record new context early in case frstor causes a trap.
869 */
870 PCPU_SET(fpcurthread, curthread);
871
872 #ifdef CPU_ENABLE_SSE
873 if (cpu_fxsr)
874 fpu_clean_state();
875 #endif
876
877 if ((curpcb->pcb_flags & PCB_NPXINITDONE) == 0) {
878 /*
879 * This is the first time this thread has used the FPU or
880 * the PCB doesn't contain a clean FPU state. Explicitly
881 * load an initial state.
882 *
883 * We prefer to restore the state from the actual save
884 * area in PCB instead of directly loading from
885 * npx_initialstate, to ignite the XSAVEOPT
886 * tracking engine.
887 */
888 bcopy(npx_initialstate, curpcb->pcb_save, cpu_max_ext_state_size);
889 fpurstor(curpcb->pcb_save);
890 if (curpcb->pcb_initial_npxcw != __INITIAL_NPXCW__)
891 fldcw(curpcb->pcb_initial_npxcw);
892 curpcb->pcb_flags |= PCB_NPXINITDONE;
893 if (PCB_USER_FPU(curpcb))
894 curpcb->pcb_flags |= PCB_NPXUSERINITDONE;
895 } else {
896 fpurstor(curpcb->pcb_save);
897 }
898 critical_exit();
899
900 return (1);
901 }
902
903 /*
904 * Wrapper for fpusave() called from context switch routines.
905 *
906 * npxsave() must be called with interrupts disabled, so that it clears
907 * fpcurthread atomically with saving the state. We require callers to do the
908 * disabling, since most callers need to disable interrupts anyway to call
909 * npxsave() atomically with checking fpcurthread.
910 */
911 void
912 npxsave(addr)
913 union savefpu *addr;
914 {
915
916 stop_emulating();
917 #ifdef CPU_ENABLE_SSE
918 if (use_xsaveopt)
919 xsaveopt((char *)addr, xsave_mask);
920 else
921 #endif
922 fpusave(addr);
923 start_emulating();
924 PCPU_SET(fpcurthread, NULL);
925 }
926
927 /*
928 * Unconditionally save the current co-processor state across suspend and
929 * resume.
930 */
931 void
932 npxsuspend(union savefpu *addr)
933 {
934 register_t cr0;
935
936 if (!hw_float)
937 return;
938 if (PCPU_GET(fpcurthread) == NULL) {
939 bcopy(npx_initialstate, addr, cpu_max_ext_state_size);
940 return;
941 }
942 cr0 = rcr0();
943 stop_emulating();
944 fpusave(addr);
945 load_cr0(cr0);
946 }
947
948 void
949 npxresume(union savefpu *addr)
950 {
951 register_t cr0;
952
953 if (!hw_float)
954 return;
955
956 cr0 = rcr0();
957 npxinit(false);
958 stop_emulating();
959 fpurstor(addr);
960 load_cr0(cr0);
961 }
962
963 void
964 npxdrop()
965 {
966 struct thread *td;
967
968 /*
969 * Discard pending exceptions in the !cpu_fxsr case so that unmasked
970 * ones don't cause a panic on the next frstor.
971 */
972 #ifdef CPU_ENABLE_SSE
973 if (!cpu_fxsr)
974 #endif
975 fnclex();
976
977 td = PCPU_GET(fpcurthread);
978 KASSERT(td == curthread, ("fpudrop: fpcurthread != curthread"));
979 CRITICAL_ASSERT(td);
980 PCPU_SET(fpcurthread, NULL);
981 td->td_pcb->pcb_flags &= ~PCB_NPXINITDONE;
982 start_emulating();
983 }
984
985 /*
986 * Get the user state of the FPU into pcb->pcb_user_save without
987 * dropping ownership (if possible). It returns the FPU ownership
988 * status.
989 */
990 int
991 npxgetregs(struct thread *td)
992 {
993 struct pcb *pcb;
994 #ifdef CPU_ENABLE_SSE
995 uint64_t *xstate_bv, bit;
996 char *sa;
997 int max_ext_n, i;
998 #endif
999 int owned;
1000
1001 if (!hw_float)
1002 return (_MC_FPOWNED_NONE);
1003
1004 pcb = td->td_pcb;
1005 if ((pcb->pcb_flags & PCB_NPXINITDONE) == 0) {
1006 bcopy(npx_initialstate, get_pcb_user_save_pcb(pcb),
1007 cpu_max_ext_state_size);
1008 SET_FPU_CW(get_pcb_user_save_pcb(pcb), pcb->pcb_initial_npxcw);
1009 npxuserinited(td);
1010 return (_MC_FPOWNED_PCB);
1011 }
1012 critical_enter();
1013 if (td == PCPU_GET(fpcurthread)) {
1014 fpusave(get_pcb_user_save_pcb(pcb));
1015 #ifdef CPU_ENABLE_SSE
1016 if (!cpu_fxsr)
1017 #endif
1018 /*
1019 * fnsave initializes the FPU and destroys whatever
1020 * context it contains. Make sure the FPU owner
1021 * starts with a clean state next time.
1022 */
1023 npxdrop();
1024 owned = _MC_FPOWNED_FPU;
1025 } else {
1026 owned = _MC_FPOWNED_PCB;
1027 }
1028 critical_exit();
1029 #ifdef CPU_ENABLE_SSE
1030 if (use_xsave) {
1031 /*
1032 * Handle partially saved state.
1033 */
1034 sa = (char *)get_pcb_user_save_pcb(pcb);
1035 xstate_bv = (uint64_t *)(sa + sizeof(union savefpu) +
1036 offsetof(struct xstate_hdr, xstate_bv));
1037 if (xsave_mask >> 32 != 0)
1038 max_ext_n = fls(xsave_mask >> 32) + 32;
1039 else
1040 max_ext_n = fls(xsave_mask);
1041 for (i = 0; i < max_ext_n; i++) {
1042 bit = 1ULL << i;
1043 if ((xsave_mask & bit) == 0 || (*xstate_bv & bit) != 0)
1044 continue;
1045 bcopy((char *)npx_initialstate +
1046 xsave_area_desc[i].offset,
1047 sa + xsave_area_desc[i].offset,
1048 xsave_area_desc[i].size);
1049 *xstate_bv |= bit;
1050 }
1051 }
1052 #endif
1053 return (owned);
1054 }
1055
1056 void
1057 npxuserinited(struct thread *td)
1058 {
1059 struct pcb *pcb;
1060
1061 pcb = td->td_pcb;
1062 if (PCB_USER_FPU(pcb))
1063 pcb->pcb_flags |= PCB_NPXINITDONE;
1064 pcb->pcb_flags |= PCB_NPXUSERINITDONE;
1065 }
1066
1067 #ifdef CPU_ENABLE_SSE
1068 int
1069 npxsetxstate(struct thread *td, char *xfpustate, size_t xfpustate_size)
1070 {
1071 struct xstate_hdr *hdr, *ehdr;
1072 size_t len, max_len;
1073 uint64_t bv;
1074
1075 /* XXXKIB should we clear all extended state in xstate_bv instead ? */
1076 if (xfpustate == NULL)
1077 return (0);
1078 if (!use_xsave)
1079 return (EOPNOTSUPP);
1080
1081 len = xfpustate_size;
1082 if (len < sizeof(struct xstate_hdr))
1083 return (EINVAL);
1084 max_len = cpu_max_ext_state_size - sizeof(union savefpu);
1085 if (len > max_len)
1086 return (EINVAL);
1087
1088 ehdr = (struct xstate_hdr *)xfpustate;
1089 bv = ehdr->xstate_bv;
1090
1091 /*
1092 * Avoid #gp.
1093 */
1094 if (bv & ~xsave_mask)
1095 return (EINVAL);
1096
1097 hdr = (struct xstate_hdr *)(get_pcb_user_save_td(td) + 1);
1098
1099 hdr->xstate_bv = bv;
1100 bcopy(xfpustate + sizeof(struct xstate_hdr),
1101 (char *)(hdr + 1), len - sizeof(struct xstate_hdr));
1102
1103 return (0);
1104 }
1105 #endif
1106
1107 int
1108 npxsetregs(struct thread *td, union savefpu *addr, char *xfpustate,
1109 size_t xfpustate_size)
1110 {
1111 struct pcb *pcb;
1112 #ifdef CPU_ENABLE_SSE
1113 int error;
1114 #endif
1115
1116 if (!hw_float)
1117 return (ENXIO);
1118
1119 pcb = td->td_pcb;
1120 critical_enter();
1121 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) {
1122 #ifdef CPU_ENABLE_SSE
1123 error = npxsetxstate(td, xfpustate, xfpustate_size);
1124 if (error != 0) {
1125 critical_exit();
1126 return (error);
1127 }
1128 if (!cpu_fxsr)
1129 #endif
1130 fnclex(); /* As in npxdrop(). */
1131 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr));
1132 fpurstor(get_pcb_user_save_td(td));
1133 critical_exit();
1134 pcb->pcb_flags |= PCB_NPXUSERINITDONE | PCB_NPXINITDONE;
1135 } else {
1136 critical_exit();
1137 #ifdef CPU_ENABLE_SSE
1138 error = npxsetxstate(td, xfpustate, xfpustate_size);
1139 if (error != 0)
1140 return (error);
1141 #endif
1142 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr));
1143 npxuserinited(td);
1144 }
1145 return (0);
1146 }
1147
1148 static void
1149 fpusave(addr)
1150 union savefpu *addr;
1151 {
1152
1153 #ifdef CPU_ENABLE_SSE
1154 if (use_xsave)
1155 xsave((char *)addr, xsave_mask);
1156 else if (cpu_fxsr)
1157 fxsave(addr);
1158 else
1159 #endif
1160 fnsave(addr);
1161 }
1162
1163 #ifdef CPU_ENABLE_SSE
1164 static void
1165 npx_fill_fpregs_xmm1(struct savexmm *sv_xmm, struct save87 *sv_87)
1166 {
1167 struct env87 *penv_87;
1168 struct envxmm *penv_xmm;
1169 int i;
1170
1171 penv_87 = &sv_87->sv_env;
1172 penv_xmm = &sv_xmm->sv_env;
1173
1174 /* FPU control/status */
1175 penv_87->en_cw = penv_xmm->en_cw;
1176 penv_87->en_sw = penv_xmm->en_sw;
1177 penv_87->en_fip = penv_xmm->en_fip;
1178 penv_87->en_fcs = penv_xmm->en_fcs;
1179 penv_87->en_opcode = penv_xmm->en_opcode;
1180 penv_87->en_foo = penv_xmm->en_foo;
1181 penv_87->en_fos = penv_xmm->en_fos;
1182
1183 /* FPU registers and tags */
1184 penv_87->en_tw = 0xffff;
1185 for (i = 0; i < 8; ++i) {
1186 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc;
1187 if ((penv_xmm->en_tw & (1 << i)) != 0)
1188 /* zero and special are set as valid */
1189 penv_87->en_tw &= ~(3 << i);
1190 }
1191 }
1192
1193 void
1194 npx_fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87)
1195 {
1196
1197 bzero(sv_87, sizeof(*sv_87));
1198 npx_fill_fpregs_xmm1(sv_xmm, sv_87);
1199 }
1200
1201 void
1202 npx_set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm)
1203 {
1204 struct env87 *penv_87;
1205 struct envxmm *penv_xmm;
1206 int i;
1207
1208 penv_87 = &sv_87->sv_env;
1209 penv_xmm = &sv_xmm->sv_env;
1210
1211 /* FPU control/status */
1212 penv_xmm->en_cw = penv_87->en_cw;
1213 penv_xmm->en_sw = penv_87->en_sw;
1214 penv_xmm->en_fip = penv_87->en_fip;
1215 penv_xmm->en_fcs = penv_87->en_fcs;
1216 penv_xmm->en_opcode = penv_87->en_opcode;
1217 penv_xmm->en_foo = penv_87->en_foo;
1218 penv_xmm->en_fos = penv_87->en_fos;
1219
1220 /* FPU registers and tags */
1221 penv_xmm->en_tw = 0;
1222 for (i = 0; i < 8; ++i) {
1223 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i];
1224 if ((penv_87->en_tw && (3 << i)) != (3 << i))
1225 penv_xmm->en_tw |= 1 << i;
1226 }
1227 }
1228 #endif /* CPU_ENABLE_SSE */
1229
1230 void
1231 npx_get_fsave(void *addr)
1232 {
1233 struct thread *td;
1234 union savefpu *sv;
1235
1236 td = curthread;
1237 npxgetregs(td);
1238 sv = get_pcb_user_save_td(td);
1239 #ifdef CPU_ENABLE_SSE
1240 if (cpu_fxsr)
1241 npx_fill_fpregs_xmm1(&sv->sv_xmm, addr);
1242 else
1243 #endif
1244 bcopy(sv, addr, sizeof(struct env87) +
1245 sizeof(struct fpacc87[8]));
1246 }
1247
1248 int
1249 npx_set_fsave(void *addr)
1250 {
1251 union savefpu sv;
1252 int error;
1253
1254 bzero(&sv, sizeof(sv));
1255 #ifdef CPU_ENABLE_SSE
1256 if (cpu_fxsr)
1257 npx_set_fpregs_xmm(addr, &sv.sv_xmm);
1258 else
1259 #endif
1260 bcopy(addr, &sv, sizeof(struct env87) +
1261 sizeof(struct fpacc87[8]));
1262 error = npxsetregs(curthread, &sv, NULL, 0);
1263 return (error);
1264 }
1265
1266 #ifdef CPU_ENABLE_SSE
1267 /*
1268 * On AuthenticAMD processors, the fxrstor instruction does not restore
1269 * the x87's stored last instruction pointer, last data pointer, and last
1270 * opcode values, except in the rare case in which the exception summary
1271 * (ES) bit in the x87 status word is set to 1.
1272 *
1273 * In order to avoid leaking this information across processes, we clean
1274 * these values by performing a dummy load before executing fxrstor().
1275 */
1276 static void
1277 fpu_clean_state(void)
1278 {
1279 static float dummy_variable = 0.0;
1280 u_short status;
1281
1282 /*
1283 * Clear the ES bit in the x87 status word if it is currently
1284 * set, in order to avoid causing a fault in the upcoming load.
1285 */
1286 fnstsw(&status);
1287 if (status & 0x80)
1288 fnclex();
1289
1290 /*
1291 * Load the dummy variable into the x87 stack. This mangles
1292 * the x87 stack, but we don't care since we're about to call
1293 * fxrstor() anyway.
1294 */
1295 __asm __volatile("ffree %%st(7); flds %0" : : "m" (dummy_variable));
1296 }
1297 #endif /* CPU_ENABLE_SSE */
1298
1299 static void
1300 fpurstor(addr)
1301 union savefpu *addr;
1302 {
1303
1304 #ifdef CPU_ENABLE_SSE
1305 if (use_xsave)
1306 xrstor((char *)addr, xsave_mask);
1307 else if (cpu_fxsr)
1308 fxrstor(addr);
1309 else
1310 #endif
1311 frstor(addr);
1312 }
1313
1314 #ifdef DEV_ISA
1315 /*
1316 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI.
1317 */
1318 static struct isa_pnp_id npxisa_ids[] = {
1319 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */
1320 { 0 }
1321 };
1322
1323 static int
1324 npxisa_probe(device_t dev)
1325 {
1326 int result;
1327 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, npxisa_ids)) <= 0) {
1328 device_quiet(dev);
1329 }
1330 return(result);
1331 }
1332
1333 static int
1334 npxisa_attach(device_t dev)
1335 {
1336 return (0);
1337 }
1338
1339 static device_method_t npxisa_methods[] = {
1340 /* Device interface */
1341 DEVMETHOD(device_probe, npxisa_probe),
1342 DEVMETHOD(device_attach, npxisa_attach),
1343 DEVMETHOD(device_detach, bus_generic_detach),
1344 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1345 DEVMETHOD(device_suspend, bus_generic_suspend),
1346 DEVMETHOD(device_resume, bus_generic_resume),
1347
1348 { 0, 0 }
1349 };
1350
1351 static driver_t npxisa_driver = {
1352 "npxisa",
1353 npxisa_methods,
1354 1, /* no softc */
1355 };
1356
1357 static devclass_t npxisa_devclass;
1358
1359 DRIVER_MODULE(npxisa, isa, npxisa_driver, npxisa_devclass, 0, 0);
1360 #ifndef PC98
1361 DRIVER_MODULE(npxisa, acpi, npxisa_driver, npxisa_devclass, 0, 0);
1362 #endif
1363 #endif /* DEV_ISA */
1364
1365 static MALLOC_DEFINE(M_FPUKERN_CTX, "fpukern_ctx",
1366 "Kernel contexts for FPU state");
1367
1368 #define FPU_KERN_CTX_NPXINITDONE 0x01
1369 #define FPU_KERN_CTX_DUMMY 0x02
1370 #define FPU_KERN_CTX_INUSE 0x04
1371
1372 struct fpu_kern_ctx {
1373 union savefpu *prev;
1374 uint32_t flags;
1375 char hwstate1[];
1376 };
1377
1378 struct fpu_kern_ctx *
1379 fpu_kern_alloc_ctx(u_int flags)
1380 {
1381 struct fpu_kern_ctx *res;
1382 size_t sz;
1383
1384 sz = sizeof(struct fpu_kern_ctx) + XSAVE_AREA_ALIGN +
1385 cpu_max_ext_state_size;
1386 res = malloc(sz, M_FPUKERN_CTX, ((flags & FPU_KERN_NOWAIT) ?
1387 M_NOWAIT : M_WAITOK) | M_ZERO);
1388 return (res);
1389 }
1390
1391 void
1392 fpu_kern_free_ctx(struct fpu_kern_ctx *ctx)
1393 {
1394
1395 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) == 0, ("free'ing inuse ctx"));
1396 /* XXXKIB clear the memory ? */
1397 free(ctx, M_FPUKERN_CTX);
1398 }
1399
1400 static union savefpu *
1401 fpu_kern_ctx_savefpu(struct fpu_kern_ctx *ctx)
1402 {
1403 vm_offset_t p;
1404
1405 p = (vm_offset_t)&ctx->hwstate1;
1406 p = roundup2(p, XSAVE_AREA_ALIGN);
1407 return ((union savefpu *)p);
1408 }
1409
1410 int
1411 fpu_kern_enter(struct thread *td, struct fpu_kern_ctx *ctx, u_int flags)
1412 {
1413 struct pcb *pcb;
1414
1415 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) == 0, ("using inuse ctx"));
1416
1417 if ((flags & FPU_KERN_KTHR) != 0 && is_fpu_kern_thread(0)) {
1418 ctx->flags = FPU_KERN_CTX_DUMMY | FPU_KERN_CTX_INUSE;
1419 return (0);
1420 }
1421 pcb = td->td_pcb;
1422 KASSERT(!PCB_USER_FPU(pcb) || pcb->pcb_save ==
1423 get_pcb_user_save_pcb(pcb), ("mangled pcb_save"));
1424 ctx->flags = FPU_KERN_CTX_INUSE;
1425 if ((pcb->pcb_flags & PCB_NPXINITDONE) != 0)
1426 ctx->flags |= FPU_KERN_CTX_NPXINITDONE;
1427 npxexit(td);
1428 ctx->prev = pcb->pcb_save;
1429 pcb->pcb_save = fpu_kern_ctx_savefpu(ctx);
1430 pcb->pcb_flags |= PCB_KERNNPX;
1431 pcb->pcb_flags &= ~PCB_NPXINITDONE;
1432 return (0);
1433 }
1434
1435 int
1436 fpu_kern_leave(struct thread *td, struct fpu_kern_ctx *ctx)
1437 {
1438 struct pcb *pcb;
1439
1440 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) != 0,
1441 ("leaving not inuse ctx"));
1442 ctx->flags &= ~FPU_KERN_CTX_INUSE;
1443
1444 if (is_fpu_kern_thread(0) && (ctx->flags & FPU_KERN_CTX_DUMMY) != 0)
1445 return (0);
1446 pcb = td->td_pcb;
1447 critical_enter();
1448 if (curthread == PCPU_GET(fpcurthread))
1449 npxdrop();
1450 critical_exit();
1451 pcb->pcb_save = ctx->prev;
1452 if (pcb->pcb_save == get_pcb_user_save_pcb(pcb)) {
1453 if ((pcb->pcb_flags & PCB_NPXUSERINITDONE) != 0)
1454 pcb->pcb_flags |= PCB_NPXINITDONE;
1455 else
1456 pcb->pcb_flags &= ~PCB_NPXINITDONE;
1457 pcb->pcb_flags &= ~PCB_KERNNPX;
1458 } else {
1459 if ((ctx->flags & FPU_KERN_CTX_NPXINITDONE) != 0)
1460 pcb->pcb_flags |= PCB_NPXINITDONE;
1461 else
1462 pcb->pcb_flags &= ~PCB_NPXINITDONE;
1463 KASSERT(!PCB_USER_FPU(pcb), ("unpaired fpu_kern_leave"));
1464 }
1465 return (0);
1466 }
1467
1468 int
1469 fpu_kern_thread(u_int flags)
1470 {
1471
1472 KASSERT((curthread->td_pflags & TDP_KTHREAD) != 0,
1473 ("Only kthread may use fpu_kern_thread"));
1474 KASSERT(curpcb->pcb_save == get_pcb_user_save_pcb(curpcb),
1475 ("mangled pcb_save"));
1476 KASSERT(PCB_USER_FPU(curpcb), ("recursive call"));
1477
1478 curpcb->pcb_flags |= PCB_KERNNPX;
1479 return (0);
1480 }
1481
1482 int
1483 is_fpu_kern_thread(u_int flags)
1484 {
1485
1486 if ((curthread->td_pflags & TDP_KTHREAD) == 0)
1487 return (0);
1488 return ((curpcb->pcb_flags & PCB_KERNNPX) != 0);
1489 }
1490
1491 /*
1492 * FPU save area alloc/free/init utility routines
1493 */
1494 union savefpu *
1495 fpu_save_area_alloc(void)
1496 {
1497
1498 return (uma_zalloc(fpu_save_area_zone, 0));
1499 }
1500
1501 void
1502 fpu_save_area_free(union savefpu *fsa)
1503 {
1504
1505 uma_zfree(fpu_save_area_zone, fsa);
1506 }
1507
1508 void
1509 fpu_save_area_reset(union savefpu *fsa)
1510 {
1511
1512 bcopy(npx_initialstate, fsa, cpu_max_ext_state_size);
1513 }
Cache object: c2c9c05815e0db4bc021e87211695e9c
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