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sys/i386/isa/npx.c
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1 /*- 2 * Copyright (c) 1990 William Jolitz. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by the University of 17 * California, Berkeley and its contributors. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 35 * $FreeBSD$ 36 */ 37 38 #include "opt_cpu.h" 39 #include "opt_debug_npx.h" 40 #include "opt_math_emulate.h" 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/bus.h> 45 #include <sys/kernel.h> 46 #include <sys/malloc.h> 47 #include <sys/module.h> 48 #include <sys/sysctl.h> 49 #include <sys/proc.h> 50 #include <machine/bus.h> 51 #include <sys/rman.h> 52 #ifdef NPX_DEBUG 53 #include <sys/syslog.h> 54 #endif 55 #include <sys/signalvar.h> 56 57 #ifndef SMP 58 #include <machine/asmacros.h> 59 #endif 60 #include <machine/cputypes.h> 61 #include <machine/frame.h> 62 #include <machine/ipl.h> 63 #include <machine/md_var.h> 64 #include <machine/pcb.h> 65 #include <machine/psl.h> 66 #ifndef SMP 67 #include <machine/clock.h> 68 #endif 69 #include <machine/resource.h> 70 #include <machine/specialreg.h> 71 #include <machine/segments.h> 72 73 #ifndef SMP 74 #include <i386/isa/icu.h> 75 #include <i386/isa/intr_machdep.h> 76 #include <i386/isa/isa.h> 77 #endif 78 79 /* 80 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver. 81 */ 82 83 /* Configuration flags. */ 84 #define NPX_DISABLE_I586_OPTIMIZED_BCOPY (1 << 0) 85 #define NPX_DISABLE_I586_OPTIMIZED_BZERO (1 << 1) 86 #define NPX_DISABLE_I586_OPTIMIZED_COPYIO (1 << 2) 87 #define NPX_PREFER_EMULATOR (1 << 3) 88 89 #ifdef __GNUC__ 90 91 #define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr))) 92 #define fnclex() __asm("fnclex") 93 #define fninit() __asm("fninit") 94 #define fnop() __asm("fnop") 95 #define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr))) 96 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 97 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr))) 98 #define fp_divide_by_0() __asm("fldz; fld1; fdiv %st,%st(1); fnop") 99 #define frstor(addr) __asm("frstor %0" : : "m" (*(addr))) 100 #ifdef CPU_ENABLE_SSE 101 #define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr))) 102 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 103 #endif 104 #define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \ 105 : : "n" (CR0_TS) : "ax") 106 #define stop_emulating() __asm("clts") 107 108 #else /* not __GNUC__ */ 109 110 void fldcw __P((caddr_t addr)); 111 void fnclex __P((void)); 112 void fninit __P((void)); 113 void fnop __P((void)); 114 void fnsave __P((caddr_t addr)); 115 void fnstcw __P((caddr_t addr)); 116 void fnstsw __P((caddr_t addr)); 117 void fp_divide_by_0 __P((void)); 118 void frstor __P((caddr_t addr)); 119 #ifdef CPU_ENABLE_SSE 120 void fxsave __P((caddr_t addr)); 121 void fxrstor __P((caddr_t addr)); 122 #endif 123 void start_emulating __P((void)); 124 void stop_emulating __P((void)); 125 126 #endif /* __GNUC__ */ 127 128 #ifdef CPU_ENABLE_SSE 129 #define GET_FPU_EXSW_PTR(pcb) \ 130 (cpu_fxsr ? \ 131 &(pcb)->pcb_save.sv_xmm.sv_ex_sw : \ 132 &(pcb)->pcb_save.sv_87.sv_ex_sw) 133 #else /* CPU_ENABLE_SSE */ 134 #define GET_FPU_EXSW_PTR(pcb) \ 135 (&(pcb)->pcb_save.sv_87.sv_ex_sw) 136 #endif /* CPU_ENABLE_SSE */ 137 138 typedef u_char bool_t; 139 140 #ifdef CPU_ENABLE_SSE 141 static void fpu_clean_state(void); 142 #endif 143 144 static int npx_attach __P((device_t dev)); 145 void npx_intr __P((void *)); 146 static void npx_identify __P((driver_t *driver, device_t parent)); 147 static int npx_probe __P((device_t dev)); 148 static int npx_probe1 __P((device_t dev)); 149 static void fpusave __P((union savefpu *)); 150 static void fpurstor __P((union savefpu *)); 151 #ifdef I586_CPU 152 static long timezero __P((const char *funcname, 153 void (*func)(void *buf, size_t len))); 154 #endif /* I586_CPU */ 155 156 int hw_float; /* XXX currently just alias for npx_exists */ 157 158 SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint, 159 CTLFLAG_RD, &hw_float, 0, 160 "Floatingpoint instructions executed in hardware"); 161 162 #ifndef SMP 163 static u_int npx0_imask = SWI_CLOCK_MASK; 164 static struct gate_descriptor npx_idt_probeintr; 165 static int npx_intrno; 166 static volatile u_int npx_intrs_while_probing; 167 static volatile u_int npx_traps_while_probing; 168 #endif 169 170 static bool_t npx_ex16; 171 static bool_t npx_exists; 172 static bool_t npx_irq13; 173 static int npx_irq; /* irq number */ 174 175 #ifndef SMP 176 /* 177 * Special interrupt handlers. Someday intr0-intr15 will be used to count 178 * interrupts. We'll still need a special exception 16 handler. The busy 179 * latch stuff in probeintr() can be moved to npxprobe(). 180 */ 181 inthand_t probeintr; 182 __asm(" \n\ 183 .text \n\ 184 .p2align 2,0x90 \n\ 185 .type " __XSTRING(CNAME(probeintr)) ",@function \n\ 186 " __XSTRING(CNAME(probeintr)) ": \n\ 187 ss \n\ 188 incl " __XSTRING(CNAME(npx_intrs_while_probing)) " \n\ 189 pushl %eax \n\ 190 movb $0x20,%al # EOI (asm in strings loses cpp features) \n\ 191 outb %al,$0xa0 # IO_ICU2 \n\ 192 outb %al,$0x20 # IO_ICU1 \n\ 193 movb $0,%al \n\ 194 outb %al,$0xf0 # clear BUSY# latch \n\ 195 popl %eax \n\ 196 iret \n\ 197 "); 198 199 inthand_t probetrap; 200 __asm(" \n\ 201 .text \n\ 202 .p2align 2,0x90 \n\ 203 .type " __XSTRING(CNAME(probetrap)) ",@function \n\ 204 " __XSTRING(CNAME(probetrap)) ": \n\ 205 ss \n\ 206 incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\ 207 fnclex \n\ 208 iret \n\ 209 "); 210 #endif /* SMP */ 211 212 /* 213 * Identify routine. Create a connection point on our parent for probing. 214 */ 215 static void 216 npx_identify(driver, parent) 217 driver_t *driver; 218 device_t parent; 219 { 220 device_t child; 221 222 child = BUS_ADD_CHILD(parent, 0, "npx", 0); 223 if (child == NULL) 224 panic("npx_identify"); 225 } 226 227 /* 228 * Probe routine. Initialize cr0 to give correct behaviour for [f]wait 229 * whether the device exists or not (XXX should be elsewhere). Set flags 230 * to tell npxattach() what to do. Modify device struct if npx doesn't 231 * need to use interrupts. Return 1 if device exists. 232 */ 233 static int 234 npx_probe(dev) 235 device_t dev; 236 { 237 #ifdef SMP 238 239 if (resource_int_value("npx", 0, "irq", &npx_irq) != 0) 240 npx_irq = 13; 241 return npx_probe1(dev); 242 243 #else /* SMP */ 244 245 int result; 246 u_long save_eflags; 247 u_char save_icu1_mask; 248 u_char save_icu2_mask; 249 struct gate_descriptor save_idt_npxintr; 250 struct gate_descriptor save_idt_npxtrap; 251 /* 252 * This routine is now just a wrapper for npxprobe1(), to install 253 * special npx interrupt and trap handlers, to enable npx interrupts 254 * and to disable other interrupts. Someday isa_configure() will 255 * install suitable handlers and run with interrupts enabled so we 256 * won't need to do so much here. 257 */ 258 if (resource_int_value("npx", 0, "irq", &npx_irq) != 0) 259 npx_irq = 13; 260 npx_intrno = NRSVIDT + npx_irq; 261 save_eflags = read_eflags(); 262 disable_intr(); 263 save_icu1_mask = inb(IO_ICU1 + 1); 264 save_icu2_mask = inb(IO_ICU2 + 1); 265 save_idt_npxintr = idt[npx_intrno]; 266 save_idt_npxtrap = idt[16]; 267 outb(IO_ICU1 + 1, ~IRQ_SLAVE); 268 outb(IO_ICU2 + 1, ~(1 << (npx_irq - 8))); 269 setidt(16, probetrap, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 270 setidt(npx_intrno, probeintr, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 271 npx_idt_probeintr = idt[npx_intrno]; 272 enable_intr(); 273 result = npx_probe1(dev); 274 disable_intr(); 275 outb(IO_ICU1 + 1, save_icu1_mask); 276 outb(IO_ICU2 + 1, save_icu2_mask); 277 idt[npx_intrno] = save_idt_npxintr; 278 idt[16] = save_idt_npxtrap; 279 write_eflags(save_eflags); 280 return (result); 281 282 #endif /* SMP */ 283 } 284 285 static int 286 npx_probe1(dev) 287 device_t dev; 288 { 289 #ifndef SMP 290 u_short control; 291 u_short status; 292 #endif 293 294 /* 295 * Partially reset the coprocessor, if any. Some BIOS's don't reset 296 * it after a warm boot. 297 */ 298 outb(0xf1, 0); /* full reset on some systems, NOP on others */ 299 outb(0xf0, 0); /* clear BUSY# latch */ 300 /* 301 * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT 302 * instructions. We must set the CR0_MP bit and use the CR0_TS 303 * bit to control the trap, because setting the CR0_EM bit does 304 * not cause WAIT instructions to trap. It's important to trap 305 * WAIT instructions - otherwise the "wait" variants of no-wait 306 * control instructions would degenerate to the "no-wait" variants 307 * after FP context switches but work correctly otherwise. It's 308 * particularly important to trap WAITs when there is no NPX - 309 * otherwise the "wait" variants would always degenerate. 310 * 311 * Try setting CR0_NE to get correct error reporting on 486DX's. 312 * Setting it should fail or do nothing on lesser processors. 313 */ 314 load_cr0(rcr0() | CR0_MP | CR0_NE); 315 /* 316 * But don't trap while we're probing. 317 */ 318 stop_emulating(); 319 /* 320 * Finish resetting the coprocessor, if any. If there is an error 321 * pending, then we may get a bogus IRQ13, but probeintr() will handle 322 * it OK. Bogus halts have never been observed, but we enabled 323 * IRQ13 and cleared the BUSY# latch early to handle them anyway. 324 */ 325 fninit(); 326 327 #ifdef SMP 328 /* 329 * Exception 16 MUST work for SMP. 330 */ 331 npx_irq13 = 0; 332 npx_ex16 = hw_float = npx_exists = 1; 333 device_set_desc(dev, "math processor"); 334 return (0); 335 336 #else /* !SMP */ 337 device_set_desc(dev, "math processor"); 338 339 /* 340 * Don't use fwait here because it might hang. 341 * Don't use fnop here because it usually hangs if there is no FPU. 342 */ 343 DELAY(1000); /* wait for any IRQ13 */ 344 #ifdef DIAGNOSTIC 345 if (npx_intrs_while_probing != 0) 346 printf("fninit caused %u bogus npx interrupt(s)\n", 347 npx_intrs_while_probing); 348 if (npx_traps_while_probing != 0) 349 printf("fninit caused %u bogus npx trap(s)\n", 350 npx_traps_while_probing); 351 #endif 352 /* 353 * Check for a status of mostly zero. 354 */ 355 status = 0x5a5a; 356 fnstsw(&status); 357 if ((status & 0xb8ff) == 0) { 358 /* 359 * Good, now check for a proper control word. 360 */ 361 control = 0x5a5a; 362 fnstcw(&control); 363 if ((control & 0x1f3f) == 0x033f) { 364 hw_float = npx_exists = 1; 365 /* 366 * We have an npx, now divide by 0 to see if exception 367 * 16 works. 368 */ 369 control &= ~(1 << 2); /* enable divide by 0 trap */ 370 fldcw(&control); 371 npx_traps_while_probing = npx_intrs_while_probing = 0; 372 fp_divide_by_0(); 373 if (npx_traps_while_probing != 0) { 374 /* 375 * Good, exception 16 works. 376 */ 377 npx_ex16 = 1; 378 return (0); 379 } 380 if (npx_intrs_while_probing != 0) { 381 int rid; 382 struct resource *r; 383 void *intr; 384 /* 385 * Bad, we are stuck with IRQ13. 386 */ 387 npx_irq13 = 1; 388 /* 389 * npxattach would be too late to set npx0_imask 390 */ 391 npx0_imask |= (1 << npx_irq); 392 393 /* 394 * We allocate these resources permanently, 395 * so there is no need to keep track of them. 396 */ 397 rid = 0; 398 r = bus_alloc_resource(dev, SYS_RES_IOPORT, 399 &rid, IO_NPX, IO_NPX, 400 IO_NPXSIZE, RF_ACTIVE); 401 if (r == 0) 402 panic("npx: can't get ports"); 403 rid = 0; 404 r = bus_alloc_resource(dev, SYS_RES_IRQ, 405 &rid, npx_irq, npx_irq, 406 1, RF_ACTIVE); 407 if (r == 0) 408 panic("npx: can't get IRQ"); 409 BUS_SETUP_INTR(device_get_parent(dev), 410 dev, r, INTR_TYPE_MISC, 411 npx_intr, 0, &intr); 412 if (intr == 0) 413 panic("npx: can't create intr"); 414 415 return (0); 416 } 417 /* 418 * Worse, even IRQ13 is broken. Use emulator. 419 */ 420 } 421 } 422 /* 423 * Probe failed, but we want to get to npxattach to initialize the 424 * emulator and say that it has been installed. XXX handle devices 425 * that aren't really devices better. 426 */ 427 return (0); 428 #endif /* SMP */ 429 } 430 431 /* 432 * Attach routine - announce which it is, and wire into system 433 */ 434 int 435 npx_attach(dev) 436 device_t dev; 437 { 438 int flags; 439 440 if (resource_int_value("npx", 0, "flags", &flags) != 0) 441 flags = 0; 442 443 if (flags) 444 device_printf(dev, "flags 0x%x ", flags); 445 if (npx_irq13) { 446 device_printf(dev, "using IRQ 13 interface\n"); 447 } else { 448 #if defined(MATH_EMULATE) || defined(GPL_MATH_EMULATE) 449 if (npx_ex16) { 450 if (!(flags & NPX_PREFER_EMULATOR)) 451 device_printf(dev, "INT 16 interface\n"); 452 else { 453 device_printf(dev, "FPU exists, but flags request " 454 "emulator\n"); 455 hw_float = npx_exists = 0; 456 } 457 } else if (npx_exists) { 458 device_printf(dev, "error reporting broken; using 387 emulator\n"); 459 hw_float = npx_exists = 0; 460 } else 461 device_printf(dev, "387 emulator\n"); 462 #else 463 if (npx_ex16) { 464 device_printf(dev, "INT 16 interface\n"); 465 if (flags & NPX_PREFER_EMULATOR) { 466 device_printf(dev, "emulator requested, but none compiled " 467 "into kernel, using FPU\n"); 468 } 469 } else 470 device_printf(dev, "no 387 emulator in kernel and no FPU!\n"); 471 #endif 472 } 473 npxinit(__INITIAL_NPXCW__); 474 475 #ifdef I586_CPU 476 if (cpu_class == CPUCLASS_586 && npx_ex16 && npx_exists && 477 timezero("i586_bzero()", i586_bzero) < 478 timezero("bzero()", bzero) * 4 / 5) { 479 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY)) { 480 bcopy_vector = i586_bcopy; 481 ovbcopy_vector = i586_bcopy; 482 } 483 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BZERO)) 484 bzero = i586_bzero; 485 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_COPYIO)) { 486 copyin_vector = i586_copyin; 487 copyout_vector = i586_copyout; 488 } 489 } 490 #endif 491 492 return (0); /* XXX unused */ 493 } 494 495 /* 496 * Initialize floating point unit. 497 */ 498 void 499 npxinit(control) 500 u_short control; 501 { 502 static union savefpu dummy; 503 504 if (!npx_exists) 505 return; 506 /* 507 * fninit has the same h/w bugs as fnsave. Use the detoxified 508 * fnsave to throw away any junk in the fpu. npxsave() initializes 509 * the fpu and sets npxproc = NULL as important side effects. 510 */ 511 npxsave(&dummy); 512 stop_emulating(); 513 #ifdef CPU_ENABLE_SSE 514 /* XXX npxsave() doesn't actually initialize the fpu in the SSE case. */ 515 if (cpu_fxsr) 516 fninit(); 517 #endif 518 fldcw(&control); 519 if (curpcb != NULL) 520 fpusave(&curpcb->pcb_save); 521 start_emulating(); 522 } 523 524 /* 525 * Free coprocessor (if we have it). 526 */ 527 void 528 npxexit(p) 529 struct proc *p; 530 { 531 532 if (p == npxproc) 533 npxsave(&curpcb->pcb_save); 534 #ifdef NPX_DEBUG 535 if (npx_exists) { 536 u_int masked_exceptions; 537 538 masked_exceptions = curpcb->pcb_save.sv_87.sv_env.en_cw 539 & curpcb->pcb_save.sv_87.sv_env.en_sw & 0x7f; 540 /* 541 * Log exceptions that would have trapped with the old 542 * control word (overflow, divide by 0, and invalid operand). 543 */ 544 if (masked_exceptions & 0x0d) 545 log(LOG_ERR, 546 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n", 547 p->p_pid, p->p_comm, masked_exceptions); 548 } 549 #endif 550 } 551 552 /* 553 * The following mechanism is used to ensure that the FPE_... value 554 * that is passed as a trapcode to the signal handler of the user 555 * process does not have more than one bit set. 556 * 557 * Multiple bits may be set if the user process modifies the control 558 * word while a status word bit is already set. While this is a sign 559 * of bad coding, we have no choise than to narrow them down to one 560 * bit, since we must not send a trapcode that is not exactly one of 561 * the FPE_ macros. 562 * 563 * The mechanism has a static table with 127 entries. Each combination 564 * of the 7 FPU status word exception bits directly translates to a 565 * position in this table, where a single FPE_... value is stored. 566 * This FPE_... value stored there is considered the "most important" 567 * of the exception bits and will be sent as the signal code. The 568 * precedence of the bits is based upon Intel Document "Numerical 569 * Applications", Chapter "Special Computational Situations". 570 * 571 * The macro to choose one of these values does these steps: 1) Throw 572 * away status word bits that cannot be masked. 2) Throw away the bits 573 * currently masked in the control word, assuming the user isn't 574 * interested in them anymore. 3) Reinsert status word bit 7 (stack 575 * fault) if it is set, which cannot be masked but must be presered. 576 * 4) Use the remaining bits to point into the trapcode table. 577 * 578 * The 6 maskable bits in order of their preference, as stated in the 579 * above referenced Intel manual: 580 * 1 Invalid operation (FP_X_INV) 581 * 1a Stack underflow 582 * 1b Stack overflow 583 * 1c Operand of unsupported format 584 * 1d SNaN operand. 585 * 2 QNaN operand (not an exception, irrelavant here) 586 * 3 Any other invalid-operation not mentioned above or zero divide 587 * (FP_X_INV, FP_X_DZ) 588 * 4 Denormal operand (FP_X_DNML) 589 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 590 * 6 Inexact result (FP_X_IMP) 591 */ 592 static char fpetable[128] = { 593 0, 594 FPE_FLTINV, /* 1 - INV */ 595 FPE_FLTUND, /* 2 - DNML */ 596 FPE_FLTINV, /* 3 - INV | DNML */ 597 FPE_FLTDIV, /* 4 - DZ */ 598 FPE_FLTINV, /* 5 - INV | DZ */ 599 FPE_FLTDIV, /* 6 - DNML | DZ */ 600 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 601 FPE_FLTOVF, /* 8 - OFL */ 602 FPE_FLTINV, /* 9 - INV | OFL */ 603 FPE_FLTUND, /* A - DNML | OFL */ 604 FPE_FLTINV, /* B - INV | DNML | OFL */ 605 FPE_FLTDIV, /* C - DZ | OFL */ 606 FPE_FLTINV, /* D - INV | DZ | OFL */ 607 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 608 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 609 FPE_FLTUND, /* 10 - UFL */ 610 FPE_FLTINV, /* 11 - INV | UFL */ 611 FPE_FLTUND, /* 12 - DNML | UFL */ 612 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 613 FPE_FLTDIV, /* 14 - DZ | UFL */ 614 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 615 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 616 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 617 FPE_FLTOVF, /* 18 - OFL | UFL */ 618 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 619 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 620 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 621 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 622 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 623 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 624 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 625 FPE_FLTRES, /* 20 - IMP */ 626 FPE_FLTINV, /* 21 - INV | IMP */ 627 FPE_FLTUND, /* 22 - DNML | IMP */ 628 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 629 FPE_FLTDIV, /* 24 - DZ | IMP */ 630 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 631 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 632 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 633 FPE_FLTOVF, /* 28 - OFL | IMP */ 634 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 635 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 636 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 637 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 638 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 639 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 640 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 641 FPE_FLTUND, /* 30 - UFL | IMP */ 642 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 643 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 644 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 645 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 646 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 647 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 648 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 649 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 650 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 651 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 652 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 653 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 654 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 655 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 656 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 657 FPE_FLTSUB, /* 40 - STK */ 658 FPE_FLTSUB, /* 41 - INV | STK */ 659 FPE_FLTUND, /* 42 - DNML | STK */ 660 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 661 FPE_FLTDIV, /* 44 - DZ | STK */ 662 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 663 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 664 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 665 FPE_FLTOVF, /* 48 - OFL | STK */ 666 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 667 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 668 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 669 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 670 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 671 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 672 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 673 FPE_FLTUND, /* 50 - UFL | STK */ 674 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 675 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 676 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 677 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 678 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 679 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 680 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 681 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 682 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 683 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 684 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 685 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 686 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 687 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 688 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 689 FPE_FLTRES, /* 60 - IMP | STK */ 690 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 691 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 692 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 693 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 694 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 695 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 696 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 697 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 698 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 699 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 700 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 701 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 702 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 703 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 704 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 705 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 706 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 707 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 708 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 709 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 710 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 711 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 712 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 713 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 714 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 715 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 716 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 717 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 718 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 719 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 720 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 721 }; 722 723 /* 724 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE. 725 * 726 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now 727 * depend on longjmp() restoring a usable state. Restoring the state 728 * or examining it might fail if we didn't clear exceptions. 729 * 730 * The error code chosen will be one of the FPE_... macros. It will be 731 * sent as the second argument to old BSD-style signal handlers and as 732 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers. 733 * 734 * XXX the FP state is not preserved across signal handlers. So signal 735 * handlers cannot afford to do FP unless they preserve the state or 736 * longjmp() out. Both preserving the state and longjmp()ing may be 737 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable 738 * solution for signals other than SIGFPE. 739 */ 740 void 741 npx_intr(dummy) 742 void *dummy; 743 { 744 int code; 745 u_short control; 746 struct intrframe *frame; 747 u_long *exstat; 748 749 if (npxproc == NULL || !npx_exists) { 750 printf("npxintr: npxproc = %p, curproc = %p, npx_exists = %d\n", 751 npxproc, curproc, npx_exists); 752 panic("npxintr from nowhere"); 753 } 754 if (npxproc != curproc) { 755 printf("npxintr: npxproc = %p, curproc = %p, npx_exists = %d\n", 756 npxproc, curproc, npx_exists); 757 panic("npxintr from non-current process"); 758 } 759 760 exstat = GET_FPU_EXSW_PTR(curpcb); 761 outb(0xf0, 0); 762 fnstsw(exstat); 763 fnstcw(&control); 764 fnclex(); 765 766 /* 767 * Pass exception to process. 768 */ 769 frame = (struct intrframe *)&dummy; /* XXX */ 770 if ((ISPL(frame->if_cs) == SEL_UPL) || (frame->if_eflags & PSL_VM)) { 771 /* 772 * Interrupt is essentially a trap, so we can afford to call 773 * the SIGFPE handler (if any) as soon as the interrupt 774 * returns. 775 * 776 * XXX little or nothing is gained from this, and plenty is 777 * lost - the interrupt frame has to contain the trap frame 778 * (this is otherwise only necessary for the rescheduling trap 779 * in doreti, and the frame for that could easily be set up 780 * just before it is used). 781 */ 782 curproc->p_md.md_regs = INTR_TO_TRAPFRAME(frame); 783 /* 784 * Encode the appropriate code for detailed information on 785 * this exception. 786 */ 787 code = 788 fpetable[(*exstat & ~control & 0x3f) | (*exstat & 0x40)]; 789 trapsignal(curproc, SIGFPE, code); 790 } else { 791 /* 792 * Nested interrupt. These losers occur when: 793 * o an IRQ13 is bogusly generated at a bogus time, e.g.: 794 * o immediately after an fnsave or frstor of an 795 * error state. 796 * o a couple of 386 instructions after 797 * "fstpl _memvar" causes a stack overflow. 798 * These are especially nasty when combined with a 799 * trace trap. 800 * o an IRQ13 occurs at the same time as another higher- 801 * priority interrupt. 802 * 803 * Treat them like a true async interrupt. 804 */ 805 psignal(curproc, SIGFPE); 806 } 807 } 808 809 /* 810 * Implement device not available (DNA) exception 811 * 812 * It would be better to switch FP context here (if curproc != npxproc) 813 * and not necessarily for every context switch, but it is too hard to 814 * access foreign pcb's. 815 */ 816 int 817 npxdna() 818 { 819 u_long *exstat; 820 821 if (!npx_exists) 822 return (0); 823 if (npxproc != NULL) { 824 printf("npxdna: npxproc = %p, curproc = %p\n", 825 npxproc, curproc); 826 panic("npxdna"); 827 } 828 stop_emulating(); 829 /* 830 * Record new context early in case frstor causes an IRQ13. 831 */ 832 npxproc = curproc; 833 exstat = GET_FPU_EXSW_PTR(curpcb); 834 *exstat = 0; 835 /* 836 * The following frstor may cause an IRQ13 when the state being 837 * restored has a pending error. The error will appear to have been 838 * triggered by the current (npx) user instruction even when that 839 * instruction is a no-wait instruction that should not trigger an 840 * error (e.g., fnclex). On at least one 486 system all of the 841 * no-wait instructions are broken the same as frstor, so our 842 * treatment does not amplify the breakage. On at least one 843 * 386/Cyrix 387 system, fnclex works correctly while frstor and 844 * fnsave are broken, so our treatment breaks fnclex if it is the 845 * first FPU instruction after a context switch. 846 */ 847 fpurstor(&curpcb->pcb_save); 848 849 return (1); 850 } 851 852 /* 853 * Wrapper for fnsave instruction to handle h/w bugs. If there is an error 854 * pending, then fnsave generates a bogus IRQ13 on some systems. Force 855 * any IRQ13 to be handled immediately, and then ignore it. This routine is 856 * often called at splhigh so it must not use many system services. In 857 * particular, it's much easier to install a special handler than to 858 * guarantee that it's safe to use npxintr() and its supporting code. 859 */ 860 void 861 npxsave(addr) 862 union savefpu *addr; 863 { 864 #if defined(SMP) || defined(CPU_ENABLE_SSE) 865 866 stop_emulating(); 867 fpusave(addr); 868 869 /* fnop(); */ 870 start_emulating(); 871 npxproc = NULL; 872 873 #else /* SMP or CPU_ENABLE_SSE */ 874 875 u_char icu1_mask; 876 u_char icu2_mask; 877 u_char old_icu1_mask; 878 u_char old_icu2_mask; 879 struct gate_descriptor save_idt_npxintr; 880 881 disable_intr(); 882 old_icu1_mask = inb(IO_ICU1 + 1); 883 old_icu2_mask = inb(IO_ICU2 + 1); 884 save_idt_npxintr = idt[npx_intrno]; 885 outb(IO_ICU1 + 1, old_icu1_mask & ~(IRQ_SLAVE | npx0_imask)); 886 outb(IO_ICU2 + 1, old_icu2_mask & ~(npx0_imask >> 8)); 887 idt[npx_intrno] = npx_idt_probeintr; 888 enable_intr(); 889 stop_emulating(); 890 fnsave(addr); 891 fnop(); 892 start_emulating(); 893 npxproc = NULL; 894 disable_intr(); 895 icu1_mask = inb(IO_ICU1 + 1); /* masks may have changed */ 896 icu2_mask = inb(IO_ICU2 + 1); 897 outb(IO_ICU1 + 1, 898 (icu1_mask & ~npx0_imask) | (old_icu1_mask & npx0_imask)); 899 outb(IO_ICU2 + 1, 900 (icu2_mask & ~(npx0_imask >> 8)) 901 | (old_icu2_mask & (npx0_imask >> 8))); 902 idt[npx_intrno] = save_idt_npxintr; 903 enable_intr(); /* back to usual state */ 904 905 #endif /* SMP */ 906 } 907 908 static void 909 fpusave(addr) 910 union savefpu *addr; 911 { 912 913 #ifdef CPU_ENABLE_SSE 914 if (cpu_fxsr) 915 fxsave(addr); 916 else 917 #endif 918 fnsave(addr); 919 } 920 921 #ifdef CPU_ENABLE_SSE 922 /* 923 * On AuthenticAMD processors, the fxrstor instruction does not restore 924 * the x87's stored last instruction pointer, last data pointer, and last 925 * opcode values, except in the rare case in which the exception summary 926 * (ES) bit in the x87 status word is set to 1. 927 * 928 * In order to avoid leaking this information across processes, we clean 929 * these values by performing a dummy load before executing fxrstor(). 930 */ 931 static double dummy_variable = 0.0; 932 static void 933 fpu_clean_state(void) 934 { 935 u_short status; 936 937 /* 938 * Clear the ES bit in the x87 status word if it is currently 939 * set, in order to avoid causing a fault in the upcoming load. 940 */ 941 fnstsw(&status); 942 if (status & 0x80) 943 fnclex(); 944 945 /* 946 * Load the dummy variable into the x87 stack. This mangles 947 * the x87 stack, but we don't care since we're about to call 948 * fxrstor() anyway. 949 */ 950 __asm __volatile("ffree %%st(7); fld %0" : : "m" (dummy_variable)); 951 } 952 #endif /* CPU_ENABLE_SSE */ 953 954 static void 955 fpurstor(addr) 956 union savefpu *addr; 957 { 958 959 #ifdef CPU_ENABLE_SSE 960 if (cpu_fxsr) { 961 fpu_clean_state(); 962 fxrstor(addr); 963 } else 964 #endif 965 frstor(addr); 966 } 967 968 #ifdef I586_CPU 969 static long 970 timezero(funcname, func) 971 const char *funcname; 972 void (*func) __P((void *buf, size_t len)); 973 974 { 975 void *buf; 976 #define BUFSIZE 1000000 977 long usec; 978 struct timeval finish, start; 979 980 buf = malloc(BUFSIZE, M_TEMP, M_NOWAIT); 981 if (buf == NULL) 982 return (BUFSIZE); 983 microtime(&start); 984 (*func)(buf, BUFSIZE); 985 microtime(&finish); 986 usec = 1000000 * (finish.tv_sec - start.tv_sec) + 987 finish.tv_usec - start.tv_usec; 988 if (usec <= 0) 989 usec = 1; 990 if (bootverbose) 991 printf("%s bandwidth = %ld bytes/sec\n", 992 funcname, (long)(BUFSIZE * (int64_t)1000000 / usec)); 993 free(buf, M_TEMP); 994 return (usec); 995 } 996 #endif /* I586_CPU */ 997 998 static device_method_t npx_methods[] = { 999 /* Device interface */ 1000 DEVMETHOD(device_identify, npx_identify), 1001 DEVMETHOD(device_probe, npx_probe), 1002 DEVMETHOD(device_attach, npx_attach), 1003 DEVMETHOD(device_detach, bus_generic_detach), 1004 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1005 DEVMETHOD(device_suspend, bus_generic_suspend), 1006 DEVMETHOD(device_resume, bus_generic_resume), 1007 1008 { 0, 0 } 1009 }; 1010 1011 static driver_t npx_driver = { 1012 "npx", 1013 npx_methods, 1014 1, /* no softc */ 1015 }; 1016 1017 static devclass_t npx_devclass; 1018 1019 /* 1020 * We prefer to attach to the root nexus so that the usual case (exception 16) 1021 * doesn't describe the processor as being `on isa'. 1022 */ 1023 DRIVER_MODULE(npx, nexus, npx_driver, npx_devclass, 0, 0);
Cache object: 10c8acff91d844e8b2034a27c7df9322
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