The Design and Implementation of the FreeBSD Operating System, Second Edition
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sys/i386/isa/npx.c

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    1 /*-
    2  * Copyright (c) 1990 William Jolitz.
    3  * Copyright (c) 1991 The Regents of the University of California.
    4  * All rights reserved.
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions
    8  * are met:
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  * 4. Neither the name of the University nor the names of its contributors
   15  *    may be used to endorse or promote products derived from this software
   16  *    without specific prior written permission.
   17  *
   18  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   28  * SUCH DAMAGE.
   29  *
   30  *      from: @(#)npx.c 7.2 (Berkeley) 5/12/91
   31  */
   32 
   33 #include <sys/cdefs.h>
   34 __FBSDID("$FreeBSD: releng/5.4/sys/i386/isa/npx.c 157863 2006-04-19 07:03:14Z cperciva $");
   35 
   36 #include "opt_cpu.h"
   37 #include "opt_debug_npx.h"
   38 #include "opt_isa.h"
   39 #include "opt_npx.h"
   40 
   41 #include <sys/param.h>
   42 #include <sys/systm.h>
   43 #include <sys/bus.h>
   44 #include <sys/kernel.h>
   45 #include <sys/lock.h>
   46 #include <sys/malloc.h>
   47 #include <sys/module.h>
   48 #include <sys/mutex.h>
   49 #include <sys/mutex.h>
   50 #include <sys/proc.h>
   51 #include <sys/smp.h>
   52 #include <sys/sysctl.h>
   53 #include <machine/bus.h>
   54 #include <sys/rman.h>
   55 #ifdef NPX_DEBUG
   56 #include <sys/syslog.h>
   57 #endif
   58 #include <sys/signalvar.h>
   59 
   60 #include <machine/asmacros.h>
   61 #include <machine/cputypes.h>
   62 #include <machine/frame.h>
   63 #include <machine/md_var.h>
   64 #include <machine/pcb.h>
   65 #include <machine/psl.h>
   66 #include <machine/clock.h>
   67 #include <machine/resource.h>
   68 #include <machine/specialreg.h>
   69 #include <machine/segments.h>
   70 #include <machine/ucontext.h>
   71 
   72 #ifdef PC98
   73 #include <pc98/pc98/pc98.h>
   74 #else
   75 #include <i386/isa/isa.h>
   76 #endif
   77 #include <machine/intr_machdep.h>
   78 #ifdef DEV_ISA
   79 #include <isa/isavar.h>
   80 #endif
   81 
   82 #if !defined(CPU_ENABLE_SSE) && defined(I686_CPU)
   83 #define CPU_ENABLE_SSE
   84 #endif
   85 #if defined(CPU_DISABLE_SSE)
   86 #undef CPU_ENABLE_SSE
   87 #endif
   88 
   89 /*
   90  * 387 and 287 Numeric Coprocessor Extension (NPX) Driver.
   91  */
   92 
   93 /* Configuration flags. */
   94 #define NPX_DISABLE_I586_OPTIMIZED_BCOPY        (1 << 0)
   95 #define NPX_DISABLE_I586_OPTIMIZED_BZERO        (1 << 1)
   96 #define NPX_DISABLE_I586_OPTIMIZED_COPYIO       (1 << 2)
   97 
   98 #if (defined(__GNUC__) && !defined(lint)) || defined(__INTEL_COMPILER)
   99 
  100 #define fldcw(addr)             __asm("fldcw %0" : : "m" (*(addr)))
  101 #define fnclex()                __asm("fnclex")
  102 #define fninit()                __asm("fninit")
  103 #define fnsave(addr)            __asm __volatile("fnsave %0" : "=m" (*(addr)))
  104 #define fnstcw(addr)            __asm __volatile("fnstcw %0" : "=m" (*(addr)))
  105 #define fnstsw(addr)            __asm __volatile("fnstsw %0" : "=m" (*(addr)))
  106 #define fp_divide_by_0()        __asm("fldz; fld1; fdiv %st,%st(1); fnop")
  107 #define frstor(addr)            __asm("frstor %0" : : "m" (*(addr)))
  108 #ifdef CPU_ENABLE_SSE
  109 #define fxrstor(addr)           __asm("fxrstor %0" : : "m" (*(addr)))
  110 #define fxsave(addr)            __asm __volatile("fxsave %0" : "=m" (*(addr)))
  111 #define ldmxcsr(__csr)          __asm __volatile("ldmxcsr %0" : : "m" (__csr))
  112 #endif
  113 #define start_emulating()       __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \
  114                                       : : "n" (CR0_TS) : "ax")
  115 #define stop_emulating()        __asm("clts")
  116 
  117 #else   /* !((__GNUC__ && !lint ) || __INTEL_COMPILER) */
  118 
  119 void    fldcw(caddr_t addr);
  120 void    fnclex(void);
  121 void    fninit(void);
  122 void    fnsave(caddr_t addr);
  123 void    fnstcw(caddr_t addr);
  124 void    fnstsw(caddr_t addr);
  125 void    fp_divide_by_0(void);
  126 void    frstor(caddr_t addr);
  127 #ifdef CPU_ENABLE_SSE
  128 void    fxsave(caddr_t addr);
  129 void    fxrstor(caddr_t addr);
  130 #endif
  131 void    start_emulating(void);
  132 void    stop_emulating(void);
  133 
  134 #endif  /* (__GNUC__ && !lint ) || __INTEL_COMPILER */
  135 
  136 #ifdef CPU_ENABLE_SSE
  137 #define GET_FPU_CW(thread) \
  138         (cpu_fxsr ? \
  139                 (thread)->td_pcb->pcb_save.sv_xmm.sv_env.en_cw : \
  140                 (thread)->td_pcb->pcb_save.sv_87.sv_env.en_cw)
  141 #define GET_FPU_SW(thread) \
  142         (cpu_fxsr ? \
  143                 (thread)->td_pcb->pcb_save.sv_xmm.sv_env.en_sw : \
  144                 (thread)->td_pcb->pcb_save.sv_87.sv_env.en_sw)
  145 #else /* CPU_ENABLE_SSE */
  146 #define GET_FPU_CW(thread) \
  147         (thread->td_pcb->pcb_save.sv_87.sv_env.en_cw)
  148 #define GET_FPU_SW(thread) \
  149         (thread->td_pcb->pcb_save.sv_87.sv_env.en_sw)
  150 #endif /* CPU_ENABLE_SSE */
  151 
  152 typedef u_char bool_t;
  153 
  154 #ifdef CPU_ENABLE_SSE
  155 static  void    fpu_clean_state(void);
  156 #endif
  157 
  158 static  void    fpusave(union savefpu *);
  159 static  void    fpurstor(union savefpu *);
  160 static  int     npx_attach(device_t dev);
  161 static  void    npx_identify(driver_t *driver, device_t parent);
  162 static  void    npx_intr(void *);
  163 static  int     npx_probe(device_t dev);
  164 #ifdef I586_CPU_XXX
  165 static  long    timezero(const char *funcname,
  166                     void (*func)(void *buf, size_t len));
  167 #endif /* I586_CPU */
  168 
  169 int     hw_float;               /* XXX currently just alias for npx_exists */
  170 
  171 SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint,
  172         CTLFLAG_RD, &hw_float, 0, 
  173         "Floatingpoint instructions executed in hardware");
  174 
  175 static  volatile u_int          npx_intrs_while_probing;
  176 static  volatile u_int          npx_traps_while_probing;
  177 
  178 static  union savefpu           npx_cleanstate;
  179 static  bool_t                  npx_cleanstate_ready;
  180 static  bool_t                  npx_ex16;
  181 static  bool_t                  npx_exists;
  182 static  bool_t                  npx_irq13;
  183 
  184 alias_for_inthand_t probetrap;
  185 __asm("                                                         \n\
  186         .text                                                   \n\
  187         .p2align 2,0x90                                         \n\
  188         .type   " __XSTRING(CNAME(probetrap)) ",@function       \n\
  189 " __XSTRING(CNAME(probetrap)) ":                                \n\
  190         ss                                                      \n\
  191         incl    " __XSTRING(CNAME(npx_traps_while_probing)) "   \n\
  192         fnclex                                                  \n\
  193         iret                                                    \n\
  194 ");
  195 
  196 /*
  197  * Identify routine.  Create a connection point on our parent for probing.
  198  */
  199 static void
  200 npx_identify(driver, parent)
  201         driver_t *driver;
  202         device_t parent;
  203 {
  204         device_t child;
  205 
  206         child = BUS_ADD_CHILD(parent, 0, "npx", 0);
  207         if (child == NULL)
  208                 panic("npx_identify");
  209 }
  210 
  211 /*
  212  * Do minimal handling of npx interrupts to convert them to traps.
  213  */
  214 static void
  215 npx_intr(dummy)
  216         void *dummy;
  217 {
  218         struct thread *td;
  219 
  220         npx_intrs_while_probing++;
  221 
  222         /*
  223          * The BUSY# latch must be cleared in all cases so that the next
  224          * unmasked npx exception causes an interrupt.
  225          */
  226 #ifdef PC98
  227         outb(0xf8, 0);
  228 #else
  229         outb(0xf0, 0);
  230 #endif
  231 
  232         /*
  233          * fpcurthread is normally non-null here.  In that case, schedule an
  234          * AST to finish the exception handling in the correct context
  235          * (this interrupt may occur after the thread has entered the
  236          * kernel via a syscall or an interrupt).  Otherwise, the npx
  237          * state of the thread that caused this interrupt must have been
  238          * pushed to the thread's pcb, and clearing of the busy latch
  239          * above has finished the (essentially null) handling of this
  240          * interrupt.  Control will eventually return to the instruction
  241          * that caused it and it will repeat.  We will eventually (usually
  242          * soon) win the race to handle the interrupt properly.
  243          */
  244         td = PCPU_GET(fpcurthread);
  245         if (td != NULL) {
  246                 td->td_pcb->pcb_flags |= PCB_NPXTRAP;
  247                 mtx_lock_spin(&sched_lock);
  248                 td->td_flags |= TDF_ASTPENDING;
  249                 mtx_unlock_spin(&sched_lock);
  250         }
  251 }
  252 
  253 /*
  254  * Probe routine.  Initialize cr0 to give correct behaviour for [f]wait
  255  * whether the device exists or not (XXX should be elsewhere).  Set flags
  256  * to tell npxattach() what to do.  Modify device struct if npx doesn't
  257  * need to use interrupts.  Return 0 if device exists.
  258  */
  259 static int
  260 npx_probe(dev)
  261         device_t dev;
  262 {
  263         struct gate_descriptor save_idt_npxtrap;
  264         struct resource *ioport_res, *irq_res;
  265         void *irq_cookie;
  266         int ioport_rid, irq_num, irq_rid;
  267         u_short control;
  268         u_short status;
  269 
  270         save_idt_npxtrap = idt[IDT_MF];
  271         setidt(IDT_MF, probetrap, SDT_SYS386TGT, SEL_KPL,
  272             GSEL(GCODE_SEL, SEL_KPL));
  273         ioport_rid = 0;
  274         ioport_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &ioport_rid,
  275             IO_NPX, IO_NPX, IO_NPXSIZE, RF_ACTIVE);
  276         if (ioport_res == NULL)
  277                 panic("npx: can't get ports");
  278 #ifdef PC98
  279         if (resource_int_value("npx", 0, "irq", &irq_num) != 0)
  280                 irq_num = 8;
  281 #else
  282         if (resource_int_value("npx", 0, "irq", &irq_num) != 0)
  283                 irq_num = 13;
  284 #endif
  285         irq_rid = 0;
  286         irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &irq_rid, irq_num,
  287             irq_num, 1, RF_ACTIVE);
  288         if (irq_res == NULL)
  289                 panic("npx: can't get IRQ");
  290         if (bus_setup_intr(dev, irq_res, INTR_TYPE_MISC | INTR_FAST, npx_intr,
  291             NULL, &irq_cookie) != 0)
  292                 panic("npx: can't create intr");
  293 
  294         /*
  295          * Partially reset the coprocessor, if any.  Some BIOS's don't reset
  296          * it after a warm boot.
  297          */
  298 #ifdef PC98
  299         outb(0xf8,0);
  300 #else
  301         outb(0xf1, 0);          /* full reset on some systems, NOP on others */
  302         outb(0xf0, 0);          /* clear BUSY# latch */
  303 #endif
  304         /*
  305          * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT
  306          * instructions.  We must set the CR0_MP bit and use the CR0_TS
  307          * bit to control the trap, because setting the CR0_EM bit does
  308          * not cause WAIT instructions to trap.  It's important to trap
  309          * WAIT instructions - otherwise the "wait" variants of no-wait
  310          * control instructions would degenerate to the "no-wait" variants
  311          * after FP context switches but work correctly otherwise.  It's
  312          * particularly important to trap WAITs when there is no NPX -
  313          * otherwise the "wait" variants would always degenerate.
  314          *
  315          * Try setting CR0_NE to get correct error reporting on 486DX's.
  316          * Setting it should fail or do nothing on lesser processors.
  317          */
  318         load_cr0(rcr0() | CR0_MP | CR0_NE);
  319         /*
  320          * But don't trap while we're probing.
  321          */
  322         stop_emulating();
  323         /*
  324          * Finish resetting the coprocessor, if any.  If there is an error
  325          * pending, then we may get a bogus IRQ13, but npx_intr() will handle
  326          * it OK.  Bogus halts have never been observed, but we enabled
  327          * IRQ13 and cleared the BUSY# latch early to handle them anyway.
  328          */
  329         fninit();
  330 
  331         device_set_desc(dev, "math processor");
  332 
  333         /*
  334          * Don't use fwait here because it might hang.
  335          * Don't use fnop here because it usually hangs if there is no FPU.
  336          */
  337         DELAY(1000);            /* wait for any IRQ13 */
  338 #ifdef DIAGNOSTIC
  339         if (npx_intrs_while_probing != 0)
  340                 printf("fninit caused %u bogus npx interrupt(s)\n",
  341                        npx_intrs_while_probing);
  342         if (npx_traps_while_probing != 0)
  343                 printf("fninit caused %u bogus npx trap(s)\n",
  344                        npx_traps_while_probing);
  345 #endif
  346         /*
  347          * Check for a status of mostly zero.
  348          */
  349         status = 0x5a5a;
  350         fnstsw(&status);
  351         if ((status & 0xb8ff) == 0) {
  352                 /*
  353                  * Good, now check for a proper control word.
  354                  */
  355                 control = 0x5a5a;
  356                 fnstcw(&control);
  357                 if ((control & 0x1f3f) == 0x033f) {
  358                         hw_float = npx_exists = 1;
  359                         /*
  360                          * We have an npx, now divide by 0 to see if exception
  361                          * 16 works.
  362                          */
  363                         control &= ~(1 << 2);   /* enable divide by 0 trap */
  364                         fldcw(&control);
  365 #ifdef FPU_ERROR_BROKEN
  366                         /*
  367                          * FPU error signal doesn't work on some CPU
  368                          * accelerator board.
  369                          */
  370                         npx_ex16 = 1;
  371                         return (0);
  372 #endif
  373                         npx_traps_while_probing = npx_intrs_while_probing = 0;
  374                         fp_divide_by_0();
  375                         DELAY(1000);    /* wait for any IRQ13 */
  376                         if (npx_traps_while_probing != 0) {
  377                                 /*
  378                                  * Good, exception 16 works.
  379                                  */
  380                                 npx_ex16 = 1;
  381                                 goto no_irq13;
  382                         }
  383                         if (npx_intrs_while_probing != 0) {
  384                                 /*
  385                                  * Bad, we are stuck with IRQ13.
  386                                  */
  387                                 npx_irq13 = 1;
  388                                 idt[IDT_MF] = save_idt_npxtrap;
  389 #ifdef SMP
  390                                 if (mp_ncpus > 1)
  391                                         panic("npx0 cannot use IRQ 13 on an SMP system");
  392 #endif
  393                                 return (0);
  394                         }
  395                         /*
  396                          * Worse, even IRQ13 is broken.  Use emulator.
  397                          */
  398                 }
  399         }
  400         /*
  401          * Probe failed, but we want to get to npxattach to initialize the
  402          * emulator and say that it has been installed.  XXX handle devices
  403          * that aren't really devices better.
  404          */
  405 #ifdef SMP
  406         if (mp_ncpus > 1)
  407                 panic("npx0 cannot be emulated on an SMP system");
  408 #endif
  409         /* FALLTHROUGH */
  410 no_irq13:
  411         idt[IDT_MF] = save_idt_npxtrap;
  412         bus_teardown_intr(dev, irq_res, irq_cookie);
  413         bus_release_resource(dev, SYS_RES_IRQ, irq_rid, irq_res);
  414         bus_release_resource(dev, SYS_RES_IOPORT, ioport_rid, ioport_res);
  415         return (0);
  416 }
  417 
  418 /*
  419  * Attach routine - announce which it is, and wire into system
  420  */
  421 static int
  422 npx_attach(dev)
  423         device_t dev;
  424 {
  425         int flags;
  426         register_t s;
  427 
  428         flags = device_get_flags(dev);
  429 
  430         if (npx_irq13)
  431                 device_printf(dev, "IRQ 13 interface\n");
  432         else if (npx_ex16)
  433                 device_printf(dev, "INT 16 interface\n");
  434         else
  435                 device_printf(dev, "WARNING: no FPU!\n");
  436 
  437         npxinit(__INITIAL_NPXCW__);
  438 
  439         if (npx_cleanstate_ready == 0) {
  440                 s = intr_disable();
  441                 stop_emulating();
  442                 fpusave(&npx_cleanstate);
  443                 start_emulating();
  444                 npx_cleanstate_ready = 1;
  445                 intr_restore(s);
  446         }
  447 #ifdef I586_CPU_XXX
  448         if (cpu_class == CPUCLASS_586 && npx_ex16 && npx_exists &&
  449             timezero("i586_bzero()", i586_bzero) <
  450             timezero("bzero()", bzero) * 4 / 5) {
  451                 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY))
  452                         bcopy_vector = i586_bcopy;
  453                 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BZERO))
  454                         bzero_vector = i586_bzero;
  455                 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_COPYIO)) {
  456                         copyin_vector = i586_copyin;
  457                         copyout_vector = i586_copyout;
  458                 }
  459         }
  460 #endif
  461 
  462         return (0);             /* XXX unused */
  463 }
  464 
  465 /*
  466  * Initialize floating point unit.
  467  */
  468 void
  469 npxinit(control)
  470         u_short control;
  471 {
  472         static union savefpu dummy;
  473         register_t savecrit;
  474 
  475         if (!npx_exists)
  476                 return;
  477         /*
  478          * fninit has the same h/w bugs as fnsave.  Use the detoxified
  479          * fnsave to throw away any junk in the fpu.  npxsave() initializes
  480          * the fpu and sets fpcurthread = NULL as important side effects.
  481          */
  482         savecrit = intr_disable();
  483         npxsave(&dummy);
  484         stop_emulating();
  485 #ifdef CPU_ENABLE_SSE
  486         /* XXX npxsave() doesn't actually initialize the fpu in the SSE case. */
  487         if (cpu_fxsr)
  488                 fninit();
  489 #endif
  490         fldcw(&control);
  491         start_emulating();
  492         intr_restore(savecrit);
  493 }
  494 
  495 /*
  496  * Free coprocessor (if we have it).
  497  */
  498 void
  499 npxexit(td)
  500         struct thread *td;
  501 {
  502         register_t savecrit;
  503 
  504         savecrit = intr_disable();
  505         if (curthread == PCPU_GET(fpcurthread))
  506                 npxsave(&PCPU_GET(curpcb)->pcb_save);
  507         intr_restore(savecrit);
  508 #ifdef NPX_DEBUG
  509         if (npx_exists) {
  510                 u_int   masked_exceptions;
  511 
  512                 masked_exceptions = GET_FPU_CW(td) & GET_FPU_SW(td) & 0x7f;
  513                 /*
  514                  * Log exceptions that would have trapped with the old
  515                  * control word (overflow, divide by 0, and invalid operand).
  516                  */
  517                 if (masked_exceptions & 0x0d)
  518                         log(LOG_ERR,
  519         "pid %d (%s) exited with masked floating point exceptions 0x%02x\n",
  520                             td->td_proc->p_pid, td->td_proc->p_comm,
  521                             masked_exceptions);
  522         }
  523 #endif
  524 }
  525 
  526 int
  527 npxformat()
  528 {
  529 
  530         if (!npx_exists)
  531                 return (_MC_FPFMT_NODEV);
  532 #ifdef  CPU_ENABLE_SSE
  533         if (cpu_fxsr)
  534                 return (_MC_FPFMT_XMM);
  535 #endif
  536         return (_MC_FPFMT_387);
  537 }
  538 
  539 /* 
  540  * The following mechanism is used to ensure that the FPE_... value
  541  * that is passed as a trapcode to the signal handler of the user
  542  * process does not have more than one bit set.
  543  * 
  544  * Multiple bits may be set if the user process modifies the control
  545  * word while a status word bit is already set.  While this is a sign
  546  * of bad coding, we have no choise than to narrow them down to one
  547  * bit, since we must not send a trapcode that is not exactly one of
  548  * the FPE_ macros.
  549  *
  550  * The mechanism has a static table with 127 entries.  Each combination
  551  * of the 7 FPU status word exception bits directly translates to a
  552  * position in this table, where a single FPE_... value is stored.
  553  * This FPE_... value stored there is considered the "most important"
  554  * of the exception bits and will be sent as the signal code.  The
  555  * precedence of the bits is based upon Intel Document "Numerical
  556  * Applications", Chapter "Special Computational Situations".
  557  *
  558  * The macro to choose one of these values does these steps: 1) Throw
  559  * away status word bits that cannot be masked.  2) Throw away the bits
  560  * currently masked in the control word, assuming the user isn't
  561  * interested in them anymore.  3) Reinsert status word bit 7 (stack
  562  * fault) if it is set, which cannot be masked but must be presered.
  563  * 4) Use the remaining bits to point into the trapcode table.
  564  *
  565  * The 6 maskable bits in order of their preference, as stated in the
  566  * above referenced Intel manual:
  567  * 1  Invalid operation (FP_X_INV)
  568  * 1a   Stack underflow
  569  * 1b   Stack overflow
  570  * 1c   Operand of unsupported format
  571  * 1d   SNaN operand.
  572  * 2  QNaN operand (not an exception, irrelavant here)
  573  * 3  Any other invalid-operation not mentioned above or zero divide
  574  *      (FP_X_INV, FP_X_DZ)
  575  * 4  Denormal operand (FP_X_DNML)
  576  * 5  Numeric over/underflow (FP_X_OFL, FP_X_UFL)
  577  * 6  Inexact result (FP_X_IMP) 
  578  */
  579 static char fpetable[128] = {
  580         0,
  581         FPE_FLTINV,     /*  1 - INV */
  582         FPE_FLTUND,     /*  2 - DNML */
  583         FPE_FLTINV,     /*  3 - INV | DNML */
  584         FPE_FLTDIV,     /*  4 - DZ */
  585         FPE_FLTINV,     /*  5 - INV | DZ */
  586         FPE_FLTDIV,     /*  6 - DNML | DZ */
  587         FPE_FLTINV,     /*  7 - INV | DNML | DZ */
  588         FPE_FLTOVF,     /*  8 - OFL */
  589         FPE_FLTINV,     /*  9 - INV | OFL */
  590         FPE_FLTUND,     /*  A - DNML | OFL */
  591         FPE_FLTINV,     /*  B - INV | DNML | OFL */
  592         FPE_FLTDIV,     /*  C - DZ | OFL */
  593         FPE_FLTINV,     /*  D - INV | DZ | OFL */
  594         FPE_FLTDIV,     /*  E - DNML | DZ | OFL */
  595         FPE_FLTINV,     /*  F - INV | DNML | DZ | OFL */
  596         FPE_FLTUND,     /* 10 - UFL */
  597         FPE_FLTINV,     /* 11 - INV | UFL */
  598         FPE_FLTUND,     /* 12 - DNML | UFL */
  599         FPE_FLTINV,     /* 13 - INV | DNML | UFL */
  600         FPE_FLTDIV,     /* 14 - DZ | UFL */
  601         FPE_FLTINV,     /* 15 - INV | DZ | UFL */
  602         FPE_FLTDIV,     /* 16 - DNML | DZ | UFL */
  603         FPE_FLTINV,     /* 17 - INV | DNML | DZ | UFL */
  604         FPE_FLTOVF,     /* 18 - OFL | UFL */
  605         FPE_FLTINV,     /* 19 - INV | OFL | UFL */
  606         FPE_FLTUND,     /* 1A - DNML | OFL | UFL */
  607         FPE_FLTINV,     /* 1B - INV | DNML | OFL | UFL */
  608         FPE_FLTDIV,     /* 1C - DZ | OFL | UFL */
  609         FPE_FLTINV,     /* 1D - INV | DZ | OFL | UFL */
  610         FPE_FLTDIV,     /* 1E - DNML | DZ | OFL | UFL */
  611         FPE_FLTINV,     /* 1F - INV | DNML | DZ | OFL | UFL */
  612         FPE_FLTRES,     /* 20 - IMP */
  613         FPE_FLTINV,     /* 21 - INV | IMP */
  614         FPE_FLTUND,     /* 22 - DNML | IMP */
  615         FPE_FLTINV,     /* 23 - INV | DNML | IMP */
  616         FPE_FLTDIV,     /* 24 - DZ | IMP */
  617         FPE_FLTINV,     /* 25 - INV | DZ | IMP */
  618         FPE_FLTDIV,     /* 26 - DNML | DZ | IMP */
  619         FPE_FLTINV,     /* 27 - INV | DNML | DZ | IMP */
  620         FPE_FLTOVF,     /* 28 - OFL | IMP */
  621         FPE_FLTINV,     /* 29 - INV | OFL | IMP */
  622         FPE_FLTUND,     /* 2A - DNML | OFL | IMP */
  623         FPE_FLTINV,     /* 2B - INV | DNML | OFL | IMP */
  624         FPE_FLTDIV,     /* 2C - DZ | OFL | IMP */
  625         FPE_FLTINV,     /* 2D - INV | DZ | OFL | IMP */
  626         FPE_FLTDIV,     /* 2E - DNML | DZ | OFL | IMP */
  627         FPE_FLTINV,     /* 2F - INV | DNML | DZ | OFL | IMP */
  628         FPE_FLTUND,     /* 30 - UFL | IMP */
  629         FPE_FLTINV,     /* 31 - INV | UFL | IMP */
  630         FPE_FLTUND,     /* 32 - DNML | UFL | IMP */
  631         FPE_FLTINV,     /* 33 - INV | DNML | UFL | IMP */
  632         FPE_FLTDIV,     /* 34 - DZ | UFL | IMP */
  633         FPE_FLTINV,     /* 35 - INV | DZ | UFL | IMP */
  634         FPE_FLTDIV,     /* 36 - DNML | DZ | UFL | IMP */
  635         FPE_FLTINV,     /* 37 - INV | DNML | DZ | UFL | IMP */
  636         FPE_FLTOVF,     /* 38 - OFL | UFL | IMP */
  637         FPE_FLTINV,     /* 39 - INV | OFL | UFL | IMP */
  638         FPE_FLTUND,     /* 3A - DNML | OFL | UFL | IMP */
  639         FPE_FLTINV,     /* 3B - INV | DNML | OFL | UFL | IMP */
  640         FPE_FLTDIV,     /* 3C - DZ | OFL | UFL | IMP */
  641         FPE_FLTINV,     /* 3D - INV | DZ | OFL | UFL | IMP */
  642         FPE_FLTDIV,     /* 3E - DNML | DZ | OFL | UFL | IMP */
  643         FPE_FLTINV,     /* 3F - INV | DNML | DZ | OFL | UFL | IMP */
  644         FPE_FLTSUB,     /* 40 - STK */
  645         FPE_FLTSUB,     /* 41 - INV | STK */
  646         FPE_FLTUND,     /* 42 - DNML | STK */
  647         FPE_FLTSUB,     /* 43 - INV | DNML | STK */
  648         FPE_FLTDIV,     /* 44 - DZ | STK */
  649         FPE_FLTSUB,     /* 45 - INV | DZ | STK */
  650         FPE_FLTDIV,     /* 46 - DNML | DZ | STK */
  651         FPE_FLTSUB,     /* 47 - INV | DNML | DZ | STK */
  652         FPE_FLTOVF,     /* 48 - OFL | STK */
  653         FPE_FLTSUB,     /* 49 - INV | OFL | STK */
  654         FPE_FLTUND,     /* 4A - DNML | OFL | STK */
  655         FPE_FLTSUB,     /* 4B - INV | DNML | OFL | STK */
  656         FPE_FLTDIV,     /* 4C - DZ | OFL | STK */
  657         FPE_FLTSUB,     /* 4D - INV | DZ | OFL | STK */
  658         FPE_FLTDIV,     /* 4E - DNML | DZ | OFL | STK */
  659         FPE_FLTSUB,     /* 4F - INV | DNML | DZ | OFL | STK */
  660         FPE_FLTUND,     /* 50 - UFL | STK */
  661         FPE_FLTSUB,     /* 51 - INV | UFL | STK */
  662         FPE_FLTUND,     /* 52 - DNML | UFL | STK */
  663         FPE_FLTSUB,     /* 53 - INV | DNML | UFL | STK */
  664         FPE_FLTDIV,     /* 54 - DZ | UFL | STK */
  665         FPE_FLTSUB,     /* 55 - INV | DZ | UFL | STK */
  666         FPE_FLTDIV,     /* 56 - DNML | DZ | UFL | STK */
  667         FPE_FLTSUB,     /* 57 - INV | DNML | DZ | UFL | STK */
  668         FPE_FLTOVF,     /* 58 - OFL | UFL | STK */
  669         FPE_FLTSUB,     /* 59 - INV | OFL | UFL | STK */
  670         FPE_FLTUND,     /* 5A - DNML | OFL | UFL | STK */
  671         FPE_FLTSUB,     /* 5B - INV | DNML | OFL | UFL | STK */
  672         FPE_FLTDIV,     /* 5C - DZ | OFL | UFL | STK */
  673         FPE_FLTSUB,     /* 5D - INV | DZ | OFL | UFL | STK */
  674         FPE_FLTDIV,     /* 5E - DNML | DZ | OFL | UFL | STK */
  675         FPE_FLTSUB,     /* 5F - INV | DNML | DZ | OFL | UFL | STK */
  676         FPE_FLTRES,     /* 60 - IMP | STK */
  677         FPE_FLTSUB,     /* 61 - INV | IMP | STK */
  678         FPE_FLTUND,     /* 62 - DNML | IMP | STK */
  679         FPE_FLTSUB,     /* 63 - INV | DNML | IMP | STK */
  680         FPE_FLTDIV,     /* 64 - DZ | IMP | STK */
  681         FPE_FLTSUB,     /* 65 - INV | DZ | IMP | STK */
  682         FPE_FLTDIV,     /* 66 - DNML | DZ | IMP | STK */
  683         FPE_FLTSUB,     /* 67 - INV | DNML | DZ | IMP | STK */
  684         FPE_FLTOVF,     /* 68 - OFL | IMP | STK */
  685         FPE_FLTSUB,     /* 69 - INV | OFL | IMP | STK */
  686         FPE_FLTUND,     /* 6A - DNML | OFL | IMP | STK */
  687         FPE_FLTSUB,     /* 6B - INV | DNML | OFL | IMP | STK */
  688         FPE_FLTDIV,     /* 6C - DZ | OFL | IMP | STK */
  689         FPE_FLTSUB,     /* 6D - INV | DZ | OFL | IMP | STK */
  690         FPE_FLTDIV,     /* 6E - DNML | DZ | OFL | IMP | STK */
  691         FPE_FLTSUB,     /* 6F - INV | DNML | DZ | OFL | IMP | STK */
  692         FPE_FLTUND,     /* 70 - UFL | IMP | STK */
  693         FPE_FLTSUB,     /* 71 - INV | UFL | IMP | STK */
  694         FPE_FLTUND,     /* 72 - DNML | UFL | IMP | STK */
  695         FPE_FLTSUB,     /* 73 - INV | DNML | UFL | IMP | STK */
  696         FPE_FLTDIV,     /* 74 - DZ | UFL | IMP | STK */
  697         FPE_FLTSUB,     /* 75 - INV | DZ | UFL | IMP | STK */
  698         FPE_FLTDIV,     /* 76 - DNML | DZ | UFL | IMP | STK */
  699         FPE_FLTSUB,     /* 77 - INV | DNML | DZ | UFL | IMP | STK */
  700         FPE_FLTOVF,     /* 78 - OFL | UFL | IMP | STK */
  701         FPE_FLTSUB,     /* 79 - INV | OFL | UFL | IMP | STK */
  702         FPE_FLTUND,     /* 7A - DNML | OFL | UFL | IMP | STK */
  703         FPE_FLTSUB,     /* 7B - INV | DNML | OFL | UFL | IMP | STK */
  704         FPE_FLTDIV,     /* 7C - DZ | OFL | UFL | IMP | STK */
  705         FPE_FLTSUB,     /* 7D - INV | DZ | OFL | UFL | IMP | STK */
  706         FPE_FLTDIV,     /* 7E - DNML | DZ | OFL | UFL | IMP | STK */
  707         FPE_FLTSUB,     /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */
  708 };
  709 
  710 /*
  711  * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE.
  712  *
  713  * Clearing exceptions is necessary mainly to avoid IRQ13 bugs.  We now
  714  * depend on longjmp() restoring a usable state.  Restoring the state
  715  * or examining it might fail if we didn't clear exceptions.
  716  *
  717  * The error code chosen will be one of the FPE_... macros. It will be
  718  * sent as the second argument to old BSD-style signal handlers and as
  719  * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers.
  720  *
  721  * XXX the FP state is not preserved across signal handlers.  So signal
  722  * handlers cannot afford to do FP unless they preserve the state or
  723  * longjmp() out.  Both preserving the state and longjmp()ing may be
  724  * destroyed by IRQ13 bugs.  Clearing FP exceptions is not an acceptable
  725  * solution for signals other than SIGFPE.
  726  */
  727 int
  728 npxtrap()
  729 {
  730         register_t savecrit;
  731         u_short control, status;
  732 
  733         if (!npx_exists) {
  734                 printf("npxtrap: fpcurthread = %p, curthread = %p, npx_exists = %d\n",
  735                        PCPU_GET(fpcurthread), curthread, npx_exists);
  736                 panic("npxtrap from nowhere");
  737         }
  738         savecrit = intr_disable();
  739 
  740         /*
  741          * Interrupt handling (for another interrupt) may have pushed the
  742          * state to memory.  Fetch the relevant parts of the state from
  743          * wherever they are.
  744          */
  745         if (PCPU_GET(fpcurthread) != curthread) {
  746                 control = GET_FPU_CW(curthread);
  747                 status = GET_FPU_SW(curthread);
  748         } else {
  749                 fnstcw(&control);
  750                 fnstsw(&status);
  751         }
  752 
  753         if (PCPU_GET(fpcurthread) == curthread)
  754                 fnclex();
  755         intr_restore(savecrit);
  756         return (fpetable[status & ((~control & 0x3f) | 0x40)]);
  757 }
  758 
  759 /*
  760  * Implement device not available (DNA) exception
  761  *
  762  * It would be better to switch FP context here (if curthread != fpcurthread)
  763  * and not necessarily for every context switch, but it is too hard to
  764  * access foreign pcb's.
  765  */
  766 
  767 static int err_count = 0;
  768 
  769 int
  770 npxdna()
  771 {
  772         struct pcb *pcb;
  773         register_t s;
  774 #ifdef CPU_ENABLE_SSE
  775         int mxcsr;
  776 #endif
  777         u_short control;
  778 
  779         if (!npx_exists)
  780                 return (0);
  781         if (PCPU_GET(fpcurthread) == curthread) {
  782                 printf("npxdna: fpcurthread == curthread %d times\n",
  783                     ++err_count);
  784                 stop_emulating();
  785                 return (1);
  786         }
  787         if (PCPU_GET(fpcurthread) != NULL) {
  788                 printf("npxdna: fpcurthread = %p (%d), curthread = %p (%d)\n",
  789                        PCPU_GET(fpcurthread),
  790                        PCPU_GET(fpcurthread)->td_proc->p_pid,
  791                        curthread, curthread->td_proc->p_pid);
  792                 panic("npxdna");
  793         }
  794         s = intr_disable();
  795         stop_emulating();
  796         /*
  797          * Record new context early in case frstor causes an IRQ13.
  798          */
  799         PCPU_SET(fpcurthread, curthread);
  800         pcb = PCPU_GET(curpcb);
  801 
  802         if ((pcb->pcb_flags & PCB_NPXINITDONE) == 0) {
  803                 /*
  804                  * This is the first time this thread has used the FPU or
  805                  * the PCB doesn't contain a clean FPU state.  Explicitly
  806                  * initialize the FPU and load the default control word.
  807                  */
  808                 fninit();
  809                 control = __INITIAL_NPXCW__;
  810                 fldcw(&control);
  811 #ifdef CPU_ENABLE_SSE
  812                 if (cpu_fxsr) {
  813                         mxcsr = __INITIAL_MXCSR__;
  814                         ldmxcsr(mxcsr);
  815                 }
  816 #endif
  817                 pcb->pcb_flags |= PCB_NPXINITDONE;
  818         } else {
  819                 /*
  820                  * The following frstor may cause an IRQ13 when the state
  821                  * being restored has a pending error.  The error will
  822                  * appear to have been triggered by the current (npx) user
  823                  * instruction even when that instruction is a no-wait
  824                  * instruction that should not trigger an error (e.g.,
  825                  * fnclex).  On at least one 486 system all of the no-wait
  826                  * instructions are broken the same as frstor, so our
  827                  * treatment does not amplify the breakage.  On at least
  828                  * one 386/Cyrix 387 system, fnclex works correctly while
  829                  * frstor and fnsave are broken, so our treatment breaks
  830                  * fnclex if it is the first FPU instruction after a context
  831                  * switch.
  832                  */
  833                 fpurstor(&pcb->pcb_save);
  834         }
  835         intr_restore(s);
  836 
  837         return (1);
  838 }
  839 
  840 /*
  841  * Wrapper for fnsave instruction, partly to handle hardware bugs.  When npx
  842  * exceptions are reported via IRQ13, spurious IRQ13's may be triggered by
  843  * no-wait npx instructions.  See the Intel application note AP-578 for
  844  * details.  This doesn't cause any additional complications here.  IRQ13's
  845  * are inherently asynchronous unless the CPU is frozen to deliver them --
  846  * one that started in userland may be delivered many instructions later,
  847  * after the process has entered the kernel.  It may even be delivered after
  848  * the fnsave here completes.  A spurious IRQ13 for the fnsave is handled in
  849  * the same way as a very-late-arriving non-spurious IRQ13 from user mode:
  850  * it is normally ignored at first because we set fpcurthread to NULL; it is
  851  * normally retriggered in npxdna() after return to user mode.
  852  *
  853  * npxsave() must be called with interrupts disabled, so that it clears
  854  * fpcurthread atomically with saving the state.  We require callers to do the
  855  * disabling, since most callers need to disable interrupts anyway to call
  856  * npxsave() atomically with checking fpcurthread.
  857  *
  858  * A previous version of npxsave() went to great lengths to excecute fnsave
  859  * with interrupts enabled in case executing it froze the CPU.  This case
  860  * can't happen, at least for Intel CPU/NPX's.  Spurious IRQ13's don't imply
  861  * spurious freezes.
  862  */
  863 void
  864 npxsave(addr)
  865         union savefpu *addr;
  866 {
  867 
  868         stop_emulating();
  869         fpusave(addr);
  870 
  871         start_emulating();
  872         PCPU_SET(fpcurthread, NULL);
  873 }
  874 
  875 /*
  876  * This should be called with interrupts disabled and only when the owning
  877  * FPU thread is non-null.
  878  */
  879 void
  880 npxdrop()
  881 {
  882         struct thread *td;
  883 
  884         /*
  885          * Discard pending exceptions in the !cpu_fxsr case so that unmasked
  886          * ones don't cause a panic on the next frstor.
  887          */
  888 #ifdef CPU_ENABLE_SSE
  889         if (!cpu_fxsr)
  890 #endif
  891                 fnclex();
  892 
  893         td = PCPU_GET(fpcurthread);
  894         PCPU_SET(fpcurthread, NULL);
  895         td->td_pcb->pcb_flags &= ~PCB_NPXINITDONE;
  896         start_emulating();
  897 }
  898 
  899 /*
  900  * Get the state of the FPU without dropping ownership (if possible).
  901  * It returns the FPU ownership status.
  902  */
  903 int
  904 npxgetregs(td, addr)
  905         struct thread *td;
  906         union savefpu *addr;
  907 {
  908         register_t s;
  909 
  910         if (!npx_exists)
  911                 return (_MC_FPOWNED_NONE);
  912 
  913         if ((td->td_pcb->pcb_flags & PCB_NPXINITDONE) == 0) {
  914                 if (npx_cleanstate_ready)
  915                         bcopy(&npx_cleanstate, addr, sizeof(npx_cleanstate));
  916                 else
  917                         bzero(addr, sizeof(*addr));
  918                 return (_MC_FPOWNED_NONE);
  919         }
  920         s = intr_disable();
  921         if (td == PCPU_GET(fpcurthread)) {
  922                 fpusave(addr);
  923 #ifdef CPU_ENABLE_SSE
  924                 if (!cpu_fxsr)
  925 #endif
  926                         /*
  927                          * fnsave initializes the FPU and destroys whatever
  928                          * context it contains.  Make sure the FPU owner
  929                          * starts with a clean state next time.
  930                          */
  931                         npxdrop();
  932                 intr_restore(s);
  933                 return (_MC_FPOWNED_FPU);
  934         } else {
  935                 intr_restore(s);
  936                 bcopy(&td->td_pcb->pcb_save, addr, sizeof(*addr));
  937                 return (_MC_FPOWNED_PCB);
  938         }
  939 }
  940 
  941 /*
  942  * Set the state of the FPU.
  943  */
  944 void
  945 npxsetregs(td, addr)
  946         struct thread *td;
  947         union savefpu *addr;
  948 {
  949         register_t s;
  950 
  951         if (!npx_exists)
  952                 return;
  953 
  954         s = intr_disable();
  955         if (td == PCPU_GET(fpcurthread)) {
  956 #ifdef CPU_ENABLE_SSE
  957                 if (!cpu_fxsr)
  958 #endif
  959                         fnclex();       /* As in npxdrop(). */
  960                 fpurstor(addr);
  961                 intr_restore(s);
  962         } else {
  963                 intr_restore(s);
  964                 bcopy(addr, &td->td_pcb->pcb_save, sizeof(*addr));
  965         }
  966         curthread->td_pcb->pcb_flags |= PCB_NPXINITDONE;
  967 }
  968 
  969 static void
  970 fpusave(addr)
  971         union savefpu *addr;
  972 {
  973         
  974 #ifdef CPU_ENABLE_SSE
  975         if (cpu_fxsr)
  976                 fxsave(addr);
  977         else
  978 #endif
  979                 fnsave(addr);
  980 }
  981 
  982 #ifdef CPU_ENABLE_SSE
  983 /*
  984  * On AuthenticAMD processors, the fxrstor instruction does not restore
  985  * the x87's stored last instruction pointer, last data pointer, and last
  986  * opcode values, except in the rare case in which the exception summary
  987  * (ES) bit in the x87 status word is set to 1.
  988  *
  989  * In order to avoid leaking this information across processes, we clean
  990  * these values by performing a dummy load before executing fxrstor().
  991  */
  992 static  double  dummy_variable = 0.0;
  993 static void
  994 fpu_clean_state(void)
  995 {
  996         u_short status;
  997 
  998         /*
  999          * Clear the ES bit in the x87 status word if it is currently
 1000          * set, in order to avoid causing a fault in the upcoming load.
 1001          */
 1002         fnstsw(&status);
 1003         if (status & 0x80)
 1004                 fnclex();
 1005 
 1006         /*
 1007          * Load the dummy variable into the x87 stack.  This mangles
 1008          * the x87 stack, but we don't care since we're about to call
 1009          * fxrstor() anyway.
 1010          */
 1011         __asm __volatile("ffree %%st(7); fld %0" : : "m" (dummy_variable));
 1012 }
 1013 #endif /* CPU_ENABLE_SSE */
 1014 
 1015 static void
 1016 fpurstor(addr)
 1017         union savefpu *addr;
 1018 {
 1019 
 1020 #ifdef CPU_ENABLE_SSE
 1021         if (cpu_fxsr) {
 1022                 fpu_clean_state();
 1023                 fxrstor(addr);
 1024         } else
 1025 #endif
 1026                 frstor(addr);
 1027 }
 1028 
 1029 #ifdef I586_CPU_XXX
 1030 static long
 1031 timezero(funcname, func)
 1032         const char *funcname;
 1033         void (*func)(void *buf, size_t len);
 1034 
 1035 {
 1036         void *buf;
 1037 #define BUFSIZE         1048576
 1038         long usec;
 1039         struct timeval finish, start;
 1040 
 1041         buf = malloc(BUFSIZE, M_TEMP, M_NOWAIT);
 1042         if (buf == NULL)
 1043                 return (BUFSIZE);
 1044         microtime(&start);
 1045         (*func)(buf, BUFSIZE);
 1046         microtime(&finish);
 1047         usec = 1000000 * (finish.tv_sec - start.tv_sec) +
 1048             finish.tv_usec - start.tv_usec;
 1049         if (usec <= 0)
 1050                 usec = 1;
 1051         if (bootverbose)
 1052                 printf("%s bandwidth = %u kBps\n", funcname,
 1053                     (u_int32_t)(((BUFSIZE >> 10) * 1000000) / usec));
 1054         free(buf, M_TEMP);
 1055         return (usec);
 1056 }
 1057 #endif /* I586_CPU */
 1058 
 1059 static device_method_t npx_methods[] = {
 1060         /* Device interface */
 1061         DEVMETHOD(device_identify,      npx_identify),
 1062         DEVMETHOD(device_probe,         npx_probe),
 1063         DEVMETHOD(device_attach,        npx_attach),
 1064         DEVMETHOD(device_detach,        bus_generic_detach),
 1065         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
 1066         DEVMETHOD(device_suspend,       bus_generic_suspend),
 1067         DEVMETHOD(device_resume,        bus_generic_resume),
 1068         
 1069         { 0, 0 }
 1070 };
 1071 
 1072 static driver_t npx_driver = {
 1073         "npx",
 1074         npx_methods,
 1075         1,                      /* no softc */
 1076 };
 1077 
 1078 static devclass_t npx_devclass;
 1079 
 1080 /*
 1081  * We prefer to attach to the root nexus so that the usual case (exception 16)
 1082  * doesn't describe the processor as being `on isa'.
 1083  */
 1084 DRIVER_MODULE(npx, nexus, npx_driver, npx_devclass, 0, 0);
 1085 
 1086 #ifdef DEV_ISA
 1087 /*
 1088  * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI.
 1089  */
 1090 static struct isa_pnp_id npxisa_ids[] = {
 1091         { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */
 1092         { 0 }
 1093 };
 1094 
 1095 static int
 1096 npxisa_probe(device_t dev)
 1097 {
 1098         int result;
 1099         if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, npxisa_ids)) <= 0) {
 1100                 device_quiet(dev);
 1101         }
 1102         return(result);
 1103 }
 1104 
 1105 static int
 1106 npxisa_attach(device_t dev)
 1107 {
 1108         return (0);
 1109 }
 1110 
 1111 static device_method_t npxisa_methods[] = {
 1112         /* Device interface */
 1113         DEVMETHOD(device_probe,         npxisa_probe),
 1114         DEVMETHOD(device_attach,        npxisa_attach),
 1115         DEVMETHOD(device_detach,        bus_generic_detach),
 1116         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
 1117         DEVMETHOD(device_suspend,       bus_generic_suspend),
 1118         DEVMETHOD(device_resume,        bus_generic_resume),
 1119         
 1120         { 0, 0 }
 1121 };
 1122 
 1123 static driver_t npxisa_driver = {
 1124         "npxisa",
 1125         npxisa_methods,
 1126         1,                      /* no softc */
 1127 };
 1128 
 1129 static devclass_t npxisa_devclass;
 1130 
 1131 DRIVER_MODULE(npxisa, isa, npxisa_driver, npxisa_devclass, 0, 0);
 1132 #ifndef PC98
 1133 DRIVER_MODULE(npxisa, acpi, npxisa_driver, npxisa_devclass, 0, 0);
 1134 #endif
 1135 #endif /* DEV_ISA */

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