The Design and Implementation of the FreeBSD Operating System, Second Edition
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sys/i386/isa/npx.c

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    1 /*-
    2  * Copyright (c) 1990 William Jolitz.
    3  * Copyright (c) 1991 The Regents of the University of California.
    4  * All rights reserved.
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions
    8  * are met:
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  * 4. Neither the name of the University nor the names of its contributors
   15  *    may be used to endorse or promote products derived from this software
   16  *    without specific prior written permission.
   17  *
   18  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   28  * SUCH DAMAGE.
   29  *
   30  *      from: @(#)npx.c 7.2 (Berkeley) 5/12/91
   31  */
   32 
   33 #include <sys/cdefs.h>
   34 __FBSDID("$FreeBSD: releng/6.0/sys/i386/isa/npx.c 157863 2006-04-19 07:03:14Z cperciva $");
   35 
   36 #include "opt_cpu.h"
   37 #include "opt_isa.h"
   38 #include "opt_npx.h"
   39 
   40 #include <sys/param.h>
   41 #include <sys/systm.h>
   42 #include <sys/bus.h>
   43 #include <sys/kernel.h>
   44 #include <sys/lock.h>
   45 #include <sys/malloc.h>
   46 #include <sys/module.h>
   47 #include <sys/mutex.h>
   48 #include <sys/mutex.h>
   49 #include <sys/proc.h>
   50 #include <sys/smp.h>
   51 #include <sys/sysctl.h>
   52 #include <machine/bus.h>
   53 #include <sys/rman.h>
   54 #ifdef NPX_DEBUG
   55 #include <sys/syslog.h>
   56 #endif
   57 #include <sys/signalvar.h>
   58 
   59 #include <machine/asmacros.h>
   60 #include <machine/cputypes.h>
   61 #include <machine/frame.h>
   62 #include <machine/md_var.h>
   63 #include <machine/pcb.h>
   64 #include <machine/psl.h>
   65 #include <machine/clock.h>
   66 #include <machine/resource.h>
   67 #include <machine/specialreg.h>
   68 #include <machine/segments.h>
   69 #include <machine/ucontext.h>
   70 
   71 #include <machine/intr_machdep.h>
   72 #ifdef DEV_ISA
   73 #include <isa/isavar.h>
   74 #endif
   75 
   76 #if !defined(CPU_DISABLE_SSE) && defined(I686_CPU)
   77 #define CPU_ENABLE_SSE
   78 #endif
   79 
   80 /*
   81  * 387 and 287 Numeric Coprocessor Extension (NPX) Driver.
   82  */
   83 
   84 /* Configuration flags. */
   85 #define NPX_DISABLE_I586_OPTIMIZED_BCOPY        (1 << 0)
   86 #define NPX_DISABLE_I586_OPTIMIZED_BZERO        (1 << 1)
   87 #define NPX_DISABLE_I586_OPTIMIZED_COPYIO       (1 << 2)
   88 
   89 #if defined(__GNUCLIKE_ASM) && !defined(lint)
   90 
   91 #define fldcw(addr)             __asm("fldcw %0" : : "m" (*(addr)))
   92 #define fnclex()                __asm("fnclex")
   93 #define fninit()                __asm("fninit")
   94 #define fnsave(addr)            __asm __volatile("fnsave %0" : "=m" (*(addr)))
   95 #define fnstcw(addr)            __asm __volatile("fnstcw %0" : "=m" (*(addr)))
   96 #define fnstsw(addr)            __asm __volatile("fnstsw %0" : "=m" (*(addr)))
   97 #define fp_divide_by_0()        __asm("fldz; fld1; fdiv %st,%st(1); fnop")
   98 #define frstor(addr)            __asm("frstor %0" : : "m" (*(addr)))
   99 #ifdef CPU_ENABLE_SSE
  100 #define fxrstor(addr)           __asm("fxrstor %0" : : "m" (*(addr)))
  101 #define fxsave(addr)            __asm __volatile("fxsave %0" : "=m" (*(addr)))
  102 #define ldmxcsr(__csr)          __asm __volatile("ldmxcsr %0" : : "m" (__csr))
  103 #endif
  104 #define start_emulating()       __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \
  105                                       : : "n" (CR0_TS) : "ax")
  106 #define stop_emulating()        __asm("clts")
  107 
  108 #else   /* !(__GNUCLIKE_ASM && !lint) */
  109 
  110 void    fldcw(caddr_t addr);
  111 void    fnclex(void);
  112 void    fninit(void);
  113 void    fnsave(caddr_t addr);
  114 void    fnstcw(caddr_t addr);
  115 void    fnstsw(caddr_t addr);
  116 void    fp_divide_by_0(void);
  117 void    frstor(caddr_t addr);
  118 #ifdef CPU_ENABLE_SSE
  119 void    fxsave(caddr_t addr);
  120 void    fxrstor(caddr_t addr);
  121 #endif
  122 void    start_emulating(void);
  123 void    stop_emulating(void);
  124 
  125 #endif  /* __GNUCLIKE_ASM && !lint */
  126 
  127 #ifdef CPU_ENABLE_SSE
  128 #define GET_FPU_CW(thread) \
  129         (cpu_fxsr ? \
  130                 (thread)->td_pcb->pcb_save.sv_xmm.sv_env.en_cw : \
  131                 (thread)->td_pcb->pcb_save.sv_87.sv_env.en_cw)
  132 #define GET_FPU_SW(thread) \
  133         (cpu_fxsr ? \
  134                 (thread)->td_pcb->pcb_save.sv_xmm.sv_env.en_sw : \
  135                 (thread)->td_pcb->pcb_save.sv_87.sv_env.en_sw)
  136 #else /* CPU_ENABLE_SSE */
  137 #define GET_FPU_CW(thread) \
  138         (thread->td_pcb->pcb_save.sv_87.sv_env.en_cw)
  139 #define GET_FPU_SW(thread) \
  140         (thread->td_pcb->pcb_save.sv_87.sv_env.en_sw)
  141 #endif /* CPU_ENABLE_SSE */
  142 
  143 typedef u_char bool_t;
  144 
  145 #ifdef CPU_ENABLE_SSE
  146 static  void    fpu_clean_state(void);
  147 #endif
  148 
  149 static  void    fpusave(union savefpu *);
  150 static  void    fpurstor(union savefpu *);
  151 static  int     npx_attach(device_t dev);
  152 static  void    npx_identify(driver_t *driver, device_t parent);
  153 static  void    npx_intr(void *);
  154 static  int     npx_probe(device_t dev);
  155 #ifdef I586_CPU_XXX
  156 static  long    timezero(const char *funcname,
  157                     void (*func)(void *buf, size_t len));
  158 #endif /* I586_CPU */
  159 
  160 int     hw_float;               /* XXX currently just alias for npx_exists */
  161 
  162 SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint,
  163         CTLFLAG_RD, &hw_float, 0, 
  164         "Floatingpoint instructions executed in hardware");
  165 
  166 static  volatile u_int          npx_intrs_while_probing;
  167 static  volatile u_int          npx_traps_while_probing;
  168 
  169 static  union savefpu           npx_cleanstate;
  170 static  bool_t                  npx_cleanstate_ready;
  171 static  bool_t                  npx_ex16;
  172 static  bool_t                  npx_exists;
  173 static  bool_t                  npx_irq13;
  174 
  175 alias_for_inthand_t probetrap;
  176 __asm("                                                         \n\
  177         .text                                                   \n\
  178         .p2align 2,0x90                                         \n\
  179         .type   " __XSTRING(CNAME(probetrap)) ",@function       \n\
  180 " __XSTRING(CNAME(probetrap)) ":                                \n\
  181         ss                                                      \n\
  182         incl    " __XSTRING(CNAME(npx_traps_while_probing)) "   \n\
  183         fnclex                                                  \n\
  184         iret                                                    \n\
  185 ");
  186 
  187 /*
  188  * Identify routine.  Create a connection point on our parent for probing.
  189  */
  190 static void
  191 npx_identify(driver, parent)
  192         driver_t *driver;
  193         device_t parent;
  194 {
  195         device_t child;
  196 
  197         child = BUS_ADD_CHILD(parent, 0, "npx", 0);
  198         if (child == NULL)
  199                 panic("npx_identify");
  200 }
  201 
  202 /*
  203  * Do minimal handling of npx interrupts to convert them to traps.
  204  */
  205 static void
  206 npx_intr(dummy)
  207         void *dummy;
  208 {
  209         struct thread *td;
  210 
  211         npx_intrs_while_probing++;
  212 
  213         /*
  214          * The BUSY# latch must be cleared in all cases so that the next
  215          * unmasked npx exception causes an interrupt.
  216          */
  217         outb(IO_NPX, 0);
  218 
  219         /*
  220          * fpcurthread is normally non-null here.  In that case, schedule an
  221          * AST to finish the exception handling in the correct context
  222          * (this interrupt may occur after the thread has entered the
  223          * kernel via a syscall or an interrupt).  Otherwise, the npx
  224          * state of the thread that caused this interrupt must have been
  225          * pushed to the thread's pcb, and clearing of the busy latch
  226          * above has finished the (essentially null) handling of this
  227          * interrupt.  Control will eventually return to the instruction
  228          * that caused it and it will repeat.  We will eventually (usually
  229          * soon) win the race to handle the interrupt properly.
  230          */
  231         td = PCPU_GET(fpcurthread);
  232         if (td != NULL) {
  233                 td->td_pcb->pcb_flags |= PCB_NPXTRAP;
  234                 mtx_lock_spin(&sched_lock);
  235                 td->td_flags |= TDF_ASTPENDING;
  236                 mtx_unlock_spin(&sched_lock);
  237         }
  238 }
  239 
  240 /*
  241  * Probe routine.  Initialize cr0 to give correct behaviour for [f]wait
  242  * whether the device exists or not (XXX should be elsewhere).  Set flags
  243  * to tell npxattach() what to do.  Modify device struct if npx doesn't
  244  * need to use interrupts.  Return 0 if device exists.
  245  */
  246 static int
  247 npx_probe(dev)
  248         device_t dev;
  249 {
  250         struct gate_descriptor save_idt_npxtrap;
  251         struct resource *ioport_res, *irq_res;
  252         void *irq_cookie;
  253         int ioport_rid, irq_num, irq_rid;
  254         u_short control;
  255         u_short status;
  256 
  257         save_idt_npxtrap = idt[IDT_MF];
  258         setidt(IDT_MF, probetrap, SDT_SYS386TGT, SEL_KPL,
  259             GSEL(GCODE_SEL, SEL_KPL));
  260         ioport_rid = 0;
  261         ioport_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &ioport_rid,
  262             IO_NPX, IO_NPX + IO_NPXSIZE - 1, IO_NPXSIZE, RF_ACTIVE);
  263         if (ioport_res == NULL)
  264                 panic("npx: can't get ports");
  265         if (resource_int_value("npx", 0, "irq", &irq_num) != 0)
  266                 irq_num = IRQ_NPX;
  267         irq_rid = 0;
  268         irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &irq_rid, irq_num,
  269             irq_num, 1, RF_ACTIVE);
  270         if (irq_res == NULL)
  271                 panic("npx: can't get IRQ");
  272         if (bus_setup_intr(dev, irq_res, INTR_TYPE_MISC | INTR_FAST, npx_intr,
  273             NULL, &irq_cookie) != 0)
  274                 panic("npx: can't create intr");
  275 
  276         /*
  277          * Partially reset the coprocessor, if any.  Some BIOS's don't reset
  278          * it after a warm boot.
  279          */
  280         npx_full_reset();
  281         outb(IO_NPX, 0);
  282 
  283         /*
  284          * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT
  285          * instructions.  We must set the CR0_MP bit and use the CR0_TS
  286          * bit to control the trap, because setting the CR0_EM bit does
  287          * not cause WAIT instructions to trap.  It's important to trap
  288          * WAIT instructions - otherwise the "wait" variants of no-wait
  289          * control instructions would degenerate to the "no-wait" variants
  290          * after FP context switches but work correctly otherwise.  It's
  291          * particularly important to trap WAITs when there is no NPX -
  292          * otherwise the "wait" variants would always degenerate.
  293          *
  294          * Try setting CR0_NE to get correct error reporting on 486DX's.
  295          * Setting it should fail or do nothing on lesser processors.
  296          */
  297         load_cr0(rcr0() | CR0_MP | CR0_NE);
  298         /*
  299          * But don't trap while we're probing.
  300          */
  301         stop_emulating();
  302         /*
  303          * Finish resetting the coprocessor, if any.  If there is an error
  304          * pending, then we may get a bogus IRQ13, but npx_intr() will handle
  305          * it OK.  Bogus halts have never been observed, but we enabled
  306          * IRQ13 and cleared the BUSY# latch early to handle them anyway.
  307          */
  308         fninit();
  309 
  310         device_set_desc(dev, "math processor");
  311 
  312         /*
  313          * Don't use fwait here because it might hang.
  314          * Don't use fnop here because it usually hangs if there is no FPU.
  315          */
  316         DELAY(1000);            /* wait for any IRQ13 */
  317 #ifdef DIAGNOSTIC
  318         if (npx_intrs_while_probing != 0)
  319                 printf("fninit caused %u bogus npx interrupt(s)\n",
  320                        npx_intrs_while_probing);
  321         if (npx_traps_while_probing != 0)
  322                 printf("fninit caused %u bogus npx trap(s)\n",
  323                        npx_traps_while_probing);
  324 #endif
  325         /*
  326          * Check for a status of mostly zero.
  327          */
  328         status = 0x5a5a;
  329         fnstsw(&status);
  330         if ((status & 0xb8ff) == 0) {
  331                 /*
  332                  * Good, now check for a proper control word.
  333                  */
  334                 control = 0x5a5a;
  335                 fnstcw(&control);
  336                 if ((control & 0x1f3f) == 0x033f) {
  337                         hw_float = npx_exists = 1;
  338                         /*
  339                          * We have an npx, now divide by 0 to see if exception
  340                          * 16 works.
  341                          */
  342                         control &= ~(1 << 2);   /* enable divide by 0 trap */
  343                         fldcw(&control);
  344 #ifdef FPU_ERROR_BROKEN
  345                         /*
  346                          * FPU error signal doesn't work on some CPU
  347                          * accelerator board.
  348                          */
  349                         npx_ex16 = 1;
  350                         return (0);
  351 #endif
  352                         npx_traps_while_probing = npx_intrs_while_probing = 0;
  353                         fp_divide_by_0();
  354                         DELAY(1000);    /* wait for any IRQ13 */
  355                         if (npx_traps_while_probing != 0) {
  356                                 /*
  357                                  * Good, exception 16 works.
  358                                  */
  359                                 npx_ex16 = 1;
  360                                 goto no_irq13;
  361                         }
  362                         if (npx_intrs_while_probing != 0) {
  363                                 /*
  364                                  * Bad, we are stuck with IRQ13.
  365                                  */
  366                                 npx_irq13 = 1;
  367                                 idt[IDT_MF] = save_idt_npxtrap;
  368 #ifdef SMP
  369                                 if (mp_ncpus > 1)
  370                                         panic("npx0 cannot use IRQ 13 on an SMP system");
  371 #endif
  372                                 return (0);
  373                         }
  374                         /*
  375                          * Worse, even IRQ13 is broken.  Use emulator.
  376                          */
  377                 }
  378         }
  379         /*
  380          * Probe failed, but we want to get to npxattach to initialize the
  381          * emulator and say that it has been installed.  XXX handle devices
  382          * that aren't really devices better.
  383          */
  384 #ifdef SMP
  385         if (mp_ncpus > 1)
  386                 panic("npx0 cannot be emulated on an SMP system");
  387 #endif
  388         /* FALLTHROUGH */
  389 no_irq13:
  390         idt[IDT_MF] = save_idt_npxtrap;
  391         bus_teardown_intr(dev, irq_res, irq_cookie);
  392         bus_release_resource(dev, SYS_RES_IRQ, irq_rid, irq_res);
  393         bus_release_resource(dev, SYS_RES_IOPORT, ioport_rid, ioport_res);
  394         return (0);
  395 }
  396 
  397 /*
  398  * Attach routine - announce which it is, and wire into system
  399  */
  400 static int
  401 npx_attach(dev)
  402         device_t dev;
  403 {
  404         int flags;
  405         register_t s;
  406 
  407         flags = device_get_flags(dev);
  408 
  409         if (npx_irq13)
  410                 device_printf(dev, "IRQ 13 interface\n");
  411         else if (npx_ex16)
  412                 device_printf(dev, "INT 16 interface\n");
  413         else
  414                 device_printf(dev, "WARNING: no FPU!\n");
  415 
  416         npxinit(__INITIAL_NPXCW__);
  417 
  418         if (npx_cleanstate_ready == 0) {
  419                 s = intr_disable();
  420                 stop_emulating();
  421                 fpusave(&npx_cleanstate);
  422                 start_emulating();
  423                 npx_cleanstate_ready = 1;
  424                 intr_restore(s);
  425         }
  426 #ifdef I586_CPU_XXX
  427         if (cpu_class == CPUCLASS_586 && npx_ex16 && npx_exists &&
  428             timezero("i586_bzero()", i586_bzero) <
  429             timezero("bzero()", bzero) * 4 / 5) {
  430                 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY))
  431                         bcopy_vector = i586_bcopy;
  432                 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BZERO))
  433                         bzero_vector = i586_bzero;
  434                 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_COPYIO)) {
  435                         copyin_vector = i586_copyin;
  436                         copyout_vector = i586_copyout;
  437                 }
  438         }
  439 #endif
  440 
  441         return (0);             /* XXX unused */
  442 }
  443 
  444 /*
  445  * Initialize floating point unit.
  446  */
  447 void
  448 npxinit(control)
  449         u_short control;
  450 {
  451         static union savefpu dummy;
  452         register_t savecrit;
  453 
  454         if (!npx_exists)
  455                 return;
  456         /*
  457          * fninit has the same h/w bugs as fnsave.  Use the detoxified
  458          * fnsave to throw away any junk in the fpu.  npxsave() initializes
  459          * the fpu and sets fpcurthread = NULL as important side effects.
  460          */
  461         savecrit = intr_disable();
  462         npxsave(&dummy);
  463         stop_emulating();
  464 #ifdef CPU_ENABLE_SSE
  465         /* XXX npxsave() doesn't actually initialize the fpu in the SSE case. */
  466         if (cpu_fxsr)
  467                 fninit();
  468 #endif
  469         fldcw(&control);
  470         start_emulating();
  471         intr_restore(savecrit);
  472 }
  473 
  474 /*
  475  * Free coprocessor (if we have it).
  476  */
  477 void
  478 npxexit(td)
  479         struct thread *td;
  480 {
  481         register_t savecrit;
  482 
  483         savecrit = intr_disable();
  484         if (curthread == PCPU_GET(fpcurthread))
  485                 npxsave(&PCPU_GET(curpcb)->pcb_save);
  486         intr_restore(savecrit);
  487 #ifdef NPX_DEBUG
  488         if (npx_exists) {
  489                 u_int   masked_exceptions;
  490 
  491                 masked_exceptions = GET_FPU_CW(td) & GET_FPU_SW(td) & 0x7f;
  492                 /*
  493                  * Log exceptions that would have trapped with the old
  494                  * control word (overflow, divide by 0, and invalid operand).
  495                  */
  496                 if (masked_exceptions & 0x0d)
  497                         log(LOG_ERR,
  498         "pid %d (%s) exited with masked floating point exceptions 0x%02x\n",
  499                             td->td_proc->p_pid, td->td_proc->p_comm,
  500                             masked_exceptions);
  501         }
  502 #endif
  503 }
  504 
  505 int
  506 npxformat()
  507 {
  508 
  509         if (!npx_exists)
  510                 return (_MC_FPFMT_NODEV);
  511 #ifdef  CPU_ENABLE_SSE
  512         if (cpu_fxsr)
  513                 return (_MC_FPFMT_XMM);
  514 #endif
  515         return (_MC_FPFMT_387);
  516 }
  517 
  518 /* 
  519  * The following mechanism is used to ensure that the FPE_... value
  520  * that is passed as a trapcode to the signal handler of the user
  521  * process does not have more than one bit set.
  522  * 
  523  * Multiple bits may be set if the user process modifies the control
  524  * word while a status word bit is already set.  While this is a sign
  525  * of bad coding, we have no choise than to narrow them down to one
  526  * bit, since we must not send a trapcode that is not exactly one of
  527  * the FPE_ macros.
  528  *
  529  * The mechanism has a static table with 127 entries.  Each combination
  530  * of the 7 FPU status word exception bits directly translates to a
  531  * position in this table, where a single FPE_... value is stored.
  532  * This FPE_... value stored there is considered the "most important"
  533  * of the exception bits and will be sent as the signal code.  The
  534  * precedence of the bits is based upon Intel Document "Numerical
  535  * Applications", Chapter "Special Computational Situations".
  536  *
  537  * The macro to choose one of these values does these steps: 1) Throw
  538  * away status word bits that cannot be masked.  2) Throw away the bits
  539  * currently masked in the control word, assuming the user isn't
  540  * interested in them anymore.  3) Reinsert status word bit 7 (stack
  541  * fault) if it is set, which cannot be masked but must be presered.
  542  * 4) Use the remaining bits to point into the trapcode table.
  543  *
  544  * The 6 maskable bits in order of their preference, as stated in the
  545  * above referenced Intel manual:
  546  * 1  Invalid operation (FP_X_INV)
  547  * 1a   Stack underflow
  548  * 1b   Stack overflow
  549  * 1c   Operand of unsupported format
  550  * 1d   SNaN operand.
  551  * 2  QNaN operand (not an exception, irrelavant here)
  552  * 3  Any other invalid-operation not mentioned above or zero divide
  553  *      (FP_X_INV, FP_X_DZ)
  554  * 4  Denormal operand (FP_X_DNML)
  555  * 5  Numeric over/underflow (FP_X_OFL, FP_X_UFL)
  556  * 6  Inexact result (FP_X_IMP) 
  557  */
  558 static char fpetable[128] = {
  559         0,
  560         FPE_FLTINV,     /*  1 - INV */
  561         FPE_FLTUND,     /*  2 - DNML */
  562         FPE_FLTINV,     /*  3 - INV | DNML */
  563         FPE_FLTDIV,     /*  4 - DZ */
  564         FPE_FLTINV,     /*  5 - INV | DZ */
  565         FPE_FLTDIV,     /*  6 - DNML | DZ */
  566         FPE_FLTINV,     /*  7 - INV | DNML | DZ */
  567         FPE_FLTOVF,     /*  8 - OFL */
  568         FPE_FLTINV,     /*  9 - INV | OFL */
  569         FPE_FLTUND,     /*  A - DNML | OFL */
  570         FPE_FLTINV,     /*  B - INV | DNML | OFL */
  571         FPE_FLTDIV,     /*  C - DZ | OFL */
  572         FPE_FLTINV,     /*  D - INV | DZ | OFL */
  573         FPE_FLTDIV,     /*  E - DNML | DZ | OFL */
  574         FPE_FLTINV,     /*  F - INV | DNML | DZ | OFL */
  575         FPE_FLTUND,     /* 10 - UFL */
  576         FPE_FLTINV,     /* 11 - INV | UFL */
  577         FPE_FLTUND,     /* 12 - DNML | UFL */
  578         FPE_FLTINV,     /* 13 - INV | DNML | UFL */
  579         FPE_FLTDIV,     /* 14 - DZ | UFL */
  580         FPE_FLTINV,     /* 15 - INV | DZ | UFL */
  581         FPE_FLTDIV,     /* 16 - DNML | DZ | UFL */
  582         FPE_FLTINV,     /* 17 - INV | DNML | DZ | UFL */
  583         FPE_FLTOVF,     /* 18 - OFL | UFL */
  584         FPE_FLTINV,     /* 19 - INV | OFL | UFL */
  585         FPE_FLTUND,     /* 1A - DNML | OFL | UFL */
  586         FPE_FLTINV,     /* 1B - INV | DNML | OFL | UFL */
  587         FPE_FLTDIV,     /* 1C - DZ | OFL | UFL */
  588         FPE_FLTINV,     /* 1D - INV | DZ | OFL | UFL */
  589         FPE_FLTDIV,     /* 1E - DNML | DZ | OFL | UFL */
  590         FPE_FLTINV,     /* 1F - INV | DNML | DZ | OFL | UFL */
  591         FPE_FLTRES,     /* 20 - IMP */
  592         FPE_FLTINV,     /* 21 - INV | IMP */
  593         FPE_FLTUND,     /* 22 - DNML | IMP */
  594         FPE_FLTINV,     /* 23 - INV | DNML | IMP */
  595         FPE_FLTDIV,     /* 24 - DZ | IMP */
  596         FPE_FLTINV,     /* 25 - INV | DZ | IMP */
  597         FPE_FLTDIV,     /* 26 - DNML | DZ | IMP */
  598         FPE_FLTINV,     /* 27 - INV | DNML | DZ | IMP */
  599         FPE_FLTOVF,     /* 28 - OFL | IMP */
  600         FPE_FLTINV,     /* 29 - INV | OFL | IMP */
  601         FPE_FLTUND,     /* 2A - DNML | OFL | IMP */
  602         FPE_FLTINV,     /* 2B - INV | DNML | OFL | IMP */
  603         FPE_FLTDIV,     /* 2C - DZ | OFL | IMP */
  604         FPE_FLTINV,     /* 2D - INV | DZ | OFL | IMP */
  605         FPE_FLTDIV,     /* 2E - DNML | DZ | OFL | IMP */
  606         FPE_FLTINV,     /* 2F - INV | DNML | DZ | OFL | IMP */
  607         FPE_FLTUND,     /* 30 - UFL | IMP */
  608         FPE_FLTINV,     /* 31 - INV | UFL | IMP */
  609         FPE_FLTUND,     /* 32 - DNML | UFL | IMP */
  610         FPE_FLTINV,     /* 33 - INV | DNML | UFL | IMP */
  611         FPE_FLTDIV,     /* 34 - DZ | UFL | IMP */
  612         FPE_FLTINV,     /* 35 - INV | DZ | UFL | IMP */
  613         FPE_FLTDIV,     /* 36 - DNML | DZ | UFL | IMP */
  614         FPE_FLTINV,     /* 37 - INV | DNML | DZ | UFL | IMP */
  615         FPE_FLTOVF,     /* 38 - OFL | UFL | IMP */
  616         FPE_FLTINV,     /* 39 - INV | OFL | UFL | IMP */
  617         FPE_FLTUND,     /* 3A - DNML | OFL | UFL | IMP */
  618         FPE_FLTINV,     /* 3B - INV | DNML | OFL | UFL | IMP */
  619         FPE_FLTDIV,     /* 3C - DZ | OFL | UFL | IMP */
  620         FPE_FLTINV,     /* 3D - INV | DZ | OFL | UFL | IMP */
  621         FPE_FLTDIV,     /* 3E - DNML | DZ | OFL | UFL | IMP */
  622         FPE_FLTINV,     /* 3F - INV | DNML | DZ | OFL | UFL | IMP */
  623         FPE_FLTSUB,     /* 40 - STK */
  624         FPE_FLTSUB,     /* 41 - INV | STK */
  625         FPE_FLTUND,     /* 42 - DNML | STK */
  626         FPE_FLTSUB,     /* 43 - INV | DNML | STK */
  627         FPE_FLTDIV,     /* 44 - DZ | STK */
  628         FPE_FLTSUB,     /* 45 - INV | DZ | STK */
  629         FPE_FLTDIV,     /* 46 - DNML | DZ | STK */
  630         FPE_FLTSUB,     /* 47 - INV | DNML | DZ | STK */
  631         FPE_FLTOVF,     /* 48 - OFL | STK */
  632         FPE_FLTSUB,     /* 49 - INV | OFL | STK */
  633         FPE_FLTUND,     /* 4A - DNML | OFL | STK */
  634         FPE_FLTSUB,     /* 4B - INV | DNML | OFL | STK */
  635         FPE_FLTDIV,     /* 4C - DZ | OFL | STK */
  636         FPE_FLTSUB,     /* 4D - INV | DZ | OFL | STK */
  637         FPE_FLTDIV,     /* 4E - DNML | DZ | OFL | STK */
  638         FPE_FLTSUB,     /* 4F - INV | DNML | DZ | OFL | STK */
  639         FPE_FLTUND,     /* 50 - UFL | STK */
  640         FPE_FLTSUB,     /* 51 - INV | UFL | STK */
  641         FPE_FLTUND,     /* 52 - DNML | UFL | STK */
  642         FPE_FLTSUB,     /* 53 - INV | DNML | UFL | STK */
  643         FPE_FLTDIV,     /* 54 - DZ | UFL | STK */
  644         FPE_FLTSUB,     /* 55 - INV | DZ | UFL | STK */
  645         FPE_FLTDIV,     /* 56 - DNML | DZ | UFL | STK */
  646         FPE_FLTSUB,     /* 57 - INV | DNML | DZ | UFL | STK */
  647         FPE_FLTOVF,     /* 58 - OFL | UFL | STK */
  648         FPE_FLTSUB,     /* 59 - INV | OFL | UFL | STK */
  649         FPE_FLTUND,     /* 5A - DNML | OFL | UFL | STK */
  650         FPE_FLTSUB,     /* 5B - INV | DNML | OFL | UFL | STK */
  651         FPE_FLTDIV,     /* 5C - DZ | OFL | UFL | STK */
  652         FPE_FLTSUB,     /* 5D - INV | DZ | OFL | UFL | STK */
  653         FPE_FLTDIV,     /* 5E - DNML | DZ | OFL | UFL | STK */
  654         FPE_FLTSUB,     /* 5F - INV | DNML | DZ | OFL | UFL | STK */
  655         FPE_FLTRES,     /* 60 - IMP | STK */
  656         FPE_FLTSUB,     /* 61 - INV | IMP | STK */
  657         FPE_FLTUND,     /* 62 - DNML | IMP | STK */
  658         FPE_FLTSUB,     /* 63 - INV | DNML | IMP | STK */
  659         FPE_FLTDIV,     /* 64 - DZ | IMP | STK */
  660         FPE_FLTSUB,     /* 65 - INV | DZ | IMP | STK */
  661         FPE_FLTDIV,     /* 66 - DNML | DZ | IMP | STK */
  662         FPE_FLTSUB,     /* 67 - INV | DNML | DZ | IMP | STK */
  663         FPE_FLTOVF,     /* 68 - OFL | IMP | STK */
  664         FPE_FLTSUB,     /* 69 - INV | OFL | IMP | STK */
  665         FPE_FLTUND,     /* 6A - DNML | OFL | IMP | STK */
  666         FPE_FLTSUB,     /* 6B - INV | DNML | OFL | IMP | STK */
  667         FPE_FLTDIV,     /* 6C - DZ | OFL | IMP | STK */
  668         FPE_FLTSUB,     /* 6D - INV | DZ | OFL | IMP | STK */
  669         FPE_FLTDIV,     /* 6E - DNML | DZ | OFL | IMP | STK */
  670         FPE_FLTSUB,     /* 6F - INV | DNML | DZ | OFL | IMP | STK */
  671         FPE_FLTUND,     /* 70 - UFL | IMP | STK */
  672         FPE_FLTSUB,     /* 71 - INV | UFL | IMP | STK */
  673         FPE_FLTUND,     /* 72 - DNML | UFL | IMP | STK */
  674         FPE_FLTSUB,     /* 73 - INV | DNML | UFL | IMP | STK */
  675         FPE_FLTDIV,     /* 74 - DZ | UFL | IMP | STK */
  676         FPE_FLTSUB,     /* 75 - INV | DZ | UFL | IMP | STK */
  677         FPE_FLTDIV,     /* 76 - DNML | DZ | UFL | IMP | STK */
  678         FPE_FLTSUB,     /* 77 - INV | DNML | DZ | UFL | IMP | STK */
  679         FPE_FLTOVF,     /* 78 - OFL | UFL | IMP | STK */
  680         FPE_FLTSUB,     /* 79 - INV | OFL | UFL | IMP | STK */
  681         FPE_FLTUND,     /* 7A - DNML | OFL | UFL | IMP | STK */
  682         FPE_FLTSUB,     /* 7B - INV | DNML | OFL | UFL | IMP | STK */
  683         FPE_FLTDIV,     /* 7C - DZ | OFL | UFL | IMP | STK */
  684         FPE_FLTSUB,     /* 7D - INV | DZ | OFL | UFL | IMP | STK */
  685         FPE_FLTDIV,     /* 7E - DNML | DZ | OFL | UFL | IMP | STK */
  686         FPE_FLTSUB,     /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */
  687 };
  688 
  689 /*
  690  * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE.
  691  *
  692  * Clearing exceptions is necessary mainly to avoid IRQ13 bugs.  We now
  693  * depend on longjmp() restoring a usable state.  Restoring the state
  694  * or examining it might fail if we didn't clear exceptions.
  695  *
  696  * The error code chosen will be one of the FPE_... macros. It will be
  697  * sent as the second argument to old BSD-style signal handlers and as
  698  * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers.
  699  *
  700  * XXX the FP state is not preserved across signal handlers.  So signal
  701  * handlers cannot afford to do FP unless they preserve the state or
  702  * longjmp() out.  Both preserving the state and longjmp()ing may be
  703  * destroyed by IRQ13 bugs.  Clearing FP exceptions is not an acceptable
  704  * solution for signals other than SIGFPE.
  705  */
  706 int
  707 npxtrap()
  708 {
  709         register_t savecrit;
  710         u_short control, status;
  711 
  712         if (!npx_exists) {
  713                 printf("npxtrap: fpcurthread = %p, curthread = %p, npx_exists = %d\n",
  714                        PCPU_GET(fpcurthread), curthread, npx_exists);
  715                 panic("npxtrap from nowhere");
  716         }
  717         savecrit = intr_disable();
  718 
  719         /*
  720          * Interrupt handling (for another interrupt) may have pushed the
  721          * state to memory.  Fetch the relevant parts of the state from
  722          * wherever they are.
  723          */
  724         if (PCPU_GET(fpcurthread) != curthread) {
  725                 control = GET_FPU_CW(curthread);
  726                 status = GET_FPU_SW(curthread);
  727         } else {
  728                 fnstcw(&control);
  729                 fnstsw(&status);
  730         }
  731 
  732         if (PCPU_GET(fpcurthread) == curthread)
  733                 fnclex();
  734         intr_restore(savecrit);
  735         return (fpetable[status & ((~control & 0x3f) | 0x40)]);
  736 }
  737 
  738 /*
  739  * Implement device not available (DNA) exception
  740  *
  741  * It would be better to switch FP context here (if curthread != fpcurthread)
  742  * and not necessarily for every context switch, but it is too hard to
  743  * access foreign pcb's.
  744  */
  745 
  746 static int err_count = 0;
  747 
  748 int
  749 npxdna()
  750 {
  751         struct pcb *pcb;
  752         register_t s;
  753 #ifdef CPU_ENABLE_SSE
  754         int mxcsr;
  755 #endif
  756         u_short control;
  757 
  758         if (!npx_exists)
  759                 return (0);
  760         if (PCPU_GET(fpcurthread) == curthread) {
  761                 printf("npxdna: fpcurthread == curthread %d times\n",
  762                     ++err_count);
  763                 stop_emulating();
  764                 return (1);
  765         }
  766         if (PCPU_GET(fpcurthread) != NULL) {
  767                 printf("npxdna: fpcurthread = %p (%d), curthread = %p (%d)\n",
  768                        PCPU_GET(fpcurthread),
  769                        PCPU_GET(fpcurthread)->td_proc->p_pid,
  770                        curthread, curthread->td_proc->p_pid);
  771                 panic("npxdna");
  772         }
  773         s = intr_disable();
  774         stop_emulating();
  775         /*
  776          * Record new context early in case frstor causes an IRQ13.
  777          */
  778         PCPU_SET(fpcurthread, curthread);
  779         pcb = PCPU_GET(curpcb);
  780 
  781         if ((pcb->pcb_flags & PCB_NPXINITDONE) == 0) {
  782                 /*
  783                  * This is the first time this thread has used the FPU or
  784                  * the PCB doesn't contain a clean FPU state.  Explicitly
  785                  * initialize the FPU and load the default control word.
  786                  */
  787                 fninit();
  788                 control = __INITIAL_NPXCW__;
  789                 fldcw(&control);
  790 #ifdef CPU_ENABLE_SSE
  791                 if (cpu_fxsr) {
  792                         mxcsr = __INITIAL_MXCSR__;
  793                         ldmxcsr(mxcsr);
  794                 }
  795 #endif
  796                 pcb->pcb_flags |= PCB_NPXINITDONE;
  797         } else {
  798                 /*
  799                  * The following frstor may cause an IRQ13 when the state
  800                  * being restored has a pending error.  The error will
  801                  * appear to have been triggered by the current (npx) user
  802                  * instruction even when that instruction is a no-wait
  803                  * instruction that should not trigger an error (e.g.,
  804                  * fnclex).  On at least one 486 system all of the no-wait
  805                  * instructions are broken the same as frstor, so our
  806                  * treatment does not amplify the breakage.  On at least
  807                  * one 386/Cyrix 387 system, fnclex works correctly while
  808                  * frstor and fnsave are broken, so our treatment breaks
  809                  * fnclex if it is the first FPU instruction after a context
  810                  * switch.
  811                  */
  812                 fpurstor(&pcb->pcb_save);
  813         }
  814         intr_restore(s);
  815 
  816         return (1);
  817 }
  818 
  819 /*
  820  * Wrapper for fnsave instruction, partly to handle hardware bugs.  When npx
  821  * exceptions are reported via IRQ13, spurious IRQ13's may be triggered by
  822  * no-wait npx instructions.  See the Intel application note AP-578 for
  823  * details.  This doesn't cause any additional complications here.  IRQ13's
  824  * are inherently asynchronous unless the CPU is frozen to deliver them --
  825  * one that started in userland may be delivered many instructions later,
  826  * after the process has entered the kernel.  It may even be delivered after
  827  * the fnsave here completes.  A spurious IRQ13 for the fnsave is handled in
  828  * the same way as a very-late-arriving non-spurious IRQ13 from user mode:
  829  * it is normally ignored at first because we set fpcurthread to NULL; it is
  830  * normally retriggered in npxdna() after return to user mode.
  831  *
  832  * npxsave() must be called with interrupts disabled, so that it clears
  833  * fpcurthread atomically with saving the state.  We require callers to do the
  834  * disabling, since most callers need to disable interrupts anyway to call
  835  * npxsave() atomically with checking fpcurthread.
  836  *
  837  * A previous version of npxsave() went to great lengths to excecute fnsave
  838  * with interrupts enabled in case executing it froze the CPU.  This case
  839  * can't happen, at least for Intel CPU/NPX's.  Spurious IRQ13's don't imply
  840  * spurious freezes.
  841  */
  842 void
  843 npxsave(addr)
  844         union savefpu *addr;
  845 {
  846 
  847         stop_emulating();
  848         fpusave(addr);
  849 
  850         start_emulating();
  851         PCPU_SET(fpcurthread, NULL);
  852 }
  853 
  854 /*
  855  * This should be called with interrupts disabled and only when the owning
  856  * FPU thread is non-null.
  857  */
  858 void
  859 npxdrop()
  860 {
  861         struct thread *td;
  862 
  863         /*
  864          * Discard pending exceptions in the !cpu_fxsr case so that unmasked
  865          * ones don't cause a panic on the next frstor.
  866          */
  867 #ifdef CPU_ENABLE_SSE
  868         if (!cpu_fxsr)
  869 #endif
  870                 fnclex();
  871 
  872         td = PCPU_GET(fpcurthread);
  873         PCPU_SET(fpcurthread, NULL);
  874         td->td_pcb->pcb_flags &= ~PCB_NPXINITDONE;
  875         start_emulating();
  876 }
  877 
  878 /*
  879  * Get the state of the FPU without dropping ownership (if possible).
  880  * It returns the FPU ownership status.
  881  */
  882 int
  883 npxgetregs(td, addr)
  884         struct thread *td;
  885         union savefpu *addr;
  886 {
  887         register_t s;
  888 
  889         if (!npx_exists)
  890                 return (_MC_FPOWNED_NONE);
  891 
  892         if ((td->td_pcb->pcb_flags & PCB_NPXINITDONE) == 0) {
  893                 if (npx_cleanstate_ready)
  894                         bcopy(&npx_cleanstate, addr, sizeof(npx_cleanstate));
  895                 else
  896                         bzero(addr, sizeof(*addr));
  897                 return (_MC_FPOWNED_NONE);
  898         }
  899         s = intr_disable();
  900         if (td == PCPU_GET(fpcurthread)) {
  901                 fpusave(addr);
  902 #ifdef CPU_ENABLE_SSE
  903                 if (!cpu_fxsr)
  904 #endif
  905                         /*
  906                          * fnsave initializes the FPU and destroys whatever
  907                          * context it contains.  Make sure the FPU owner
  908                          * starts with a clean state next time.
  909                          */
  910                         npxdrop();
  911                 intr_restore(s);
  912                 return (_MC_FPOWNED_FPU);
  913         } else {
  914                 intr_restore(s);
  915                 bcopy(&td->td_pcb->pcb_save, addr, sizeof(*addr));
  916                 return (_MC_FPOWNED_PCB);
  917         }
  918 }
  919 
  920 /*
  921  * Set the state of the FPU.
  922  */
  923 void
  924 npxsetregs(td, addr)
  925         struct thread *td;
  926         union savefpu *addr;
  927 {
  928         register_t s;
  929 
  930         if (!npx_exists)
  931                 return;
  932 
  933         s = intr_disable();
  934         if (td == PCPU_GET(fpcurthread)) {
  935 #ifdef CPU_ENABLE_SSE
  936                 if (!cpu_fxsr)
  937 #endif
  938                         fnclex();       /* As in npxdrop(). */
  939                 fpurstor(addr);
  940                 intr_restore(s);
  941         } else {
  942                 intr_restore(s);
  943                 bcopy(addr, &td->td_pcb->pcb_save, sizeof(*addr));
  944         }
  945         curthread->td_pcb->pcb_flags |= PCB_NPXINITDONE;
  946 }
  947 
  948 static void
  949 fpusave(addr)
  950         union savefpu *addr;
  951 {
  952         
  953 #ifdef CPU_ENABLE_SSE
  954         if (cpu_fxsr)
  955                 fxsave(addr);
  956         else
  957 #endif
  958                 fnsave(addr);
  959 }
  960 
  961 #ifdef CPU_ENABLE_SSE
  962 /*
  963  * On AuthenticAMD processors, the fxrstor instruction does not restore
  964  * the x87's stored last instruction pointer, last data pointer, and last
  965  * opcode values, except in the rare case in which the exception summary
  966  * (ES) bit in the x87 status word is set to 1.
  967  *
  968  * In order to avoid leaking this information across processes, we clean
  969  * these values by performing a dummy load before executing fxrstor().
  970  */
  971 static  double  dummy_variable = 0.0;
  972 static void
  973 fpu_clean_state(void)
  974 {
  975         u_short status;
  976 
  977         /*
  978          * Clear the ES bit in the x87 status word if it is currently
  979          * set, in order to avoid causing a fault in the upcoming load.
  980          */
  981         fnstsw(&status);
  982         if (status & 0x80)
  983                 fnclex();
  984 
  985         /*
  986          * Load the dummy variable into the x87 stack.  This mangles
  987          * the x87 stack, but we don't care since we're about to call
  988          * fxrstor() anyway.
  989          */
  990         __asm __volatile("ffree %%st(7); fld %0" : : "m" (dummy_variable));
  991 }
  992 #endif /* CPU_ENABLE_SSE */
  993 
  994 static void
  995 fpurstor(addr)
  996         union savefpu *addr;
  997 {
  998 
  999 #ifdef CPU_ENABLE_SSE
 1000         if (cpu_fxsr) {
 1001                 fpu_clean_state();
 1002                 fxrstor(addr);
 1003         } else
 1004 #endif
 1005                 frstor(addr);
 1006 }
 1007 
 1008 #ifdef I586_CPU_XXX
 1009 static long
 1010 timezero(funcname, func)
 1011         const char *funcname;
 1012         void (*func)(void *buf, size_t len);
 1013 
 1014 {
 1015         void *buf;
 1016 #define BUFSIZE         1048576
 1017         long usec;
 1018         struct timeval finish, start;
 1019 
 1020         buf = malloc(BUFSIZE, M_TEMP, M_NOWAIT);
 1021         if (buf == NULL)
 1022                 return (BUFSIZE);
 1023         microtime(&start);
 1024         (*func)(buf, BUFSIZE);
 1025         microtime(&finish);
 1026         usec = 1000000 * (finish.tv_sec - start.tv_sec) +
 1027             finish.tv_usec - start.tv_usec;
 1028         if (usec <= 0)
 1029                 usec = 1;
 1030         if (bootverbose)
 1031                 printf("%s bandwidth = %u kBps\n", funcname,
 1032                     (u_int32_t)(((BUFSIZE >> 10) * 1000000) / usec));
 1033         free(buf, M_TEMP);
 1034         return (usec);
 1035 }
 1036 #endif /* I586_CPU */
 1037 
 1038 static device_method_t npx_methods[] = {
 1039         /* Device interface */
 1040         DEVMETHOD(device_identify,      npx_identify),
 1041         DEVMETHOD(device_probe,         npx_probe),
 1042         DEVMETHOD(device_attach,        npx_attach),
 1043         DEVMETHOD(device_detach,        bus_generic_detach),
 1044         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
 1045         DEVMETHOD(device_suspend,       bus_generic_suspend),
 1046         DEVMETHOD(device_resume,        bus_generic_resume),
 1047         
 1048         { 0, 0 }
 1049 };
 1050 
 1051 static driver_t npx_driver = {
 1052         "npx",
 1053         npx_methods,
 1054         1,                      /* no softc */
 1055 };
 1056 
 1057 static devclass_t npx_devclass;
 1058 
 1059 /*
 1060  * We prefer to attach to the root nexus so that the usual case (exception 16)
 1061  * doesn't describe the processor as being `on isa'.
 1062  */
 1063 DRIVER_MODULE(npx, nexus, npx_driver, npx_devclass, 0, 0);
 1064 
 1065 #ifdef DEV_ISA
 1066 /*
 1067  * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI.
 1068  */
 1069 static struct isa_pnp_id npxisa_ids[] = {
 1070         { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */
 1071         { 0 }
 1072 };
 1073 
 1074 static int
 1075 npxisa_probe(device_t dev)
 1076 {
 1077         int result;
 1078         if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, npxisa_ids)) <= 0) {
 1079                 device_quiet(dev);
 1080         }
 1081         return(result);
 1082 }
 1083 
 1084 static int
 1085 npxisa_attach(device_t dev)
 1086 {
 1087         return (0);
 1088 }
 1089 
 1090 static device_method_t npxisa_methods[] = {
 1091         /* Device interface */
 1092         DEVMETHOD(device_probe,         npxisa_probe),
 1093         DEVMETHOD(device_attach,        npxisa_attach),
 1094         DEVMETHOD(device_detach,        bus_generic_detach),
 1095         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
 1096         DEVMETHOD(device_suspend,       bus_generic_suspend),
 1097         DEVMETHOD(device_resume,        bus_generic_resume),
 1098         
 1099         { 0, 0 }
 1100 };
 1101 
 1102 static driver_t npxisa_driver = {
 1103         "npxisa",
 1104         npxisa_methods,
 1105         1,                      /* no softc */
 1106 };
 1107 
 1108 static devclass_t npxisa_devclass;
 1109 
 1110 DRIVER_MODULE(npxisa, isa, npxisa_driver, npxisa_devclass, 0, 0);
 1111 #ifndef PC98
 1112 DRIVER_MODULE(npxisa, acpi, npxisa_driver, npxisa_devclass, 0, 0);
 1113 #endif
 1114 #endif /* DEV_ISA */

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