FreeBSD/Linux Kernel Cross Reference
sys/i386/isa/npx.c
1 /*-
2 * Copyright (c) 1990 William Jolitz.
3 * Copyright (c) 1991 The Regents of the University of California.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 4. Neither the name of the University nor the names of its contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91
31 */
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD: releng/6.1/sys/i386/isa/npx.c 158164 2006-04-30 05:17:59Z kensmith $");
35
36 #include "opt_cpu.h"
37 #include "opt_isa.h"
38 #include "opt_npx.h"
39
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #include <sys/bus.h>
43 #include <sys/kernel.h>
44 #include <sys/lock.h>
45 #include <sys/malloc.h>
46 #include <sys/module.h>
47 #include <sys/mutex.h>
48 #include <sys/mutex.h>
49 #include <sys/proc.h>
50 #include <sys/smp.h>
51 #include <sys/sysctl.h>
52 #include <machine/bus.h>
53 #include <sys/rman.h>
54 #ifdef NPX_DEBUG
55 #include <sys/syslog.h>
56 #endif
57 #include <sys/signalvar.h>
58
59 #include <machine/asmacros.h>
60 #include <machine/cputypes.h>
61 #include <machine/frame.h>
62 #include <machine/md_var.h>
63 #include <machine/pcb.h>
64 #include <machine/psl.h>
65 #include <machine/clock.h>
66 #include <machine/resource.h>
67 #include <machine/specialreg.h>
68 #include <machine/segments.h>
69 #include <machine/ucontext.h>
70
71 #include <machine/intr_machdep.h>
72 #ifdef DEV_ISA
73 #include <isa/isavar.h>
74 #endif
75
76 #if !defined(CPU_DISABLE_SSE) && defined(I686_CPU)
77 #define CPU_ENABLE_SSE
78 #endif
79
80 /*
81 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver.
82 */
83
84 /* Configuration flags. */
85 #define NPX_DISABLE_I586_OPTIMIZED_BCOPY (1 << 0)
86 #define NPX_DISABLE_I586_OPTIMIZED_BZERO (1 << 1)
87 #define NPX_DISABLE_I586_OPTIMIZED_COPYIO (1 << 2)
88
89 #if defined(__GNUCLIKE_ASM) && !defined(lint)
90
91 #define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr)))
92 #define fnclex() __asm("fnclex")
93 #define fninit() __asm("fninit")
94 #define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr)))
95 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr)))
96 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr)))
97 #define fp_divide_by_0() __asm("fldz; fld1; fdiv %st,%st(1); fnop")
98 #define frstor(addr) __asm("frstor %0" : : "m" (*(addr)))
99 #ifdef CPU_ENABLE_SSE
100 #define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr)))
101 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr)))
102 #define ldmxcsr(__csr) __asm __volatile("ldmxcsr %0" : : "m" (__csr))
103 #endif
104 #define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \
105 : : "n" (CR0_TS) : "ax")
106 #define stop_emulating() __asm("clts")
107
108 #else /* !(__GNUCLIKE_ASM && !lint) */
109
110 void fldcw(caddr_t addr);
111 void fnclex(void);
112 void fninit(void);
113 void fnsave(caddr_t addr);
114 void fnstcw(caddr_t addr);
115 void fnstsw(caddr_t addr);
116 void fp_divide_by_0(void);
117 void frstor(caddr_t addr);
118 #ifdef CPU_ENABLE_SSE
119 void fxsave(caddr_t addr);
120 void fxrstor(caddr_t addr);
121 #endif
122 void start_emulating(void);
123 void stop_emulating(void);
124
125 #endif /* __GNUCLIKE_ASM && !lint */
126
127 #ifdef CPU_ENABLE_SSE
128 #define GET_FPU_CW(thread) \
129 (cpu_fxsr ? \
130 (thread)->td_pcb->pcb_save.sv_xmm.sv_env.en_cw : \
131 (thread)->td_pcb->pcb_save.sv_87.sv_env.en_cw)
132 #define GET_FPU_SW(thread) \
133 (cpu_fxsr ? \
134 (thread)->td_pcb->pcb_save.sv_xmm.sv_env.en_sw : \
135 (thread)->td_pcb->pcb_save.sv_87.sv_env.en_sw)
136 #else /* CPU_ENABLE_SSE */
137 #define GET_FPU_CW(thread) \
138 (thread->td_pcb->pcb_save.sv_87.sv_env.en_cw)
139 #define GET_FPU_SW(thread) \
140 (thread->td_pcb->pcb_save.sv_87.sv_env.en_sw)
141 #endif /* CPU_ENABLE_SSE */
142
143 typedef u_char bool_t;
144
145 #ifdef CPU_ENABLE_SSE
146 static void fpu_clean_state(void);
147 #endif
148
149 static void fpusave(union savefpu *);
150 static void fpurstor(union savefpu *);
151 static int npx_attach(device_t dev);
152 static void npx_identify(driver_t *driver, device_t parent);
153 static void npx_intr(void *);
154 static int npx_probe(device_t dev);
155 #ifdef I586_CPU_XXX
156 static long timezero(const char *funcname,
157 void (*func)(void *buf, size_t len));
158 #endif /* I586_CPU */
159
160 int hw_float; /* XXX currently just alias for npx_exists */
161
162 SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint,
163 CTLFLAG_RD, &hw_float, 0,
164 "Floatingpoint instructions executed in hardware");
165
166 static volatile u_int npx_intrs_while_probing;
167 static volatile u_int npx_traps_while_probing;
168
169 static union savefpu npx_cleanstate;
170 static bool_t npx_cleanstate_ready;
171 static bool_t npx_ex16;
172 static bool_t npx_exists;
173 static bool_t npx_irq13;
174
175 alias_for_inthand_t probetrap;
176 __asm(" \n\
177 .text \n\
178 .p2align 2,0x90 \n\
179 .type " __XSTRING(CNAME(probetrap)) ",@function \n\
180 " __XSTRING(CNAME(probetrap)) ": \n\
181 ss \n\
182 incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\
183 fnclex \n\
184 iret \n\
185 ");
186
187 /*
188 * Identify routine. Create a connection point on our parent for probing.
189 */
190 static void
191 npx_identify(driver, parent)
192 driver_t *driver;
193 device_t parent;
194 {
195 device_t child;
196
197 child = BUS_ADD_CHILD(parent, 0, "npx", 0);
198 if (child == NULL)
199 panic("npx_identify");
200 }
201
202 /*
203 * Do minimal handling of npx interrupts to convert them to traps.
204 */
205 static void
206 npx_intr(dummy)
207 void *dummy;
208 {
209 struct thread *td;
210
211 npx_intrs_while_probing++;
212
213 /*
214 * The BUSY# latch must be cleared in all cases so that the next
215 * unmasked npx exception causes an interrupt.
216 */
217 outb(IO_NPX, 0);
218
219 /*
220 * fpcurthread is normally non-null here. In that case, schedule an
221 * AST to finish the exception handling in the correct context
222 * (this interrupt may occur after the thread has entered the
223 * kernel via a syscall or an interrupt). Otherwise, the npx
224 * state of the thread that caused this interrupt must have been
225 * pushed to the thread's pcb, and clearing of the busy latch
226 * above has finished the (essentially null) handling of this
227 * interrupt. Control will eventually return to the instruction
228 * that caused it and it will repeat. We will eventually (usually
229 * soon) win the race to handle the interrupt properly.
230 */
231 td = PCPU_GET(fpcurthread);
232 if (td != NULL) {
233 td->td_pcb->pcb_flags |= PCB_NPXTRAP;
234 mtx_lock_spin(&sched_lock);
235 td->td_flags |= TDF_ASTPENDING;
236 mtx_unlock_spin(&sched_lock);
237 }
238 }
239
240 /*
241 * Probe routine. Set flags to tell npxattach() what to do. Set up an
242 * interrupt handler if npx needs to use interrupts.
243 */
244 static int
245 npx_probe(dev)
246 device_t dev;
247 {
248 struct gate_descriptor save_idt_npxtrap;
249 struct resource *ioport_res, *irq_res;
250 void *irq_cookie;
251 int ioport_rid, irq_num, irq_rid;
252 u_short control;
253 u_short status;
254
255 device_set_desc(dev, "math processor");
256
257 /*
258 * Modern CPUs all have an FPU that uses the INT16 interface
259 * and provide a simple way to verify that, so handle the
260 * common case right away.
261 */
262 if (cpu_feature & CPUID_FPU) {
263 hw_float = npx_exists = 1;
264 npx_ex16 = 1;
265 device_quiet(dev);
266 return (0);
267 }
268
269 save_idt_npxtrap = idt[IDT_MF];
270 setidt(IDT_MF, probetrap, SDT_SYS386TGT, SEL_KPL,
271 GSEL(GCODE_SEL, SEL_KPL));
272 ioport_rid = 0;
273 ioport_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &ioport_rid,
274 IO_NPX, IO_NPX + IO_NPXSIZE - 1, IO_NPXSIZE, RF_ACTIVE);
275 if (ioport_res == NULL)
276 panic("npx: can't get ports");
277 if (resource_int_value("npx", 0, "irq", &irq_num) != 0)
278 irq_num = IRQ_NPX;
279 irq_rid = 0;
280 irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &irq_rid, irq_num,
281 irq_num, 1, RF_ACTIVE);
282 if (irq_res != NULL) {
283 if (bus_setup_intr(dev, irq_res, INTR_TYPE_MISC | INTR_FAST,
284 npx_intr, NULL, &irq_cookie) != 0)
285 panic("npx: can't create intr");
286 }
287
288 /*
289 * Partially reset the coprocessor, if any. Some BIOS's don't reset
290 * it after a warm boot.
291 */
292 npx_full_reset();
293 outb(IO_NPX, 0);
294
295 /*
296 * Don't trap while we're probing.
297 */
298 stop_emulating();
299
300 /*
301 * Finish resetting the coprocessor, if any. If there is an error
302 * pending, then we may get a bogus IRQ13, but npx_intr() will handle
303 * it OK. Bogus halts have never been observed, but we enabled
304 * IRQ13 and cleared the BUSY# latch early to handle them anyway.
305 */
306 fninit();
307
308 /*
309 * Don't use fwait here because it might hang.
310 * Don't use fnop here because it usually hangs if there is no FPU.
311 */
312 DELAY(1000); /* wait for any IRQ13 */
313 #ifdef DIAGNOSTIC
314 if (npx_intrs_while_probing != 0)
315 printf("fninit caused %u bogus npx interrupt(s)\n",
316 npx_intrs_while_probing);
317 if (npx_traps_while_probing != 0)
318 printf("fninit caused %u bogus npx trap(s)\n",
319 npx_traps_while_probing);
320 #endif
321 /*
322 * Check for a status of mostly zero.
323 */
324 status = 0x5a5a;
325 fnstsw(&status);
326 if ((status & 0xb8ff) == 0) {
327 /*
328 * Good, now check for a proper control word.
329 */
330 control = 0x5a5a;
331 fnstcw(&control);
332 if ((control & 0x1f3f) == 0x033f) {
333 hw_float = npx_exists = 1;
334 /*
335 * We have an npx, now divide by 0 to see if exception
336 * 16 works.
337 */
338 control &= ~(1 << 2); /* enable divide by 0 trap */
339 fldcw(&control);
340 #ifdef FPU_ERROR_BROKEN
341 /*
342 * FPU error signal doesn't work on some CPU
343 * accelerator board.
344 */
345 npx_ex16 = 1;
346 return (0);
347 #endif
348 npx_traps_while_probing = npx_intrs_while_probing = 0;
349 fp_divide_by_0();
350 DELAY(1000); /* wait for any IRQ13 */
351 if (npx_traps_while_probing != 0) {
352 /*
353 * Good, exception 16 works.
354 */
355 npx_ex16 = 1;
356 goto no_irq13;
357 }
358 if (npx_intrs_while_probing != 0) {
359 /*
360 * Bad, we are stuck with IRQ13.
361 */
362 npx_irq13 = 1;
363 idt[IDT_MF] = save_idt_npxtrap;
364 #ifdef SMP
365 if (mp_ncpus > 1)
366 panic("npx0 cannot use IRQ 13 on an SMP system");
367 #endif
368 return (0);
369 }
370 /*
371 * Worse, even IRQ13 is broken. Use emulator.
372 */
373 }
374 }
375 /*
376 * Probe failed, but we want to get to npxattach to initialize the
377 * emulator and say that it has been installed. XXX handle devices
378 * that aren't really devices better.
379 */
380 #ifdef SMP
381 if (mp_ncpus > 1)
382 panic("npx0 cannot be emulated on an SMP system");
383 #endif
384 /* FALLTHROUGH */
385 no_irq13:
386 idt[IDT_MF] = save_idt_npxtrap;
387 if (irq_res != NULL) {
388 bus_teardown_intr(dev, irq_res, irq_cookie);
389 bus_release_resource(dev, SYS_RES_IRQ, irq_rid, irq_res);
390 }
391 bus_release_resource(dev, SYS_RES_IOPORT, ioport_rid, ioport_res);
392 return (0);
393 }
394
395 /*
396 * Attach routine - announce which it is, and wire into system
397 */
398 static int
399 npx_attach(dev)
400 device_t dev;
401 {
402 int flags;
403 register_t s;
404
405 flags = device_get_flags(dev);
406
407 if (npx_irq13)
408 device_printf(dev, "IRQ 13 interface\n");
409 else if (!npx_ex16)
410 device_printf(dev, "WARNING: no FPU!\n");
411 else if (!device_is_quiet(dev) || bootverbose)
412 device_printf(dev, "INT 16 interface\n");
413
414 npxinit(__INITIAL_NPXCW__);
415
416 if (npx_cleanstate_ready == 0) {
417 s = intr_disable();
418 stop_emulating();
419 fpusave(&npx_cleanstate);
420 start_emulating();
421 npx_cleanstate_ready = 1;
422 intr_restore(s);
423 }
424 #ifdef I586_CPU_XXX
425 if (cpu_class == CPUCLASS_586 && npx_ex16 && npx_exists &&
426 timezero("i586_bzero()", i586_bzero) <
427 timezero("bzero()", bzero) * 4 / 5) {
428 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY))
429 bcopy_vector = i586_bcopy;
430 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BZERO))
431 bzero_vector = i586_bzero;
432 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_COPYIO)) {
433 copyin_vector = i586_copyin;
434 copyout_vector = i586_copyout;
435 }
436 }
437 #endif
438
439 return (0); /* XXX unused */
440 }
441
442 /*
443 * Initialize floating point unit.
444 */
445 void
446 npxinit(control)
447 u_short control;
448 {
449 static union savefpu dummy;
450 register_t savecrit;
451
452 if (!npx_exists)
453 return;
454 /*
455 * fninit has the same h/w bugs as fnsave. Use the detoxified
456 * fnsave to throw away any junk in the fpu. npxsave() initializes
457 * the fpu and sets fpcurthread = NULL as important side effects.
458 */
459 savecrit = intr_disable();
460 npxsave(&dummy);
461 stop_emulating();
462 #ifdef CPU_ENABLE_SSE
463 /* XXX npxsave() doesn't actually initialize the fpu in the SSE case. */
464 if (cpu_fxsr)
465 fninit();
466 #endif
467 fldcw(&control);
468 start_emulating();
469 intr_restore(savecrit);
470 }
471
472 /*
473 * Free coprocessor (if we have it).
474 */
475 void
476 npxexit(td)
477 struct thread *td;
478 {
479 register_t savecrit;
480
481 savecrit = intr_disable();
482 if (curthread == PCPU_GET(fpcurthread))
483 npxsave(&PCPU_GET(curpcb)->pcb_save);
484 intr_restore(savecrit);
485 #ifdef NPX_DEBUG
486 if (npx_exists) {
487 u_int masked_exceptions;
488
489 masked_exceptions = GET_FPU_CW(td) & GET_FPU_SW(td) & 0x7f;
490 /*
491 * Log exceptions that would have trapped with the old
492 * control word (overflow, divide by 0, and invalid operand).
493 */
494 if (masked_exceptions & 0x0d)
495 log(LOG_ERR,
496 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n",
497 td->td_proc->p_pid, td->td_proc->p_comm,
498 masked_exceptions);
499 }
500 #endif
501 }
502
503 int
504 npxformat()
505 {
506
507 if (!npx_exists)
508 return (_MC_FPFMT_NODEV);
509 #ifdef CPU_ENABLE_SSE
510 if (cpu_fxsr)
511 return (_MC_FPFMT_XMM);
512 #endif
513 return (_MC_FPFMT_387);
514 }
515
516 /*
517 * The following mechanism is used to ensure that the FPE_... value
518 * that is passed as a trapcode to the signal handler of the user
519 * process does not have more than one bit set.
520 *
521 * Multiple bits may be set if the user process modifies the control
522 * word while a status word bit is already set. While this is a sign
523 * of bad coding, we have no choise than to narrow them down to one
524 * bit, since we must not send a trapcode that is not exactly one of
525 * the FPE_ macros.
526 *
527 * The mechanism has a static table with 127 entries. Each combination
528 * of the 7 FPU status word exception bits directly translates to a
529 * position in this table, where a single FPE_... value is stored.
530 * This FPE_... value stored there is considered the "most important"
531 * of the exception bits and will be sent as the signal code. The
532 * precedence of the bits is based upon Intel Document "Numerical
533 * Applications", Chapter "Special Computational Situations".
534 *
535 * The macro to choose one of these values does these steps: 1) Throw
536 * away status word bits that cannot be masked. 2) Throw away the bits
537 * currently masked in the control word, assuming the user isn't
538 * interested in them anymore. 3) Reinsert status word bit 7 (stack
539 * fault) if it is set, which cannot be masked but must be presered.
540 * 4) Use the remaining bits to point into the trapcode table.
541 *
542 * The 6 maskable bits in order of their preference, as stated in the
543 * above referenced Intel manual:
544 * 1 Invalid operation (FP_X_INV)
545 * 1a Stack underflow
546 * 1b Stack overflow
547 * 1c Operand of unsupported format
548 * 1d SNaN operand.
549 * 2 QNaN operand (not an exception, irrelavant here)
550 * 3 Any other invalid-operation not mentioned above or zero divide
551 * (FP_X_INV, FP_X_DZ)
552 * 4 Denormal operand (FP_X_DNML)
553 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL)
554 * 6 Inexact result (FP_X_IMP)
555 */
556 static char fpetable[128] = {
557 0,
558 FPE_FLTINV, /* 1 - INV */
559 FPE_FLTUND, /* 2 - DNML */
560 FPE_FLTINV, /* 3 - INV | DNML */
561 FPE_FLTDIV, /* 4 - DZ */
562 FPE_FLTINV, /* 5 - INV | DZ */
563 FPE_FLTDIV, /* 6 - DNML | DZ */
564 FPE_FLTINV, /* 7 - INV | DNML | DZ */
565 FPE_FLTOVF, /* 8 - OFL */
566 FPE_FLTINV, /* 9 - INV | OFL */
567 FPE_FLTUND, /* A - DNML | OFL */
568 FPE_FLTINV, /* B - INV | DNML | OFL */
569 FPE_FLTDIV, /* C - DZ | OFL */
570 FPE_FLTINV, /* D - INV | DZ | OFL */
571 FPE_FLTDIV, /* E - DNML | DZ | OFL */
572 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */
573 FPE_FLTUND, /* 10 - UFL */
574 FPE_FLTINV, /* 11 - INV | UFL */
575 FPE_FLTUND, /* 12 - DNML | UFL */
576 FPE_FLTINV, /* 13 - INV | DNML | UFL */
577 FPE_FLTDIV, /* 14 - DZ | UFL */
578 FPE_FLTINV, /* 15 - INV | DZ | UFL */
579 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */
580 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */
581 FPE_FLTOVF, /* 18 - OFL | UFL */
582 FPE_FLTINV, /* 19 - INV | OFL | UFL */
583 FPE_FLTUND, /* 1A - DNML | OFL | UFL */
584 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */
585 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */
586 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */
587 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */
588 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */
589 FPE_FLTRES, /* 20 - IMP */
590 FPE_FLTINV, /* 21 - INV | IMP */
591 FPE_FLTUND, /* 22 - DNML | IMP */
592 FPE_FLTINV, /* 23 - INV | DNML | IMP */
593 FPE_FLTDIV, /* 24 - DZ | IMP */
594 FPE_FLTINV, /* 25 - INV | DZ | IMP */
595 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */
596 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */
597 FPE_FLTOVF, /* 28 - OFL | IMP */
598 FPE_FLTINV, /* 29 - INV | OFL | IMP */
599 FPE_FLTUND, /* 2A - DNML | OFL | IMP */
600 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */
601 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */
602 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */
603 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */
604 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */
605 FPE_FLTUND, /* 30 - UFL | IMP */
606 FPE_FLTINV, /* 31 - INV | UFL | IMP */
607 FPE_FLTUND, /* 32 - DNML | UFL | IMP */
608 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */
609 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */
610 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */
611 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */
612 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */
613 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */
614 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */
615 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */
616 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */
617 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */
618 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */
619 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */
620 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */
621 FPE_FLTSUB, /* 40 - STK */
622 FPE_FLTSUB, /* 41 - INV | STK */
623 FPE_FLTUND, /* 42 - DNML | STK */
624 FPE_FLTSUB, /* 43 - INV | DNML | STK */
625 FPE_FLTDIV, /* 44 - DZ | STK */
626 FPE_FLTSUB, /* 45 - INV | DZ | STK */
627 FPE_FLTDIV, /* 46 - DNML | DZ | STK */
628 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */
629 FPE_FLTOVF, /* 48 - OFL | STK */
630 FPE_FLTSUB, /* 49 - INV | OFL | STK */
631 FPE_FLTUND, /* 4A - DNML | OFL | STK */
632 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */
633 FPE_FLTDIV, /* 4C - DZ | OFL | STK */
634 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */
635 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */
636 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */
637 FPE_FLTUND, /* 50 - UFL | STK */
638 FPE_FLTSUB, /* 51 - INV | UFL | STK */
639 FPE_FLTUND, /* 52 - DNML | UFL | STK */
640 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */
641 FPE_FLTDIV, /* 54 - DZ | UFL | STK */
642 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */
643 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */
644 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */
645 FPE_FLTOVF, /* 58 - OFL | UFL | STK */
646 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */
647 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */
648 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */
649 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */
650 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */
651 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */
652 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */
653 FPE_FLTRES, /* 60 - IMP | STK */
654 FPE_FLTSUB, /* 61 - INV | IMP | STK */
655 FPE_FLTUND, /* 62 - DNML | IMP | STK */
656 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */
657 FPE_FLTDIV, /* 64 - DZ | IMP | STK */
658 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */
659 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */
660 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */
661 FPE_FLTOVF, /* 68 - OFL | IMP | STK */
662 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */
663 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */
664 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */
665 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */
666 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */
667 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */
668 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */
669 FPE_FLTUND, /* 70 - UFL | IMP | STK */
670 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */
671 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */
672 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */
673 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */
674 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */
675 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */
676 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */
677 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */
678 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */
679 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */
680 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */
681 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */
682 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */
683 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */
684 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */
685 };
686
687 /*
688 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE.
689 *
690 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now
691 * depend on longjmp() restoring a usable state. Restoring the state
692 * or examining it might fail if we didn't clear exceptions.
693 *
694 * The error code chosen will be one of the FPE_... macros. It will be
695 * sent as the second argument to old BSD-style signal handlers and as
696 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers.
697 *
698 * XXX the FP state is not preserved across signal handlers. So signal
699 * handlers cannot afford to do FP unless they preserve the state or
700 * longjmp() out. Both preserving the state and longjmp()ing may be
701 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable
702 * solution for signals other than SIGFPE.
703 */
704 int
705 npxtrap()
706 {
707 register_t savecrit;
708 u_short control, status;
709
710 if (!npx_exists) {
711 printf("npxtrap: fpcurthread = %p, curthread = %p, npx_exists = %d\n",
712 PCPU_GET(fpcurthread), curthread, npx_exists);
713 panic("npxtrap from nowhere");
714 }
715 savecrit = intr_disable();
716
717 /*
718 * Interrupt handling (for another interrupt) may have pushed the
719 * state to memory. Fetch the relevant parts of the state from
720 * wherever they are.
721 */
722 if (PCPU_GET(fpcurthread) != curthread) {
723 control = GET_FPU_CW(curthread);
724 status = GET_FPU_SW(curthread);
725 } else {
726 fnstcw(&control);
727 fnstsw(&status);
728 }
729
730 if (PCPU_GET(fpcurthread) == curthread)
731 fnclex();
732 intr_restore(savecrit);
733 return (fpetable[status & ((~control & 0x3f) | 0x40)]);
734 }
735
736 /*
737 * Implement device not available (DNA) exception
738 *
739 * It would be better to switch FP context here (if curthread != fpcurthread)
740 * and not necessarily for every context switch, but it is too hard to
741 * access foreign pcb's.
742 */
743
744 static int err_count = 0;
745
746 int
747 npxdna()
748 {
749 struct pcb *pcb;
750 register_t s;
751 #ifdef CPU_ENABLE_SSE
752 int mxcsr;
753 #endif
754 u_short control;
755
756 if (!npx_exists)
757 return (0);
758 if (PCPU_GET(fpcurthread) == curthread) {
759 printf("npxdna: fpcurthread == curthread %d times\n",
760 ++err_count);
761 stop_emulating();
762 return (1);
763 }
764 if (PCPU_GET(fpcurthread) != NULL) {
765 printf("npxdna: fpcurthread = %p (%d), curthread = %p (%d)\n",
766 PCPU_GET(fpcurthread),
767 PCPU_GET(fpcurthread)->td_proc->p_pid,
768 curthread, curthread->td_proc->p_pid);
769 panic("npxdna");
770 }
771 s = intr_disable();
772 stop_emulating();
773 /*
774 * Record new context early in case frstor causes an IRQ13.
775 */
776 PCPU_SET(fpcurthread, curthread);
777 pcb = PCPU_GET(curpcb);
778
779 if ((pcb->pcb_flags & PCB_NPXINITDONE) == 0) {
780 /*
781 * This is the first time this thread has used the FPU or
782 * the PCB doesn't contain a clean FPU state. Explicitly
783 * initialize the FPU and load the default control word.
784 */
785 fninit();
786 control = __INITIAL_NPXCW__;
787 fldcw(&control);
788 #ifdef CPU_ENABLE_SSE
789 if (cpu_fxsr) {
790 mxcsr = __INITIAL_MXCSR__;
791 ldmxcsr(mxcsr);
792 }
793 #endif
794 pcb->pcb_flags |= PCB_NPXINITDONE;
795 } else {
796 /*
797 * The following frstor may cause an IRQ13 when the state
798 * being restored has a pending error. The error will
799 * appear to have been triggered by the current (npx) user
800 * instruction even when that instruction is a no-wait
801 * instruction that should not trigger an error (e.g.,
802 * fnclex). On at least one 486 system all of the no-wait
803 * instructions are broken the same as frstor, so our
804 * treatment does not amplify the breakage. On at least
805 * one 386/Cyrix 387 system, fnclex works correctly while
806 * frstor and fnsave are broken, so our treatment breaks
807 * fnclex if it is the first FPU instruction after a context
808 * switch.
809 */
810 fpurstor(&pcb->pcb_save);
811 }
812 intr_restore(s);
813
814 return (1);
815 }
816
817 /*
818 * Wrapper for fnsave instruction, partly to handle hardware bugs. When npx
819 * exceptions are reported via IRQ13, spurious IRQ13's may be triggered by
820 * no-wait npx instructions. See the Intel application note AP-578 for
821 * details. This doesn't cause any additional complications here. IRQ13's
822 * are inherently asynchronous unless the CPU is frozen to deliver them --
823 * one that started in userland may be delivered many instructions later,
824 * after the process has entered the kernel. It may even be delivered after
825 * the fnsave here completes. A spurious IRQ13 for the fnsave is handled in
826 * the same way as a very-late-arriving non-spurious IRQ13 from user mode:
827 * it is normally ignored at first because we set fpcurthread to NULL; it is
828 * normally retriggered in npxdna() after return to user mode.
829 *
830 * npxsave() must be called with interrupts disabled, so that it clears
831 * fpcurthread atomically with saving the state. We require callers to do the
832 * disabling, since most callers need to disable interrupts anyway to call
833 * npxsave() atomically with checking fpcurthread.
834 *
835 * A previous version of npxsave() went to great lengths to excecute fnsave
836 * with interrupts enabled in case executing it froze the CPU. This case
837 * can't happen, at least for Intel CPU/NPX's. Spurious IRQ13's don't imply
838 * spurious freezes.
839 */
840 void
841 npxsave(addr)
842 union savefpu *addr;
843 {
844
845 stop_emulating();
846 fpusave(addr);
847
848 start_emulating();
849 PCPU_SET(fpcurthread, NULL);
850 }
851
852 /*
853 * This should be called with interrupts disabled and only when the owning
854 * FPU thread is non-null.
855 */
856 void
857 npxdrop()
858 {
859 struct thread *td;
860
861 /*
862 * Discard pending exceptions in the !cpu_fxsr case so that unmasked
863 * ones don't cause a panic on the next frstor.
864 */
865 #ifdef CPU_ENABLE_SSE
866 if (!cpu_fxsr)
867 #endif
868 fnclex();
869
870 td = PCPU_GET(fpcurthread);
871 PCPU_SET(fpcurthread, NULL);
872 td->td_pcb->pcb_flags &= ~PCB_NPXINITDONE;
873 start_emulating();
874 }
875
876 /*
877 * Get the state of the FPU without dropping ownership (if possible).
878 * It returns the FPU ownership status.
879 */
880 int
881 npxgetregs(td, addr)
882 struct thread *td;
883 union savefpu *addr;
884 {
885 register_t s;
886
887 if (!npx_exists)
888 return (_MC_FPOWNED_NONE);
889
890 if ((td->td_pcb->pcb_flags & PCB_NPXINITDONE) == 0) {
891 if (npx_cleanstate_ready)
892 bcopy(&npx_cleanstate, addr, sizeof(npx_cleanstate));
893 else
894 bzero(addr, sizeof(*addr));
895 return (_MC_FPOWNED_NONE);
896 }
897 s = intr_disable();
898 if (td == PCPU_GET(fpcurthread)) {
899 fpusave(addr);
900 #ifdef CPU_ENABLE_SSE
901 if (!cpu_fxsr)
902 #endif
903 /*
904 * fnsave initializes the FPU and destroys whatever
905 * context it contains. Make sure the FPU owner
906 * starts with a clean state next time.
907 */
908 npxdrop();
909 intr_restore(s);
910 return (_MC_FPOWNED_FPU);
911 } else {
912 intr_restore(s);
913 bcopy(&td->td_pcb->pcb_save, addr, sizeof(*addr));
914 return (_MC_FPOWNED_PCB);
915 }
916 }
917
918 /*
919 * Set the state of the FPU.
920 */
921 void
922 npxsetregs(td, addr)
923 struct thread *td;
924 union savefpu *addr;
925 {
926 register_t s;
927
928 if (!npx_exists)
929 return;
930
931 s = intr_disable();
932 if (td == PCPU_GET(fpcurthread)) {
933 #ifdef CPU_ENABLE_SSE
934 if (!cpu_fxsr)
935 #endif
936 fnclex(); /* As in npxdrop(). */
937 fpurstor(addr);
938 intr_restore(s);
939 } else {
940 intr_restore(s);
941 bcopy(addr, &td->td_pcb->pcb_save, sizeof(*addr));
942 }
943 curthread->td_pcb->pcb_flags |= PCB_NPXINITDONE;
944 }
945
946 static void
947 fpusave(addr)
948 union savefpu *addr;
949 {
950
951 #ifdef CPU_ENABLE_SSE
952 if (cpu_fxsr)
953 fxsave(addr);
954 else
955 #endif
956 fnsave(addr);
957 }
958
959 #ifdef CPU_ENABLE_SSE
960 /*
961 * On AuthenticAMD processors, the fxrstor instruction does not restore
962 * the x87's stored last instruction pointer, last data pointer, and last
963 * opcode values, except in the rare case in which the exception summary
964 * (ES) bit in the x87 status word is set to 1.
965 *
966 * In order to avoid leaking this information across processes, we clean
967 * these values by performing a dummy load before executing fxrstor().
968 */
969 static double dummy_variable = 0.0;
970 static void
971 fpu_clean_state(void)
972 {
973 u_short status;
974
975 /*
976 * Clear the ES bit in the x87 status word if it is currently
977 * set, in order to avoid causing a fault in the upcoming load.
978 */
979 fnstsw(&status);
980 if (status & 0x80)
981 fnclex();
982
983 /*
984 * Load the dummy variable into the x87 stack. This mangles
985 * the x87 stack, but we don't care since we're about to call
986 * fxrstor() anyway.
987 */
988 __asm __volatile("ffree %%st(7); fld %0" : : "m" (dummy_variable));
989 }
990 #endif /* CPU_ENABLE_SSE */
991
992 static void
993 fpurstor(addr)
994 union savefpu *addr;
995 {
996
997 #ifdef CPU_ENABLE_SSE
998 if (cpu_fxsr) {
999 fpu_clean_state();
1000 fxrstor(addr);
1001 } else
1002 #endif
1003 frstor(addr);
1004 }
1005
1006 #ifdef I586_CPU_XXX
1007 static long
1008 timezero(funcname, func)
1009 const char *funcname;
1010 void (*func)(void *buf, size_t len);
1011
1012 {
1013 void *buf;
1014 #define BUFSIZE 1048576
1015 long usec;
1016 struct timeval finish, start;
1017
1018 buf = malloc(BUFSIZE, M_TEMP, M_NOWAIT);
1019 if (buf == NULL)
1020 return (BUFSIZE);
1021 microtime(&start);
1022 (*func)(buf, BUFSIZE);
1023 microtime(&finish);
1024 usec = 1000000 * (finish.tv_sec - start.tv_sec) +
1025 finish.tv_usec - start.tv_usec;
1026 if (usec <= 0)
1027 usec = 1;
1028 if (bootverbose)
1029 printf("%s bandwidth = %u kBps\n", funcname,
1030 (u_int32_t)(((BUFSIZE >> 10) * 1000000) / usec));
1031 free(buf, M_TEMP);
1032 return (usec);
1033 }
1034 #endif /* I586_CPU */
1035
1036 static device_method_t npx_methods[] = {
1037 /* Device interface */
1038 DEVMETHOD(device_identify, npx_identify),
1039 DEVMETHOD(device_probe, npx_probe),
1040 DEVMETHOD(device_attach, npx_attach),
1041 DEVMETHOD(device_detach, bus_generic_detach),
1042 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1043 DEVMETHOD(device_suspend, bus_generic_suspend),
1044 DEVMETHOD(device_resume, bus_generic_resume),
1045
1046 { 0, 0 }
1047 };
1048
1049 static driver_t npx_driver = {
1050 "npx",
1051 npx_methods,
1052 1, /* no softc */
1053 };
1054
1055 static devclass_t npx_devclass;
1056
1057 /*
1058 * We prefer to attach to the root nexus so that the usual case (exception 16)
1059 * doesn't describe the processor as being `on isa'.
1060 */
1061 DRIVER_MODULE(npx, nexus, npx_driver, npx_devclass, 0, 0);
1062
1063 #ifdef DEV_ISA
1064 /*
1065 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI.
1066 */
1067 static struct isa_pnp_id npxisa_ids[] = {
1068 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */
1069 { 0 }
1070 };
1071
1072 static int
1073 npxisa_probe(device_t dev)
1074 {
1075 int result;
1076 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, npxisa_ids)) <= 0) {
1077 device_quiet(dev);
1078 }
1079 return(result);
1080 }
1081
1082 static int
1083 npxisa_attach(device_t dev)
1084 {
1085 return (0);
1086 }
1087
1088 static device_method_t npxisa_methods[] = {
1089 /* Device interface */
1090 DEVMETHOD(device_probe, npxisa_probe),
1091 DEVMETHOD(device_attach, npxisa_attach),
1092 DEVMETHOD(device_detach, bus_generic_detach),
1093 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1094 DEVMETHOD(device_suspend, bus_generic_suspend),
1095 DEVMETHOD(device_resume, bus_generic_resume),
1096
1097 { 0, 0 }
1098 };
1099
1100 static driver_t npxisa_driver = {
1101 "npxisa",
1102 npxisa_methods,
1103 1, /* no softc */
1104 };
1105
1106 static devclass_t npxisa_devclass;
1107
1108 DRIVER_MODULE(npxisa, isa, npxisa_driver, npxisa_devclass, 0, 0);
1109 #ifndef PC98
1110 DRIVER_MODULE(npxisa, acpi, npxisa_driver, npxisa_devclass, 0, 0);
1111 #endif
1112 #endif /* DEV_ISA */
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