The Design and Implementation of the FreeBSD Operating System, Second Edition
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sys/i386/isa/npx.c

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    1 /*-
    2  * Copyright (c) 1990 William Jolitz.
    3  * Copyright (c) 1991 The Regents of the University of California.
    4  * All rights reserved.
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions
    8  * are met:
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  * 4. Neither the name of the University nor the names of its contributors
   15  *    may be used to endorse or promote products derived from this software
   16  *    without specific prior written permission.
   17  *
   18  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   28  * SUCH DAMAGE.
   29  *
   30  *      from: @(#)npx.c 7.2 (Berkeley) 5/12/91
   31  */
   32 
   33 #include <sys/cdefs.h>
   34 __FBSDID("$FreeBSD$");
   35 
   36 #include "opt_cpu.h"
   37 #include "opt_isa.h"
   38 #include "opt_npx.h"
   39 
   40 #include <sys/param.h>
   41 #include <sys/systm.h>
   42 #include <sys/bus.h>
   43 #include <sys/kernel.h>
   44 #include <sys/lock.h>
   45 #include <sys/malloc.h>
   46 #include <sys/module.h>
   47 #include <sys/mutex.h>
   48 #include <sys/mutex.h>
   49 #include <sys/proc.h>
   50 #include <sys/smp.h>
   51 #include <sys/sysctl.h>
   52 #include <machine/bus.h>
   53 #include <sys/rman.h>
   54 #ifdef NPX_DEBUG
   55 #include <sys/syslog.h>
   56 #endif
   57 #include <sys/signalvar.h>
   58 
   59 #include <machine/asmacros.h>
   60 #include <machine/cputypes.h>
   61 #include <machine/frame.h>
   62 #include <machine/md_var.h>
   63 #include <machine/pcb.h>
   64 #include <machine/psl.h>
   65 #include <machine/resource.h>
   66 #include <machine/specialreg.h>
   67 #include <machine/segments.h>
   68 #include <machine/ucontext.h>
   69 
   70 #include <machine/intr_machdep.h>
   71 #ifdef DEV_ISA
   72 #include <isa/isavar.h>
   73 #endif
   74 
   75 #if !defined(CPU_DISABLE_SSE) && defined(I686_CPU)
   76 #define CPU_ENABLE_SSE
   77 #endif
   78 
   79 /*
   80  * 387 and 287 Numeric Coprocessor Extension (NPX) Driver.
   81  */
   82 
   83 /* Configuration flags. */
   84 #define NPX_DISABLE_I586_OPTIMIZED_BCOPY        (1 << 0)
   85 #define NPX_DISABLE_I586_OPTIMIZED_BZERO        (1 << 1)
   86 #define NPX_DISABLE_I586_OPTIMIZED_COPYIO       (1 << 2)
   87 
   88 #if defined(__GNUCLIKE_ASM) && !defined(lint)
   89 
   90 #define fldcw(addr)             __asm("fldcw %0" : : "m" (*(addr)))
   91 #define fnclex()                __asm("fnclex")
   92 #define fninit()                __asm("fninit")
   93 #define fnsave(addr)            __asm __volatile("fnsave %0" : "=m" (*(addr)))
   94 #define fnstcw(addr)            __asm __volatile("fnstcw %0" : "=m" (*(addr)))
   95 #define fnstsw(addr)            __asm __volatile("fnstsw %0" : "=m" (*(addr)))
   96 #define fp_divide_by_0()        __asm("fldz; fld1; fdiv %st,%st(1); fnop")
   97 #define frstor(addr)            __asm("frstor %0" : : "m" (*(addr)))
   98 #ifdef CPU_ENABLE_SSE
   99 #define fxrstor(addr)           __asm("fxrstor %0" : : "m" (*(addr)))
  100 #define fxsave(addr)            __asm __volatile("fxsave %0" : "=m" (*(addr)))
  101 #define ldmxcsr(__csr)          __asm __volatile("ldmxcsr %0" : : "m" (__csr))
  102 #endif
  103 #define start_emulating()       __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \
  104                                       : : "n" (CR0_TS) : "ax")
  105 #define stop_emulating()        __asm("clts")
  106 
  107 #else   /* !(__GNUCLIKE_ASM && !lint) */
  108 
  109 void    fldcw(caddr_t addr);
  110 void    fnclex(void);
  111 void    fninit(void);
  112 void    fnsave(caddr_t addr);
  113 void    fnstcw(caddr_t addr);
  114 void    fnstsw(caddr_t addr);
  115 void    fp_divide_by_0(void);
  116 void    frstor(caddr_t addr);
  117 #ifdef CPU_ENABLE_SSE
  118 void    fxsave(caddr_t addr);
  119 void    fxrstor(caddr_t addr);
  120 #endif
  121 void    start_emulating(void);
  122 void    stop_emulating(void);
  123 
  124 #endif  /* __GNUCLIKE_ASM && !lint */
  125 
  126 #ifdef CPU_ENABLE_SSE
  127 #define GET_FPU_CW(thread) \
  128         (cpu_fxsr ? \
  129                 (thread)->td_pcb->pcb_save.sv_xmm.sv_env.en_cw : \
  130                 (thread)->td_pcb->pcb_save.sv_87.sv_env.en_cw)
  131 #define GET_FPU_SW(thread) \
  132         (cpu_fxsr ? \
  133                 (thread)->td_pcb->pcb_save.sv_xmm.sv_env.en_sw : \
  134                 (thread)->td_pcb->pcb_save.sv_87.sv_env.en_sw)
  135 #else /* CPU_ENABLE_SSE */
  136 #define GET_FPU_CW(thread) \
  137         (thread->td_pcb->pcb_save.sv_87.sv_env.en_cw)
  138 #define GET_FPU_SW(thread) \
  139         (thread->td_pcb->pcb_save.sv_87.sv_env.en_sw)
  140 #endif /* CPU_ENABLE_SSE */
  141 
  142 typedef u_char bool_t;
  143 
  144 #ifdef CPU_ENABLE_SSE
  145 static  void    fpu_clean_state(void);
  146 #endif
  147 
  148 static  void    fpusave(union savefpu *);
  149 static  void    fpurstor(union savefpu *);
  150 static  int     npx_attach(device_t dev);
  151 static  void    npx_identify(driver_t *driver, device_t parent);
  152 static  int     npx_intr(void *);
  153 static  int     npx_probe(device_t dev);
  154 #ifdef I586_CPU_XXX
  155 static  long    timezero(const char *funcname,
  156                     void (*func)(void *buf, size_t len));
  157 #endif /* I586_CPU */
  158 
  159 int     hw_float;               /* XXX currently just alias for npx_exists */
  160 
  161 SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint,
  162         CTLFLAG_RD, &hw_float, 0, 
  163         "Floatingpoint instructions executed in hardware");
  164 
  165 static  volatile u_int          npx_intrs_while_probing;
  166 static  volatile u_int          npx_traps_while_probing;
  167 
  168 static  union savefpu           npx_cleanstate;
  169 static  bool_t                  npx_cleanstate_ready;
  170 static  bool_t                  npx_ex16;
  171 static  bool_t                  npx_exists;
  172 static  bool_t                  npx_irq13;
  173 
  174 alias_for_inthand_t probetrap;
  175 __asm("                                                         \n\
  176         .text                                                   \n\
  177         .p2align 2,0x90                                         \n\
  178         .type   " __XSTRING(CNAME(probetrap)) ",@function       \n\
  179 " __XSTRING(CNAME(probetrap)) ":                                \n\
  180         ss                                                      \n\
  181         incl    " __XSTRING(CNAME(npx_traps_while_probing)) "   \n\
  182         fnclex                                                  \n\
  183         iret                                                    \n\
  184 ");
  185 
  186 /*
  187  * Identify routine.  Create a connection point on our parent for probing.
  188  */
  189 static void
  190 npx_identify(driver, parent)
  191         driver_t *driver;
  192         device_t parent;
  193 {
  194         device_t child;
  195 
  196         child = BUS_ADD_CHILD(parent, 0, "npx", 0);
  197         if (child == NULL)
  198                 panic("npx_identify");
  199 }
  200 
  201 /*
  202  * Do minimal handling of npx interrupts to convert them to traps.
  203  */
  204 static int
  205 npx_intr(dummy)
  206         void *dummy;
  207 {
  208         struct thread *td;
  209 
  210         npx_intrs_while_probing++;
  211 
  212         /*
  213          * The BUSY# latch must be cleared in all cases so that the next
  214          * unmasked npx exception causes an interrupt.
  215          */
  216         outb(IO_NPX, 0);
  217 
  218         /*
  219          * fpcurthread is normally non-null here.  In that case, schedule an
  220          * AST to finish the exception handling in the correct context
  221          * (this interrupt may occur after the thread has entered the
  222          * kernel via a syscall or an interrupt).  Otherwise, the npx
  223          * state of the thread that caused this interrupt must have been
  224          * pushed to the thread's pcb, and clearing of the busy latch
  225          * above has finished the (essentially null) handling of this
  226          * interrupt.  Control will eventually return to the instruction
  227          * that caused it and it will repeat.  We will eventually (usually
  228          * soon) win the race to handle the interrupt properly.
  229          */
  230         td = PCPU_GET(fpcurthread);
  231         if (td != NULL) {
  232                 td->td_pcb->pcb_flags |= PCB_NPXTRAP;
  233                 thread_lock(td);
  234                 td->td_flags |= TDF_ASTPENDING;
  235                 thread_unlock(td);
  236         }
  237         return (FILTER_HANDLED);
  238 }
  239 
  240 /*
  241  * Probe routine.  Set flags to tell npxattach() what to do.  Set up an
  242  * interrupt handler if npx needs to use interrupts.
  243  */
  244 static int
  245 npx_probe(dev)
  246         device_t dev;
  247 {
  248         struct gate_descriptor save_idt_npxtrap;
  249         struct resource *ioport_res, *irq_res;
  250         void *irq_cookie;
  251         int ioport_rid, irq_num, irq_rid;
  252         u_short control;
  253         u_short status;
  254 
  255         device_set_desc(dev, "math processor");
  256 
  257         /*
  258          * Modern CPUs all have an FPU that uses the INT16 interface
  259          * and provide a simple way to verify that, so handle the
  260          * common case right away.
  261          */
  262         if (cpu_feature & CPUID_FPU) {
  263                 hw_float = npx_exists = 1;
  264                 npx_ex16 = 1;
  265                 device_quiet(dev);
  266                 return (0);
  267         }
  268 
  269         save_idt_npxtrap = idt[IDT_MF];
  270         setidt(IDT_MF, probetrap, SDT_SYS386TGT, SEL_KPL,
  271             GSEL(GCODE_SEL, SEL_KPL));
  272         ioport_rid = 0;
  273         ioport_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &ioport_rid,
  274             IO_NPX, IO_NPX + IO_NPXSIZE - 1, IO_NPXSIZE, RF_ACTIVE);
  275         if (ioport_res == NULL)
  276                 panic("npx: can't get ports");
  277         if (resource_int_value("npx", 0, "irq", &irq_num) != 0)
  278                 irq_num = IRQ_NPX;
  279         irq_rid = 0;
  280         irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &irq_rid, irq_num,
  281             irq_num, 1, RF_ACTIVE);
  282         if (irq_res != NULL) {
  283                 if (bus_setup_intr(dev, irq_res, INTR_TYPE_MISC,
  284                         npx_intr, NULL, NULL, &irq_cookie) != 0)
  285                         panic("npx: can't create intr");
  286         }
  287 
  288         /*
  289          * Partially reset the coprocessor, if any.  Some BIOS's don't reset
  290          * it after a warm boot.
  291          */
  292         npx_full_reset();
  293         outb(IO_NPX, 0);
  294 
  295         /*
  296          * Don't trap while we're probing.
  297          */
  298         stop_emulating();
  299 
  300         /*
  301          * Finish resetting the coprocessor, if any.  If there is an error
  302          * pending, then we may get a bogus IRQ13, but npx_intr() will handle
  303          * it OK.  Bogus halts have never been observed, but we enabled
  304          * IRQ13 and cleared the BUSY# latch early to handle them anyway.
  305          */
  306         fninit();
  307 
  308         /*
  309          * Don't use fwait here because it might hang.
  310          * Don't use fnop here because it usually hangs if there is no FPU.
  311          */
  312         DELAY(1000);            /* wait for any IRQ13 */
  313 #ifdef DIAGNOSTIC
  314         if (npx_intrs_while_probing != 0)
  315                 printf("fninit caused %u bogus npx interrupt(s)\n",
  316                        npx_intrs_while_probing);
  317         if (npx_traps_while_probing != 0)
  318                 printf("fninit caused %u bogus npx trap(s)\n",
  319                        npx_traps_while_probing);
  320 #endif
  321         /*
  322          * Check for a status of mostly zero.
  323          */
  324         status = 0x5a5a;
  325         fnstsw(&status);
  326         if ((status & 0xb8ff) == 0) {
  327                 /*
  328                  * Good, now check for a proper control word.
  329                  */
  330                 control = 0x5a5a;
  331                 fnstcw(&control);
  332                 if ((control & 0x1f3f) == 0x033f) {
  333                         hw_float = npx_exists = 1;
  334                         /*
  335                          * We have an npx, now divide by 0 to see if exception
  336                          * 16 works.
  337                          */
  338                         control &= ~(1 << 2);   /* enable divide by 0 trap */
  339                         fldcw(&control);
  340 #ifdef FPU_ERROR_BROKEN
  341                         /*
  342                          * FPU error signal doesn't work on some CPU
  343                          * accelerator board.
  344                          */
  345                         npx_ex16 = 1;
  346                         return (0);
  347 #endif
  348                         npx_traps_while_probing = npx_intrs_while_probing = 0;
  349                         fp_divide_by_0();
  350                         DELAY(1000);    /* wait for any IRQ13 */
  351                         if (npx_traps_while_probing != 0) {
  352                                 /*
  353                                  * Good, exception 16 works.
  354                                  */
  355                                 npx_ex16 = 1;
  356                                 goto no_irq13;
  357                         }
  358                         if (npx_intrs_while_probing != 0) {
  359                                 /*
  360                                  * Bad, we are stuck with IRQ13.
  361                                  */
  362                                 npx_irq13 = 1;
  363                                 idt[IDT_MF] = save_idt_npxtrap;
  364 #ifdef SMP
  365                                 if (mp_ncpus > 1)
  366                                         panic("npx0 cannot use IRQ 13 on an SMP system");
  367 #endif
  368                                 return (0);
  369                         }
  370                         /*
  371                          * Worse, even IRQ13 is broken.  Use emulator.
  372                          */
  373                 }
  374         }
  375         /*
  376          * Probe failed, but we want to get to npxattach to initialize the
  377          * emulator and say that it has been installed.  XXX handle devices
  378          * that aren't really devices better.
  379          */
  380 #ifdef SMP
  381         if (mp_ncpus > 1)
  382                 panic("npx0 cannot be emulated on an SMP system");
  383 #endif
  384         /* FALLTHROUGH */
  385 no_irq13:
  386         idt[IDT_MF] = save_idt_npxtrap;
  387         if (irq_res != NULL) {
  388                 bus_teardown_intr(dev, irq_res, irq_cookie);
  389                 bus_release_resource(dev, SYS_RES_IRQ, irq_rid, irq_res);
  390         }
  391         bus_release_resource(dev, SYS_RES_IOPORT, ioport_rid, ioport_res);
  392         return (0);
  393 }
  394 
  395 /*
  396  * Attach routine - announce which it is, and wire into system
  397  */
  398 static int
  399 npx_attach(dev)
  400         device_t dev;
  401 {
  402         int flags;
  403         register_t s;
  404 
  405         flags = device_get_flags(dev);
  406 
  407         if (npx_irq13)
  408                 device_printf(dev, "IRQ 13 interface\n");
  409         else if (!npx_ex16)
  410                 device_printf(dev, "WARNING: no FPU!\n");
  411         else if (!device_is_quiet(dev) || bootverbose)
  412                 device_printf(dev, "INT 16 interface\n");
  413 
  414         npxinit(__INITIAL_NPXCW__);
  415 
  416         if (npx_cleanstate_ready == 0) {
  417                 s = intr_disable();
  418                 stop_emulating();
  419                 fpusave(&npx_cleanstate);
  420                 start_emulating();
  421 #ifdef CPU_ENABLE_SSE
  422                 if (cpu_fxsr) {
  423                         if (npx_cleanstate.sv_xmm.sv_env.en_mxcsr_mask)
  424                                 cpu_mxcsr_mask = 
  425                                     npx_cleanstate.sv_xmm.sv_env.en_mxcsr_mask;
  426                         else
  427                                 cpu_mxcsr_mask = 0xFFBF;
  428                 }
  429 #endif
  430                 npx_cleanstate_ready = 1;
  431                 intr_restore(s);
  432         }
  433 #ifdef I586_CPU_XXX
  434         if (cpu_class == CPUCLASS_586 && npx_ex16 && npx_exists &&
  435             timezero("i586_bzero()", i586_bzero) <
  436             timezero("bzero()", bzero) * 4 / 5) {
  437                 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY))
  438                         bcopy_vector = i586_bcopy;
  439                 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BZERO))
  440                         bzero_vector = i586_bzero;
  441                 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_COPYIO)) {
  442                         copyin_vector = i586_copyin;
  443                         copyout_vector = i586_copyout;
  444                 }
  445         }
  446 #endif
  447 
  448         return (0);             /* XXX unused */
  449 }
  450 
  451 /*
  452  * Initialize floating point unit.
  453  */
  454 void
  455 npxinit(control)
  456         u_short control;
  457 {
  458         static union savefpu dummy;
  459         register_t savecrit;
  460 
  461         if (!npx_exists)
  462                 return;
  463         /*
  464          * fninit has the same h/w bugs as fnsave.  Use the detoxified
  465          * fnsave to throw away any junk in the fpu.  npxsave() initializes
  466          * the fpu and sets fpcurthread = NULL as important side effects.
  467          */
  468         savecrit = intr_disable();
  469         npxsave(&dummy);
  470         stop_emulating();
  471 #ifdef CPU_ENABLE_SSE
  472         /* XXX npxsave() doesn't actually initialize the fpu in the SSE case. */
  473         if (cpu_fxsr)
  474                 fninit();
  475 #endif
  476         fldcw(&control);
  477         start_emulating();
  478         intr_restore(savecrit);
  479 }
  480 
  481 /*
  482  * Free coprocessor (if we have it).
  483  */
  484 void
  485 npxexit(td)
  486         struct thread *td;
  487 {
  488         register_t savecrit;
  489 
  490         savecrit = intr_disable();
  491         if (curthread == PCPU_GET(fpcurthread))
  492                 npxsave(&PCPU_GET(curpcb)->pcb_save);
  493         intr_restore(savecrit);
  494 #ifdef NPX_DEBUG
  495         if (npx_exists) {
  496                 u_int   masked_exceptions;
  497 
  498                 masked_exceptions = GET_FPU_CW(td) & GET_FPU_SW(td) & 0x7f;
  499                 /*
  500                  * Log exceptions that would have trapped with the old
  501                  * control word (overflow, divide by 0, and invalid operand).
  502                  */
  503                 if (masked_exceptions & 0x0d)
  504                         log(LOG_ERR,
  505         "pid %d (%s) exited with masked floating point exceptions 0x%02x\n",
  506                             td->td_proc->p_pid, td->td_proc->p_comm,
  507                             masked_exceptions);
  508         }
  509 #endif
  510 }
  511 
  512 int
  513 npxformat()
  514 {
  515 
  516         if (!npx_exists)
  517                 return (_MC_FPFMT_NODEV);
  518 #ifdef  CPU_ENABLE_SSE
  519         if (cpu_fxsr)
  520                 return (_MC_FPFMT_XMM);
  521 #endif
  522         return (_MC_FPFMT_387);
  523 }
  524 
  525 /* 
  526  * The following mechanism is used to ensure that the FPE_... value
  527  * that is passed as a trapcode to the signal handler of the user
  528  * process does not have more than one bit set.
  529  * 
  530  * Multiple bits may be set if the user process modifies the control
  531  * word while a status word bit is already set.  While this is a sign
  532  * of bad coding, we have no choise than to narrow them down to one
  533  * bit, since we must not send a trapcode that is not exactly one of
  534  * the FPE_ macros.
  535  *
  536  * The mechanism has a static table with 127 entries.  Each combination
  537  * of the 7 FPU status word exception bits directly translates to a
  538  * position in this table, where a single FPE_... value is stored.
  539  * This FPE_... value stored there is considered the "most important"
  540  * of the exception bits and will be sent as the signal code.  The
  541  * precedence of the bits is based upon Intel Document "Numerical
  542  * Applications", Chapter "Special Computational Situations".
  543  *
  544  * The macro to choose one of these values does these steps: 1) Throw
  545  * away status word bits that cannot be masked.  2) Throw away the bits
  546  * currently masked in the control word, assuming the user isn't
  547  * interested in them anymore.  3) Reinsert status word bit 7 (stack
  548  * fault) if it is set, which cannot be masked but must be presered.
  549  * 4) Use the remaining bits to point into the trapcode table.
  550  *
  551  * The 6 maskable bits in order of their preference, as stated in the
  552  * above referenced Intel manual:
  553  * 1  Invalid operation (FP_X_INV)
  554  * 1a   Stack underflow
  555  * 1b   Stack overflow
  556  * 1c   Operand of unsupported format
  557  * 1d   SNaN operand.
  558  * 2  QNaN operand (not an exception, irrelavant here)
  559  * 3  Any other invalid-operation not mentioned above or zero divide
  560  *      (FP_X_INV, FP_X_DZ)
  561  * 4  Denormal operand (FP_X_DNML)
  562  * 5  Numeric over/underflow (FP_X_OFL, FP_X_UFL)
  563  * 6  Inexact result (FP_X_IMP) 
  564  */
  565 static char fpetable[128] = {
  566         0,
  567         FPE_FLTINV,     /*  1 - INV */
  568         FPE_FLTUND,     /*  2 - DNML */
  569         FPE_FLTINV,     /*  3 - INV | DNML */
  570         FPE_FLTDIV,     /*  4 - DZ */
  571         FPE_FLTINV,     /*  5 - INV | DZ */
  572         FPE_FLTDIV,     /*  6 - DNML | DZ */
  573         FPE_FLTINV,     /*  7 - INV | DNML | DZ */
  574         FPE_FLTOVF,     /*  8 - OFL */
  575         FPE_FLTINV,     /*  9 - INV | OFL */
  576         FPE_FLTUND,     /*  A - DNML | OFL */
  577         FPE_FLTINV,     /*  B - INV | DNML | OFL */
  578         FPE_FLTDIV,     /*  C - DZ | OFL */
  579         FPE_FLTINV,     /*  D - INV | DZ | OFL */
  580         FPE_FLTDIV,     /*  E - DNML | DZ | OFL */
  581         FPE_FLTINV,     /*  F - INV | DNML | DZ | OFL */
  582         FPE_FLTUND,     /* 10 - UFL */
  583         FPE_FLTINV,     /* 11 - INV | UFL */
  584         FPE_FLTUND,     /* 12 - DNML | UFL */
  585         FPE_FLTINV,     /* 13 - INV | DNML | UFL */
  586         FPE_FLTDIV,     /* 14 - DZ | UFL */
  587         FPE_FLTINV,     /* 15 - INV | DZ | UFL */
  588         FPE_FLTDIV,     /* 16 - DNML | DZ | UFL */
  589         FPE_FLTINV,     /* 17 - INV | DNML | DZ | UFL */
  590         FPE_FLTOVF,     /* 18 - OFL | UFL */
  591         FPE_FLTINV,     /* 19 - INV | OFL | UFL */
  592         FPE_FLTUND,     /* 1A - DNML | OFL | UFL */
  593         FPE_FLTINV,     /* 1B - INV | DNML | OFL | UFL */
  594         FPE_FLTDIV,     /* 1C - DZ | OFL | UFL */
  595         FPE_FLTINV,     /* 1D - INV | DZ | OFL | UFL */
  596         FPE_FLTDIV,     /* 1E - DNML | DZ | OFL | UFL */
  597         FPE_FLTINV,     /* 1F - INV | DNML | DZ | OFL | UFL */
  598         FPE_FLTRES,     /* 20 - IMP */
  599         FPE_FLTINV,     /* 21 - INV | IMP */
  600         FPE_FLTUND,     /* 22 - DNML | IMP */
  601         FPE_FLTINV,     /* 23 - INV | DNML | IMP */
  602         FPE_FLTDIV,     /* 24 - DZ | IMP */
  603         FPE_FLTINV,     /* 25 - INV | DZ | IMP */
  604         FPE_FLTDIV,     /* 26 - DNML | DZ | IMP */
  605         FPE_FLTINV,     /* 27 - INV | DNML | DZ | IMP */
  606         FPE_FLTOVF,     /* 28 - OFL | IMP */
  607         FPE_FLTINV,     /* 29 - INV | OFL | IMP */
  608         FPE_FLTUND,     /* 2A - DNML | OFL | IMP */
  609         FPE_FLTINV,     /* 2B - INV | DNML | OFL | IMP */
  610         FPE_FLTDIV,     /* 2C - DZ | OFL | IMP */
  611         FPE_FLTINV,     /* 2D - INV | DZ | OFL | IMP */
  612         FPE_FLTDIV,     /* 2E - DNML | DZ | OFL | IMP */
  613         FPE_FLTINV,     /* 2F - INV | DNML | DZ | OFL | IMP */
  614         FPE_FLTUND,     /* 30 - UFL | IMP */
  615         FPE_FLTINV,     /* 31 - INV | UFL | IMP */
  616         FPE_FLTUND,     /* 32 - DNML | UFL | IMP */
  617         FPE_FLTINV,     /* 33 - INV | DNML | UFL | IMP */
  618         FPE_FLTDIV,     /* 34 - DZ | UFL | IMP */
  619         FPE_FLTINV,     /* 35 - INV | DZ | UFL | IMP */
  620         FPE_FLTDIV,     /* 36 - DNML | DZ | UFL | IMP */
  621         FPE_FLTINV,     /* 37 - INV | DNML | DZ | UFL | IMP */
  622         FPE_FLTOVF,     /* 38 - OFL | UFL | IMP */
  623         FPE_FLTINV,     /* 39 - INV | OFL | UFL | IMP */
  624         FPE_FLTUND,     /* 3A - DNML | OFL | UFL | IMP */
  625         FPE_FLTINV,     /* 3B - INV | DNML | OFL | UFL | IMP */
  626         FPE_FLTDIV,     /* 3C - DZ | OFL | UFL | IMP */
  627         FPE_FLTINV,     /* 3D - INV | DZ | OFL | UFL | IMP */
  628         FPE_FLTDIV,     /* 3E - DNML | DZ | OFL | UFL | IMP */
  629         FPE_FLTINV,     /* 3F - INV | DNML | DZ | OFL | UFL | IMP */
  630         FPE_FLTSUB,     /* 40 - STK */
  631         FPE_FLTSUB,     /* 41 - INV | STK */
  632         FPE_FLTUND,     /* 42 - DNML | STK */
  633         FPE_FLTSUB,     /* 43 - INV | DNML | STK */
  634         FPE_FLTDIV,     /* 44 - DZ | STK */
  635         FPE_FLTSUB,     /* 45 - INV | DZ | STK */
  636         FPE_FLTDIV,     /* 46 - DNML | DZ | STK */
  637         FPE_FLTSUB,     /* 47 - INV | DNML | DZ | STK */
  638         FPE_FLTOVF,     /* 48 - OFL | STK */
  639         FPE_FLTSUB,     /* 49 - INV | OFL | STK */
  640         FPE_FLTUND,     /* 4A - DNML | OFL | STK */
  641         FPE_FLTSUB,     /* 4B - INV | DNML | OFL | STK */
  642         FPE_FLTDIV,     /* 4C - DZ | OFL | STK */
  643         FPE_FLTSUB,     /* 4D - INV | DZ | OFL | STK */
  644         FPE_FLTDIV,     /* 4E - DNML | DZ | OFL | STK */
  645         FPE_FLTSUB,     /* 4F - INV | DNML | DZ | OFL | STK */
  646         FPE_FLTUND,     /* 50 - UFL | STK */
  647         FPE_FLTSUB,     /* 51 - INV | UFL | STK */
  648         FPE_FLTUND,     /* 52 - DNML | UFL | STK */
  649         FPE_FLTSUB,     /* 53 - INV | DNML | UFL | STK */
  650         FPE_FLTDIV,     /* 54 - DZ | UFL | STK */
  651         FPE_FLTSUB,     /* 55 - INV | DZ | UFL | STK */
  652         FPE_FLTDIV,     /* 56 - DNML | DZ | UFL | STK */
  653         FPE_FLTSUB,     /* 57 - INV | DNML | DZ | UFL | STK */
  654         FPE_FLTOVF,     /* 58 - OFL | UFL | STK */
  655         FPE_FLTSUB,     /* 59 - INV | OFL | UFL | STK */
  656         FPE_FLTUND,     /* 5A - DNML | OFL | UFL | STK */
  657         FPE_FLTSUB,     /* 5B - INV | DNML | OFL | UFL | STK */
  658         FPE_FLTDIV,     /* 5C - DZ | OFL | UFL | STK */
  659         FPE_FLTSUB,     /* 5D - INV | DZ | OFL | UFL | STK */
  660         FPE_FLTDIV,     /* 5E - DNML | DZ | OFL | UFL | STK */
  661         FPE_FLTSUB,     /* 5F - INV | DNML | DZ | OFL | UFL | STK */
  662         FPE_FLTRES,     /* 60 - IMP | STK */
  663         FPE_FLTSUB,     /* 61 - INV | IMP | STK */
  664         FPE_FLTUND,     /* 62 - DNML | IMP | STK */
  665         FPE_FLTSUB,     /* 63 - INV | DNML | IMP | STK */
  666         FPE_FLTDIV,     /* 64 - DZ | IMP | STK */
  667         FPE_FLTSUB,     /* 65 - INV | DZ | IMP | STK */
  668         FPE_FLTDIV,     /* 66 - DNML | DZ | IMP | STK */
  669         FPE_FLTSUB,     /* 67 - INV | DNML | DZ | IMP | STK */
  670         FPE_FLTOVF,     /* 68 - OFL | IMP | STK */
  671         FPE_FLTSUB,     /* 69 - INV | OFL | IMP | STK */
  672         FPE_FLTUND,     /* 6A - DNML | OFL | IMP | STK */
  673         FPE_FLTSUB,     /* 6B - INV | DNML | OFL | IMP | STK */
  674         FPE_FLTDIV,     /* 6C - DZ | OFL | IMP | STK */
  675         FPE_FLTSUB,     /* 6D - INV | DZ | OFL | IMP | STK */
  676         FPE_FLTDIV,     /* 6E - DNML | DZ | OFL | IMP | STK */
  677         FPE_FLTSUB,     /* 6F - INV | DNML | DZ | OFL | IMP | STK */
  678         FPE_FLTUND,     /* 70 - UFL | IMP | STK */
  679         FPE_FLTSUB,     /* 71 - INV | UFL | IMP | STK */
  680         FPE_FLTUND,     /* 72 - DNML | UFL | IMP | STK */
  681         FPE_FLTSUB,     /* 73 - INV | DNML | UFL | IMP | STK */
  682         FPE_FLTDIV,     /* 74 - DZ | UFL | IMP | STK */
  683         FPE_FLTSUB,     /* 75 - INV | DZ | UFL | IMP | STK */
  684         FPE_FLTDIV,     /* 76 - DNML | DZ | UFL | IMP | STK */
  685         FPE_FLTSUB,     /* 77 - INV | DNML | DZ | UFL | IMP | STK */
  686         FPE_FLTOVF,     /* 78 - OFL | UFL | IMP | STK */
  687         FPE_FLTSUB,     /* 79 - INV | OFL | UFL | IMP | STK */
  688         FPE_FLTUND,     /* 7A - DNML | OFL | UFL | IMP | STK */
  689         FPE_FLTSUB,     /* 7B - INV | DNML | OFL | UFL | IMP | STK */
  690         FPE_FLTDIV,     /* 7C - DZ | OFL | UFL | IMP | STK */
  691         FPE_FLTSUB,     /* 7D - INV | DZ | OFL | UFL | IMP | STK */
  692         FPE_FLTDIV,     /* 7E - DNML | DZ | OFL | UFL | IMP | STK */
  693         FPE_FLTSUB,     /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */
  694 };
  695 
  696 /*
  697  * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE.
  698  *
  699  * Clearing exceptions is necessary mainly to avoid IRQ13 bugs.  We now
  700  * depend on longjmp() restoring a usable state.  Restoring the state
  701  * or examining it might fail if we didn't clear exceptions.
  702  *
  703  * The error code chosen will be one of the FPE_... macros. It will be
  704  * sent as the second argument to old BSD-style signal handlers and as
  705  * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers.
  706  *
  707  * XXX the FP state is not preserved across signal handlers.  So signal
  708  * handlers cannot afford to do FP unless they preserve the state or
  709  * longjmp() out.  Both preserving the state and longjmp()ing may be
  710  * destroyed by IRQ13 bugs.  Clearing FP exceptions is not an acceptable
  711  * solution for signals other than SIGFPE.
  712  */
  713 int
  714 npxtrap()
  715 {
  716         register_t savecrit;
  717         u_short control, status;
  718 
  719         if (!npx_exists) {
  720                 printf("npxtrap: fpcurthread = %p, curthread = %p, npx_exists = %d\n",
  721                        PCPU_GET(fpcurthread), curthread, npx_exists);
  722                 panic("npxtrap from nowhere");
  723         }
  724         savecrit = intr_disable();
  725 
  726         /*
  727          * Interrupt handling (for another interrupt) may have pushed the
  728          * state to memory.  Fetch the relevant parts of the state from
  729          * wherever they are.
  730          */
  731         if (PCPU_GET(fpcurthread) != curthread) {
  732                 control = GET_FPU_CW(curthread);
  733                 status = GET_FPU_SW(curthread);
  734         } else {
  735                 fnstcw(&control);
  736                 fnstsw(&status);
  737         }
  738 
  739         if (PCPU_GET(fpcurthread) == curthread)
  740                 fnclex();
  741         intr_restore(savecrit);
  742         return (fpetable[status & ((~control & 0x3f) | 0x40)]);
  743 }
  744 
  745 /*
  746  * Implement device not available (DNA) exception
  747  *
  748  * It would be better to switch FP context here (if curthread != fpcurthread)
  749  * and not necessarily for every context switch, but it is too hard to
  750  * access foreign pcb's.
  751  */
  752 
  753 static int err_count = 0;
  754 
  755 int
  756 npxdna()
  757 {
  758         struct pcb *pcb;
  759         register_t s;
  760 #ifdef CPU_ENABLE_SSE
  761         int mxcsr;
  762 #endif
  763         u_short control;
  764 
  765         if (!npx_exists)
  766                 return (0);
  767         if (PCPU_GET(fpcurthread) == curthread) {
  768                 printf("npxdna: fpcurthread == curthread %d times\n",
  769                     ++err_count);
  770                 stop_emulating();
  771                 return (1);
  772         }
  773         if (PCPU_GET(fpcurthread) != NULL) {
  774                 printf("npxdna: fpcurthread = %p (%d), curthread = %p (%d)\n",
  775                        PCPU_GET(fpcurthread),
  776                        PCPU_GET(fpcurthread)->td_proc->p_pid,
  777                        curthread, curthread->td_proc->p_pid);
  778                 panic("npxdna");
  779         }
  780         s = intr_disable();
  781         stop_emulating();
  782         /*
  783          * Record new context early in case frstor causes an IRQ13.
  784          */
  785         PCPU_SET(fpcurthread, curthread);
  786         pcb = PCPU_GET(curpcb);
  787 
  788         if ((pcb->pcb_flags & PCB_NPXINITDONE) == 0) {
  789                 /*
  790                  * This is the first time this thread has used the FPU or
  791                  * the PCB doesn't contain a clean FPU state.  Explicitly
  792                  * initialize the FPU and load the default control word.
  793                  */
  794                 fninit();
  795                 control = __INITIAL_NPXCW__;
  796                 fldcw(&control);
  797 #ifdef CPU_ENABLE_SSE
  798                 if (cpu_fxsr) {
  799                         mxcsr = __INITIAL_MXCSR__;
  800                         ldmxcsr(mxcsr);
  801                 }
  802 #endif
  803                 pcb->pcb_flags |= PCB_NPXINITDONE;
  804         } else {
  805                 /*
  806                  * The following frstor may cause an IRQ13 when the state
  807                  * being restored has a pending error.  The error will
  808                  * appear to have been triggered by the current (npx) user
  809                  * instruction even when that instruction is a no-wait
  810                  * instruction that should not trigger an error (e.g.,
  811                  * fnclex).  On at least one 486 system all of the no-wait
  812                  * instructions are broken the same as frstor, so our
  813                  * treatment does not amplify the breakage.  On at least
  814                  * one 386/Cyrix 387 system, fnclex works correctly while
  815                  * frstor and fnsave are broken, so our treatment breaks
  816                  * fnclex if it is the first FPU instruction after a context
  817                  * switch.
  818                  */
  819                 fpurstor(&pcb->pcb_save);
  820         }
  821         intr_restore(s);
  822 
  823         return (1);
  824 }
  825 
  826 /*
  827  * Wrapper for fnsave instruction, partly to handle hardware bugs.  When npx
  828  * exceptions are reported via IRQ13, spurious IRQ13's may be triggered by
  829  * no-wait npx instructions.  See the Intel application note AP-578 for
  830  * details.  This doesn't cause any additional complications here.  IRQ13's
  831  * are inherently asynchronous unless the CPU is frozen to deliver them --
  832  * one that started in userland may be delivered many instructions later,
  833  * after the process has entered the kernel.  It may even be delivered after
  834  * the fnsave here completes.  A spurious IRQ13 for the fnsave is handled in
  835  * the same way as a very-late-arriving non-spurious IRQ13 from user mode:
  836  * it is normally ignored at first because we set fpcurthread to NULL; it is
  837  * normally retriggered in npxdna() after return to user mode.
  838  *
  839  * npxsave() must be called with interrupts disabled, so that it clears
  840  * fpcurthread atomically with saving the state.  We require callers to do the
  841  * disabling, since most callers need to disable interrupts anyway to call
  842  * npxsave() atomically with checking fpcurthread.
  843  *
  844  * A previous version of npxsave() went to great lengths to excecute fnsave
  845  * with interrupts enabled in case executing it froze the CPU.  This case
  846  * can't happen, at least for Intel CPU/NPX's.  Spurious IRQ13's don't imply
  847  * spurious freezes.
  848  */
  849 void
  850 npxsave(addr)
  851         union savefpu *addr;
  852 {
  853 
  854         stop_emulating();
  855         fpusave(addr);
  856 
  857         start_emulating();
  858         PCPU_SET(fpcurthread, NULL);
  859 }
  860 
  861 /*
  862  * This should be called with interrupts disabled and only when the owning
  863  * FPU thread is non-null.
  864  */
  865 void
  866 npxdrop()
  867 {
  868         struct thread *td;
  869 
  870         /*
  871          * Discard pending exceptions in the !cpu_fxsr case so that unmasked
  872          * ones don't cause a panic on the next frstor.
  873          */
  874 #ifdef CPU_ENABLE_SSE
  875         if (!cpu_fxsr)
  876 #endif
  877                 fnclex();
  878 
  879         td = PCPU_GET(fpcurthread);
  880         PCPU_SET(fpcurthread, NULL);
  881         td->td_pcb->pcb_flags &= ~PCB_NPXINITDONE;
  882         start_emulating();
  883 }
  884 
  885 /*
  886  * Get the state of the FPU without dropping ownership (if possible).
  887  * It returns the FPU ownership status.
  888  */
  889 int
  890 npxgetregs(td, addr)
  891         struct thread *td;
  892         union savefpu *addr;
  893 {
  894         register_t s;
  895 
  896         if (!npx_exists)
  897                 return (_MC_FPOWNED_NONE);
  898 
  899         if ((td->td_pcb->pcb_flags & PCB_NPXINITDONE) == 0) {
  900                 if (npx_cleanstate_ready)
  901                         bcopy(&npx_cleanstate, addr, sizeof(npx_cleanstate));
  902                 else
  903                         bzero(addr, sizeof(*addr));
  904                 return (_MC_FPOWNED_NONE);
  905         }
  906         s = intr_disable();
  907         if (td == PCPU_GET(fpcurthread)) {
  908                 fpusave(addr);
  909 #ifdef CPU_ENABLE_SSE
  910                 if (!cpu_fxsr)
  911 #endif
  912                         /*
  913                          * fnsave initializes the FPU and destroys whatever
  914                          * context it contains.  Make sure the FPU owner
  915                          * starts with a clean state next time.
  916                          */
  917                         npxdrop();
  918                 intr_restore(s);
  919                 return (_MC_FPOWNED_FPU);
  920         } else {
  921                 intr_restore(s);
  922                 bcopy(&td->td_pcb->pcb_save, addr, sizeof(*addr));
  923                 return (_MC_FPOWNED_PCB);
  924         }
  925 }
  926 
  927 /*
  928  * Set the state of the FPU.
  929  */
  930 void
  931 npxsetregs(td, addr)
  932         struct thread *td;
  933         union savefpu *addr;
  934 {
  935         register_t s;
  936 
  937         if (!npx_exists)
  938                 return;
  939 
  940         s = intr_disable();
  941         if (td == PCPU_GET(fpcurthread)) {
  942 #ifdef CPU_ENABLE_SSE
  943                 if (!cpu_fxsr)
  944 #endif
  945                         fnclex();       /* As in npxdrop(). */
  946                 fpurstor(addr);
  947                 intr_restore(s);
  948         } else {
  949                 intr_restore(s);
  950                 bcopy(addr, &td->td_pcb->pcb_save, sizeof(*addr));
  951         }
  952         curthread->td_pcb->pcb_flags |= PCB_NPXINITDONE;
  953 }
  954 
  955 static void
  956 fpusave(addr)
  957         union savefpu *addr;
  958 {
  959         
  960 #ifdef CPU_ENABLE_SSE
  961         if (cpu_fxsr)
  962                 fxsave(addr);
  963         else
  964 #endif
  965                 fnsave(addr);
  966 }
  967 
  968 #ifdef CPU_ENABLE_SSE
  969 /*
  970  * On AuthenticAMD processors, the fxrstor instruction does not restore
  971  * the x87's stored last instruction pointer, last data pointer, and last
  972  * opcode values, except in the rare case in which the exception summary
  973  * (ES) bit in the x87 status word is set to 1.
  974  *
  975  * In order to avoid leaking this information across processes, we clean
  976  * these values by performing a dummy load before executing fxrstor().
  977  */
  978 static  double  dummy_variable = 0.0;
  979 static void
  980 fpu_clean_state(void)
  981 {
  982         u_short status;
  983 
  984         /*
  985          * Clear the ES bit in the x87 status word if it is currently
  986          * set, in order to avoid causing a fault in the upcoming load.
  987          */
  988         fnstsw(&status);
  989         if (status & 0x80)
  990                 fnclex();
  991 
  992         /*
  993          * Load the dummy variable into the x87 stack.  This mangles
  994          * the x87 stack, but we don't care since we're about to call
  995          * fxrstor() anyway.
  996          */
  997         __asm __volatile("ffree %%st(7); fld %0" : : "m" (dummy_variable));
  998 }
  999 #endif /* CPU_ENABLE_SSE */
 1000 
 1001 static void
 1002 fpurstor(addr)
 1003         union savefpu *addr;
 1004 {
 1005 
 1006 #ifdef CPU_ENABLE_SSE
 1007         if (cpu_fxsr) {
 1008                 fpu_clean_state();
 1009                 fxrstor(addr);
 1010         } else
 1011 #endif
 1012                 frstor(addr);
 1013 }
 1014 
 1015 #ifdef I586_CPU_XXX
 1016 static long
 1017 timezero(funcname, func)
 1018         const char *funcname;
 1019         void (*func)(void *buf, size_t len);
 1020 
 1021 {
 1022         void *buf;
 1023 #define BUFSIZE         1048576
 1024         long usec;
 1025         struct timeval finish, start;
 1026 
 1027         buf = malloc(BUFSIZE, M_TEMP, M_NOWAIT);
 1028         if (buf == NULL)
 1029                 return (BUFSIZE);
 1030         microtime(&start);
 1031         (*func)(buf, BUFSIZE);
 1032         microtime(&finish);
 1033         usec = 1000000 * (finish.tv_sec - start.tv_sec) +
 1034             finish.tv_usec - start.tv_usec;
 1035         if (usec <= 0)
 1036                 usec = 1;
 1037         if (bootverbose)
 1038                 printf("%s bandwidth = %u kBps\n", funcname,
 1039                     (u_int32_t)(((BUFSIZE >> 10) * 1000000) / usec));
 1040         free(buf, M_TEMP);
 1041         return (usec);
 1042 }
 1043 #endif /* I586_CPU */
 1044 
 1045 static device_method_t npx_methods[] = {
 1046         /* Device interface */
 1047         DEVMETHOD(device_identify,      npx_identify),
 1048         DEVMETHOD(device_probe,         npx_probe),
 1049         DEVMETHOD(device_attach,        npx_attach),
 1050         DEVMETHOD(device_detach,        bus_generic_detach),
 1051         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
 1052         DEVMETHOD(device_suspend,       bus_generic_suspend),
 1053         DEVMETHOD(device_resume,        bus_generic_resume),
 1054         
 1055         { 0, 0 }
 1056 };
 1057 
 1058 static driver_t npx_driver = {
 1059         "npx",
 1060         npx_methods,
 1061         1,                      /* no softc */
 1062 };
 1063 
 1064 static devclass_t npx_devclass;
 1065 
 1066 /*
 1067  * We prefer to attach to the root nexus so that the usual case (exception 16)
 1068  * doesn't describe the processor as being `on isa'.
 1069  */
 1070 DRIVER_MODULE(npx, nexus, npx_driver, npx_devclass, 0, 0);
 1071 
 1072 #ifdef DEV_ISA
 1073 /*
 1074  * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI.
 1075  */
 1076 static struct isa_pnp_id npxisa_ids[] = {
 1077         { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */
 1078         { 0 }
 1079 };
 1080 
 1081 static int
 1082 npxisa_probe(device_t dev)
 1083 {
 1084         int result;
 1085         if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, npxisa_ids)) <= 0) {
 1086                 device_quiet(dev);
 1087         }
 1088         return(result);
 1089 }
 1090 
 1091 static int
 1092 npxisa_attach(device_t dev)
 1093 {
 1094         return (0);
 1095 }
 1096 
 1097 static device_method_t npxisa_methods[] = {
 1098         /* Device interface */
 1099         DEVMETHOD(device_probe,         npxisa_probe),
 1100         DEVMETHOD(device_attach,        npxisa_attach),
 1101         DEVMETHOD(device_detach,        bus_generic_detach),
 1102         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
 1103         DEVMETHOD(device_suspend,       bus_generic_suspend),
 1104         DEVMETHOD(device_resume,        bus_generic_resume),
 1105         
 1106         { 0, 0 }
 1107 };
 1108 
 1109 static driver_t npxisa_driver = {
 1110         "npxisa",
 1111         npxisa_methods,
 1112         1,                      /* no softc */
 1113 };
 1114 
 1115 static devclass_t npxisa_devclass;
 1116 
 1117 DRIVER_MODULE(npxisa, isa, npxisa_driver, npxisa_devclass, 0, 0);
 1118 #ifndef PC98
 1119 DRIVER_MODULE(npxisa, acpi, npxisa_driver, npxisa_devclass, 0, 0);
 1120 #endif
 1121 #endif /* DEV_ISA */

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