The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/i386/isa/npx.c

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    1 /*-
    2  * Copyright (c) 1990 William Jolitz.
    3  * Copyright (c) 1991 The Regents of the University of California.
    4  * All rights reserved.
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions
    8  * are met:
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  * 4. Neither the name of the University nor the names of its contributors
   15  *    may be used to endorse or promote products derived from this software
   16  *    without specific prior written permission.
   17  *
   18  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   28  * SUCH DAMAGE.
   29  *
   30  *      from: @(#)npx.c 7.2 (Berkeley) 5/12/91
   31  */
   32 
   33 #include <sys/cdefs.h>
   34 __FBSDID("$FreeBSD: releng/7.4/sys/i386/isa/npx.c 191793 2009-05-04 19:19:13Z jhb $");
   35 
   36 #include "opt_cpu.h"
   37 #include "opt_isa.h"
   38 #include "opt_npx.h"
   39 
   40 #include <sys/param.h>
   41 #include <sys/systm.h>
   42 #include <sys/bus.h>
   43 #include <sys/kernel.h>
   44 #include <sys/lock.h>
   45 #include <sys/malloc.h>
   46 #include <sys/module.h>
   47 #include <sys/mutex.h>
   48 #include <sys/mutex.h>
   49 #include <sys/proc.h>
   50 #include <sys/smp.h>
   51 #include <sys/sysctl.h>
   52 #include <machine/bus.h>
   53 #include <sys/rman.h>
   54 #ifdef NPX_DEBUG
   55 #include <sys/syslog.h>
   56 #endif
   57 #include <sys/signalvar.h>
   58 
   59 #include <machine/asmacros.h>
   60 #include <machine/cputypes.h>
   61 #include <machine/frame.h>
   62 #include <machine/md_var.h>
   63 #include <machine/pcb.h>
   64 #include <machine/psl.h>
   65 #include <machine/resource.h>
   66 #include <machine/specialreg.h>
   67 #include <machine/segments.h>
   68 #include <machine/ucontext.h>
   69 
   70 #include <machine/intr_machdep.h>
   71 #ifdef DEV_ISA
   72 #include <isa/isavar.h>
   73 #endif
   74 
   75 #if !defined(CPU_DISABLE_SSE) && defined(I686_CPU)
   76 #define CPU_ENABLE_SSE
   77 #endif
   78 
   79 /*
   80  * 387 and 287 Numeric Coprocessor Extension (NPX) Driver.
   81  */
   82 
   83 /* Configuration flags. */
   84 #define NPX_DISABLE_I586_OPTIMIZED_BCOPY        (1 << 0)
   85 #define NPX_DISABLE_I586_OPTIMIZED_BZERO        (1 << 1)
   86 #define NPX_DISABLE_I586_OPTIMIZED_COPYIO       (1 << 2)
   87 
   88 #if defined(__GNUCLIKE_ASM) && !defined(lint)
   89 
   90 #define fldcw(addr)             __asm("fldcw %0" : : "m" (*(addr)))
   91 #define fnclex()                __asm("fnclex")
   92 #define fninit()                __asm("fninit")
   93 #define fnsave(addr)            __asm __volatile("fnsave %0" : "=m" (*(addr)))
   94 #define fnstcw(addr)            __asm __volatile("fnstcw %0" : "=m" (*(addr)))
   95 #define fnstsw(addr)            __asm __volatile("fnstsw %0" : "=m" (*(addr)))
   96 #define fp_divide_by_0()        __asm("fldz; fld1; fdiv %st,%st(1); fnop")
   97 #define frstor(addr)            __asm("frstor %0" : : "m" (*(addr)))
   98 #ifdef CPU_ENABLE_SSE
   99 #define fxrstor(addr)           __asm("fxrstor %0" : : "m" (*(addr)))
  100 #define fxsave(addr)            __asm __volatile("fxsave %0" : "=m" (*(addr)))
  101 #define ldmxcsr(__csr)          __asm __volatile("ldmxcsr %0" : : "m" (__csr))
  102 #endif
  103 #define start_emulating()       __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \
  104                                       : : "n" (CR0_TS) : "ax")
  105 #define stop_emulating()        __asm("clts")
  106 
  107 #else   /* !(__GNUCLIKE_ASM && !lint) */
  108 
  109 void    fldcw(caddr_t addr);
  110 void    fnclex(void);
  111 void    fninit(void);
  112 void    fnsave(caddr_t addr);
  113 void    fnstcw(caddr_t addr);
  114 void    fnstsw(caddr_t addr);
  115 void    fp_divide_by_0(void);
  116 void    frstor(caddr_t addr);
  117 #ifdef CPU_ENABLE_SSE
  118 void    fxsave(caddr_t addr);
  119 void    fxrstor(caddr_t addr);
  120 #endif
  121 void    start_emulating(void);
  122 void    stop_emulating(void);
  123 
  124 #endif  /* __GNUCLIKE_ASM && !lint */
  125 
  126 #ifdef CPU_ENABLE_SSE
  127 #define GET_FPU_CW(thread) \
  128         (cpu_fxsr ? \
  129                 (thread)->td_pcb->pcb_save.sv_xmm.sv_env.en_cw : \
  130                 (thread)->td_pcb->pcb_save.sv_87.sv_env.en_cw)
  131 #define GET_FPU_SW(thread) \
  132         (cpu_fxsr ? \
  133                 (thread)->td_pcb->pcb_save.sv_xmm.sv_env.en_sw : \
  134                 (thread)->td_pcb->pcb_save.sv_87.sv_env.en_sw)
  135 #define SET_FPU_CW(savefpu, value) do { \
  136         if (cpu_fxsr) \
  137                 (savefpu)->sv_xmm.sv_env.en_cw = (value); \
  138         else \
  139                 (savefpu)->sv_87.sv_env.en_cw = (value); \
  140 } while (0)
  141 #else /* CPU_ENABLE_SSE */
  142 #define GET_FPU_CW(thread) \
  143         (thread->td_pcb->pcb_save.sv_87.sv_env.en_cw)
  144 #define GET_FPU_SW(thread) \
  145         (thread->td_pcb->pcb_save.sv_87.sv_env.en_sw)
  146 #define SET_FPU_CW(savefpu, value) \
  147         (savefpu)->sv_87.sv_env.en_cw = (value)
  148 #endif /* CPU_ENABLE_SSE */
  149 
  150 typedef u_char bool_t;
  151 
  152 #ifdef CPU_ENABLE_SSE
  153 static  void    fpu_clean_state(void);
  154 #endif
  155 
  156 static  void    fpusave(union savefpu *);
  157 static  void    fpurstor(union savefpu *);
  158 static  int     npx_attach(device_t dev);
  159 static  void    npx_identify(driver_t *driver, device_t parent);
  160 static  int     npx_intr(void *);
  161 static  int     npx_probe(device_t dev);
  162 #ifdef I586_CPU_XXX
  163 static  long    timezero(const char *funcname,
  164                     void (*func)(void *buf, size_t len));
  165 #endif /* I586_CPU */
  166 
  167 int     hw_float;               /* XXX currently just alias for npx_exists */
  168 
  169 SYSCTL_INT(_hw, HW_FLOATINGPT, floatingpoint, CTLFLAG_RD,
  170     &hw_float, 0, "Floating point instructions executed in hardware");
  171 
  172 static  volatile u_int          npx_intrs_while_probing;
  173 static  volatile u_int          npx_traps_while_probing;
  174 
  175 static  union savefpu           npx_initialstate;
  176 static  bool_t                  npx_ex16;
  177 static  bool_t                  npx_exists;
  178 static  bool_t                  npx_irq13;
  179 
  180 alias_for_inthand_t probetrap;
  181 __asm("                                                         \n\
  182         .text                                                   \n\
  183         .p2align 2,0x90                                         \n\
  184         .type   " __XSTRING(CNAME(probetrap)) ",@function       \n\
  185 " __XSTRING(CNAME(probetrap)) ":                                \n\
  186         ss                                                      \n\
  187         incl    " __XSTRING(CNAME(npx_traps_while_probing)) "   \n\
  188         fnclex                                                  \n\
  189         iret                                                    \n\
  190 ");
  191 
  192 /*
  193  * Identify routine.  Create a connection point on our parent for probing.
  194  */
  195 static void
  196 npx_identify(driver, parent)
  197         driver_t *driver;
  198         device_t parent;
  199 {
  200         device_t child;
  201 
  202         child = BUS_ADD_CHILD(parent, 0, "npx", 0);
  203         if (child == NULL)
  204                 panic("npx_identify");
  205 }
  206 
  207 /*
  208  * Do minimal handling of npx interrupts to convert them to traps.
  209  */
  210 static int
  211 npx_intr(dummy)
  212         void *dummy;
  213 {
  214         struct thread *td;
  215 
  216         npx_intrs_while_probing++;
  217 
  218         /*
  219          * The BUSY# latch must be cleared in all cases so that the next
  220          * unmasked npx exception causes an interrupt.
  221          */
  222         outb(IO_NPX, 0);
  223 
  224         /*
  225          * fpcurthread is normally non-null here.  In that case, schedule an
  226          * AST to finish the exception handling in the correct context
  227          * (this interrupt may occur after the thread has entered the
  228          * kernel via a syscall or an interrupt).  Otherwise, the npx
  229          * state of the thread that caused this interrupt must have been
  230          * pushed to the thread's pcb, and clearing of the busy latch
  231          * above has finished the (essentially null) handling of this
  232          * interrupt.  Control will eventually return to the instruction
  233          * that caused it and it will repeat.  We will eventually (usually
  234          * soon) win the race to handle the interrupt properly.
  235          */
  236         td = PCPU_GET(fpcurthread);
  237         if (td != NULL) {
  238                 td->td_pcb->pcb_flags |= PCB_NPXTRAP;
  239                 thread_lock(td);
  240                 td->td_flags |= TDF_ASTPENDING;
  241                 thread_unlock(td);
  242         }
  243         return (FILTER_HANDLED);
  244 }
  245 
  246 /*
  247  * Probe routine.  Set flags to tell npxattach() what to do.  Set up an
  248  * interrupt handler if npx needs to use interrupts.
  249  */
  250 static int
  251 npx_probe(dev)
  252         device_t dev;
  253 {
  254         struct gate_descriptor save_idt_npxtrap;
  255         struct resource *ioport_res, *irq_res;
  256         void *irq_cookie;
  257         int ioport_rid, irq_num, irq_rid;
  258         u_short control;
  259         u_short status;
  260 
  261         device_set_desc(dev, "math processor");
  262 
  263         /*
  264          * Modern CPUs all have an FPU that uses the INT16 interface
  265          * and provide a simple way to verify that, so handle the
  266          * common case right away.
  267          */
  268         if (cpu_feature & CPUID_FPU) {
  269                 hw_float = npx_exists = 1;
  270                 npx_ex16 = 1;
  271                 device_quiet(dev);
  272                 return (0);
  273         }
  274 
  275         save_idt_npxtrap = idt[IDT_MF];
  276         setidt(IDT_MF, probetrap, SDT_SYS386TGT, SEL_KPL,
  277             GSEL(GCODE_SEL, SEL_KPL));
  278         ioport_rid = 0;
  279         ioport_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &ioport_rid,
  280             IO_NPX, IO_NPX + IO_NPXSIZE - 1, IO_NPXSIZE, RF_ACTIVE);
  281         if (ioport_res == NULL)
  282                 panic("npx: can't get ports");
  283         if (resource_int_value("npx", 0, "irq", &irq_num) != 0)
  284                 irq_num = IRQ_NPX;
  285         irq_rid = 0;
  286         irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &irq_rid, irq_num,
  287             irq_num, 1, RF_ACTIVE);
  288         if (irq_res != NULL) {
  289                 if (bus_setup_intr(dev, irq_res, INTR_TYPE_MISC,
  290                         npx_intr, NULL, NULL, &irq_cookie) != 0)
  291                         panic("npx: can't create intr");
  292         }
  293 
  294         /*
  295          * Partially reset the coprocessor, if any.  Some BIOS's don't reset
  296          * it after a warm boot.
  297          */
  298         npx_full_reset();
  299         outb(IO_NPX, 0);
  300 
  301         /*
  302          * Don't trap while we're probing.
  303          */
  304         stop_emulating();
  305 
  306         /*
  307          * Finish resetting the coprocessor, if any.  If there is an error
  308          * pending, then we may get a bogus IRQ13, but npx_intr() will handle
  309          * it OK.  Bogus halts have never been observed, but we enabled
  310          * IRQ13 and cleared the BUSY# latch early to handle them anyway.
  311          */
  312         fninit();
  313 
  314         /*
  315          * Don't use fwait here because it might hang.
  316          * Don't use fnop here because it usually hangs if there is no FPU.
  317          */
  318         DELAY(1000);            /* wait for any IRQ13 */
  319 #ifdef DIAGNOSTIC
  320         if (npx_intrs_while_probing != 0)
  321                 printf("fninit caused %u bogus npx interrupt(s)\n",
  322                        npx_intrs_while_probing);
  323         if (npx_traps_while_probing != 0)
  324                 printf("fninit caused %u bogus npx trap(s)\n",
  325                        npx_traps_while_probing);
  326 #endif
  327         /*
  328          * Check for a status of mostly zero.
  329          */
  330         status = 0x5a5a;
  331         fnstsw(&status);
  332         if ((status & 0xb8ff) == 0) {
  333                 /*
  334                  * Good, now check for a proper control word.
  335                  */
  336                 control = 0x5a5a;
  337                 fnstcw(&control);
  338                 if ((control & 0x1f3f) == 0x033f) {
  339                         hw_float = npx_exists = 1;
  340                         /*
  341                          * We have an npx, now divide by 0 to see if exception
  342                          * 16 works.
  343                          */
  344                         control &= ~(1 << 2);   /* enable divide by 0 trap */
  345                         fldcw(&control);
  346 #ifdef FPU_ERROR_BROKEN
  347                         /*
  348                          * FPU error signal doesn't work on some CPU
  349                          * accelerator board.
  350                          */
  351                         npx_ex16 = 1;
  352                         return (0);
  353 #endif
  354                         npx_traps_while_probing = npx_intrs_while_probing = 0;
  355                         fp_divide_by_0();
  356                         DELAY(1000);    /* wait for any IRQ13 */
  357                         if (npx_traps_while_probing != 0) {
  358                                 /*
  359                                  * Good, exception 16 works.
  360                                  */
  361                                 npx_ex16 = 1;
  362                                 goto no_irq13;
  363                         }
  364                         if (npx_intrs_while_probing != 0) {
  365                                 /*
  366                                  * Bad, we are stuck with IRQ13.
  367                                  */
  368                                 npx_irq13 = 1;
  369                                 idt[IDT_MF] = save_idt_npxtrap;
  370 #ifdef SMP
  371                                 if (mp_ncpus > 1)
  372                                         panic("npx0 cannot use IRQ 13 on an SMP system");
  373 #endif
  374                                 return (0);
  375                         }
  376                         /*
  377                          * Worse, even IRQ13 is broken.
  378                          */
  379                 }
  380         }
  381 
  382         /* Probe failed.  Floating point simply won't work. */
  383         device_printf(dev, "WARNING: no FPU!\n");
  384 
  385         /* FALLTHROUGH */
  386 no_irq13:
  387         idt[IDT_MF] = save_idt_npxtrap;
  388         if (irq_res != NULL) {
  389                 bus_teardown_intr(dev, irq_res, irq_cookie);
  390                 bus_release_resource(dev, SYS_RES_IRQ, irq_rid, irq_res);
  391         }
  392         bus_release_resource(dev, SYS_RES_IOPORT, ioport_rid, ioport_res);
  393         return (npx_exists ? 0 : ENXIO);
  394 }
  395 
  396 /*
  397  * Attach routine - announce which it is, and wire into system
  398  */
  399 static int
  400 npx_attach(dev)
  401         device_t dev;
  402 {
  403         int flags;
  404         register_t s;
  405 
  406         flags = device_get_flags(dev);
  407 
  408         if (npx_irq13)
  409                 device_printf(dev, "IRQ 13 interface\n");
  410         else if (!device_is_quiet(dev) || bootverbose)
  411                 device_printf(dev, "INT 16 interface\n");
  412 
  413         npxinit();
  414 
  415         s = intr_disable();
  416         stop_emulating();
  417         fpusave(&npx_initialstate);
  418         start_emulating();
  419 #ifdef CPU_ENABLE_SSE
  420         if (cpu_fxsr) {
  421                 if (npx_initialstate.sv_xmm.sv_env.en_mxcsr_mask)
  422                         cpu_mxcsr_mask = 
  423                             npx_initialstate.sv_xmm.sv_env.en_mxcsr_mask;
  424                 else
  425                         cpu_mxcsr_mask = 0xFFBF;
  426                 bzero(npx_initialstate.sv_xmm.sv_fp,
  427                     sizeof(npx_initialstate.sv_xmm.sv_fp));
  428                 bzero(npx_initialstate.sv_xmm.sv_xmm,
  429                     sizeof(npx_initialstate.sv_xmm.sv_xmm));
  430                 /* XXX might need even more zeroing. */
  431         } else
  432 #endif
  433                 bzero(npx_initialstate.sv_87.sv_ac,
  434                     sizeof(npx_initialstate.sv_87.sv_ac));
  435         intr_restore(s);
  436 #ifdef I586_CPU_XXX
  437         if (cpu_class == CPUCLASS_586 && npx_ex16 &&
  438             timezero("i586_bzero()", i586_bzero) <
  439             timezero("bzero()", bzero) * 4 / 5) {
  440                 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY))
  441                         bcopy_vector = i586_bcopy;
  442                 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BZERO))
  443                         bzero_vector = i586_bzero;
  444                 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_COPYIO)) {
  445                         copyin_vector = i586_copyin;
  446                         copyout_vector = i586_copyout;
  447                 }
  448         }
  449 #endif
  450 
  451         return (0);             /* XXX unused */
  452 }
  453 
  454 /*
  455  * Initialize floating point unit.
  456  */
  457 void
  458 npxinit(void)
  459 {
  460         static union savefpu dummy;
  461         register_t savecrit;
  462         u_short control;
  463 
  464         if (!npx_exists)
  465                 return;
  466         /*
  467          * fninit has the same h/w bugs as fnsave.  Use the detoxified
  468          * fnsave to throw away any junk in the fpu.  npxsave() initializes
  469          * the fpu and sets fpcurthread = NULL as important side effects.
  470          */
  471         savecrit = intr_disable();
  472         npxsave(&dummy);
  473         stop_emulating();
  474 #ifdef CPU_ENABLE_SSE
  475         /* XXX npxsave() doesn't actually initialize the fpu in the SSE case. */
  476         if (cpu_fxsr)
  477                 fninit();
  478 #endif
  479         control = __INITIAL_NPXCW__;
  480         fldcw(&control);
  481         start_emulating();
  482         intr_restore(savecrit);
  483 }
  484 
  485 /*
  486  * Free coprocessor (if we have it).
  487  */
  488 void
  489 npxexit(td)
  490         struct thread *td;
  491 {
  492         register_t savecrit;
  493 
  494         savecrit = intr_disable();
  495         if (curthread == PCPU_GET(fpcurthread))
  496                 npxsave(&PCPU_GET(curpcb)->pcb_save);
  497         intr_restore(savecrit);
  498 #ifdef NPX_DEBUG
  499         if (npx_exists) {
  500                 u_int   masked_exceptions;
  501 
  502                 masked_exceptions = GET_FPU_CW(td) & GET_FPU_SW(td) & 0x7f;
  503                 /*
  504                  * Log exceptions that would have trapped with the old
  505                  * control word (overflow, divide by 0, and invalid operand).
  506                  */
  507                 if (masked_exceptions & 0x0d)
  508                         log(LOG_ERR,
  509         "pid %d (%s) exited with masked floating point exceptions 0x%02x\n",
  510                             td->td_proc->p_pid, td->td_proc->p_comm,
  511                             masked_exceptions);
  512         }
  513 #endif
  514 }
  515 
  516 int
  517 npxformat()
  518 {
  519 
  520         if (!npx_exists)
  521                 return (_MC_FPFMT_NODEV);
  522 #ifdef  CPU_ENABLE_SSE
  523         if (cpu_fxsr)
  524                 return (_MC_FPFMT_XMM);
  525 #endif
  526         return (_MC_FPFMT_387);
  527 }
  528 
  529 /* 
  530  * The following mechanism is used to ensure that the FPE_... value
  531  * that is passed as a trapcode to the signal handler of the user
  532  * process does not have more than one bit set.
  533  * 
  534  * Multiple bits may be set if the user process modifies the control
  535  * word while a status word bit is already set.  While this is a sign
  536  * of bad coding, we have no choise than to narrow them down to one
  537  * bit, since we must not send a trapcode that is not exactly one of
  538  * the FPE_ macros.
  539  *
  540  * The mechanism has a static table with 127 entries.  Each combination
  541  * of the 7 FPU status word exception bits directly translates to a
  542  * position in this table, where a single FPE_... value is stored.
  543  * This FPE_... value stored there is considered the "most important"
  544  * of the exception bits and will be sent as the signal code.  The
  545  * precedence of the bits is based upon Intel Document "Numerical
  546  * Applications", Chapter "Special Computational Situations".
  547  *
  548  * The macro to choose one of these values does these steps: 1) Throw
  549  * away status word bits that cannot be masked.  2) Throw away the bits
  550  * currently masked in the control word, assuming the user isn't
  551  * interested in them anymore.  3) Reinsert status word bit 7 (stack
  552  * fault) if it is set, which cannot be masked but must be presered.
  553  * 4) Use the remaining bits to point into the trapcode table.
  554  *
  555  * The 6 maskable bits in order of their preference, as stated in the
  556  * above referenced Intel manual:
  557  * 1  Invalid operation (FP_X_INV)
  558  * 1a   Stack underflow
  559  * 1b   Stack overflow
  560  * 1c   Operand of unsupported format
  561  * 1d   SNaN operand.
  562  * 2  QNaN operand (not an exception, irrelavant here)
  563  * 3  Any other invalid-operation not mentioned above or zero divide
  564  *      (FP_X_INV, FP_X_DZ)
  565  * 4  Denormal operand (FP_X_DNML)
  566  * 5  Numeric over/underflow (FP_X_OFL, FP_X_UFL)
  567  * 6  Inexact result (FP_X_IMP) 
  568  */
  569 static char fpetable[128] = {
  570         0,
  571         FPE_FLTINV,     /*  1 - INV */
  572         FPE_FLTUND,     /*  2 - DNML */
  573         FPE_FLTINV,     /*  3 - INV | DNML */
  574         FPE_FLTDIV,     /*  4 - DZ */
  575         FPE_FLTINV,     /*  5 - INV | DZ */
  576         FPE_FLTDIV,     /*  6 - DNML | DZ */
  577         FPE_FLTINV,     /*  7 - INV | DNML | DZ */
  578         FPE_FLTOVF,     /*  8 - OFL */
  579         FPE_FLTINV,     /*  9 - INV | OFL */
  580         FPE_FLTUND,     /*  A - DNML | OFL */
  581         FPE_FLTINV,     /*  B - INV | DNML | OFL */
  582         FPE_FLTDIV,     /*  C - DZ | OFL */
  583         FPE_FLTINV,     /*  D - INV | DZ | OFL */
  584         FPE_FLTDIV,     /*  E - DNML | DZ | OFL */
  585         FPE_FLTINV,     /*  F - INV | DNML | DZ | OFL */
  586         FPE_FLTUND,     /* 10 - UFL */
  587         FPE_FLTINV,     /* 11 - INV | UFL */
  588         FPE_FLTUND,     /* 12 - DNML | UFL */
  589         FPE_FLTINV,     /* 13 - INV | DNML | UFL */
  590         FPE_FLTDIV,     /* 14 - DZ | UFL */
  591         FPE_FLTINV,     /* 15 - INV | DZ | UFL */
  592         FPE_FLTDIV,     /* 16 - DNML | DZ | UFL */
  593         FPE_FLTINV,     /* 17 - INV | DNML | DZ | UFL */
  594         FPE_FLTOVF,     /* 18 - OFL | UFL */
  595         FPE_FLTINV,     /* 19 - INV | OFL | UFL */
  596         FPE_FLTUND,     /* 1A - DNML | OFL | UFL */
  597         FPE_FLTINV,     /* 1B - INV | DNML | OFL | UFL */
  598         FPE_FLTDIV,     /* 1C - DZ | OFL | UFL */
  599         FPE_FLTINV,     /* 1D - INV | DZ | OFL | UFL */
  600         FPE_FLTDIV,     /* 1E - DNML | DZ | OFL | UFL */
  601         FPE_FLTINV,     /* 1F - INV | DNML | DZ | OFL | UFL */
  602         FPE_FLTRES,     /* 20 - IMP */
  603         FPE_FLTINV,     /* 21 - INV | IMP */
  604         FPE_FLTUND,     /* 22 - DNML | IMP */
  605         FPE_FLTINV,     /* 23 - INV | DNML | IMP */
  606         FPE_FLTDIV,     /* 24 - DZ | IMP */
  607         FPE_FLTINV,     /* 25 - INV | DZ | IMP */
  608         FPE_FLTDIV,     /* 26 - DNML | DZ | IMP */
  609         FPE_FLTINV,     /* 27 - INV | DNML | DZ | IMP */
  610         FPE_FLTOVF,     /* 28 - OFL | IMP */
  611         FPE_FLTINV,     /* 29 - INV | OFL | IMP */
  612         FPE_FLTUND,     /* 2A - DNML | OFL | IMP */
  613         FPE_FLTINV,     /* 2B - INV | DNML | OFL | IMP */
  614         FPE_FLTDIV,     /* 2C - DZ | OFL | IMP */
  615         FPE_FLTINV,     /* 2D - INV | DZ | OFL | IMP */
  616         FPE_FLTDIV,     /* 2E - DNML | DZ | OFL | IMP */
  617         FPE_FLTINV,     /* 2F - INV | DNML | DZ | OFL | IMP */
  618         FPE_FLTUND,     /* 30 - UFL | IMP */
  619         FPE_FLTINV,     /* 31 - INV | UFL | IMP */
  620         FPE_FLTUND,     /* 32 - DNML | UFL | IMP */
  621         FPE_FLTINV,     /* 33 - INV | DNML | UFL | IMP */
  622         FPE_FLTDIV,     /* 34 - DZ | UFL | IMP */
  623         FPE_FLTINV,     /* 35 - INV | DZ | UFL | IMP */
  624         FPE_FLTDIV,     /* 36 - DNML | DZ | UFL | IMP */
  625         FPE_FLTINV,     /* 37 - INV | DNML | DZ | UFL | IMP */
  626         FPE_FLTOVF,     /* 38 - OFL | UFL | IMP */
  627         FPE_FLTINV,     /* 39 - INV | OFL | UFL | IMP */
  628         FPE_FLTUND,     /* 3A - DNML | OFL | UFL | IMP */
  629         FPE_FLTINV,     /* 3B - INV | DNML | OFL | UFL | IMP */
  630         FPE_FLTDIV,     /* 3C - DZ | OFL | UFL | IMP */
  631         FPE_FLTINV,     /* 3D - INV | DZ | OFL | UFL | IMP */
  632         FPE_FLTDIV,     /* 3E - DNML | DZ | OFL | UFL | IMP */
  633         FPE_FLTINV,     /* 3F - INV | DNML | DZ | OFL | UFL | IMP */
  634         FPE_FLTSUB,     /* 40 - STK */
  635         FPE_FLTSUB,     /* 41 - INV | STK */
  636         FPE_FLTUND,     /* 42 - DNML | STK */
  637         FPE_FLTSUB,     /* 43 - INV | DNML | STK */
  638         FPE_FLTDIV,     /* 44 - DZ | STK */
  639         FPE_FLTSUB,     /* 45 - INV | DZ | STK */
  640         FPE_FLTDIV,     /* 46 - DNML | DZ | STK */
  641         FPE_FLTSUB,     /* 47 - INV | DNML | DZ | STK */
  642         FPE_FLTOVF,     /* 48 - OFL | STK */
  643         FPE_FLTSUB,     /* 49 - INV | OFL | STK */
  644         FPE_FLTUND,     /* 4A - DNML | OFL | STK */
  645         FPE_FLTSUB,     /* 4B - INV | DNML | OFL | STK */
  646         FPE_FLTDIV,     /* 4C - DZ | OFL | STK */
  647         FPE_FLTSUB,     /* 4D - INV | DZ | OFL | STK */
  648         FPE_FLTDIV,     /* 4E - DNML | DZ | OFL | STK */
  649         FPE_FLTSUB,     /* 4F - INV | DNML | DZ | OFL | STK */
  650         FPE_FLTUND,     /* 50 - UFL | STK */
  651         FPE_FLTSUB,     /* 51 - INV | UFL | STK */
  652         FPE_FLTUND,     /* 52 - DNML | UFL | STK */
  653         FPE_FLTSUB,     /* 53 - INV | DNML | UFL | STK */
  654         FPE_FLTDIV,     /* 54 - DZ | UFL | STK */
  655         FPE_FLTSUB,     /* 55 - INV | DZ | UFL | STK */
  656         FPE_FLTDIV,     /* 56 - DNML | DZ | UFL | STK */
  657         FPE_FLTSUB,     /* 57 - INV | DNML | DZ | UFL | STK */
  658         FPE_FLTOVF,     /* 58 - OFL | UFL | STK */
  659         FPE_FLTSUB,     /* 59 - INV | OFL | UFL | STK */
  660         FPE_FLTUND,     /* 5A - DNML | OFL | UFL | STK */
  661         FPE_FLTSUB,     /* 5B - INV | DNML | OFL | UFL | STK */
  662         FPE_FLTDIV,     /* 5C - DZ | OFL | UFL | STK */
  663         FPE_FLTSUB,     /* 5D - INV | DZ | OFL | UFL | STK */
  664         FPE_FLTDIV,     /* 5E - DNML | DZ | OFL | UFL | STK */
  665         FPE_FLTSUB,     /* 5F - INV | DNML | DZ | OFL | UFL | STK */
  666         FPE_FLTRES,     /* 60 - IMP | STK */
  667         FPE_FLTSUB,     /* 61 - INV | IMP | STK */
  668         FPE_FLTUND,     /* 62 - DNML | IMP | STK */
  669         FPE_FLTSUB,     /* 63 - INV | DNML | IMP | STK */
  670         FPE_FLTDIV,     /* 64 - DZ | IMP | STK */
  671         FPE_FLTSUB,     /* 65 - INV | DZ | IMP | STK */
  672         FPE_FLTDIV,     /* 66 - DNML | DZ | IMP | STK */
  673         FPE_FLTSUB,     /* 67 - INV | DNML | DZ | IMP | STK */
  674         FPE_FLTOVF,     /* 68 - OFL | IMP | STK */
  675         FPE_FLTSUB,     /* 69 - INV | OFL | IMP | STK */
  676         FPE_FLTUND,     /* 6A - DNML | OFL | IMP | STK */
  677         FPE_FLTSUB,     /* 6B - INV | DNML | OFL | IMP | STK */
  678         FPE_FLTDIV,     /* 6C - DZ | OFL | IMP | STK */
  679         FPE_FLTSUB,     /* 6D - INV | DZ | OFL | IMP | STK */
  680         FPE_FLTDIV,     /* 6E - DNML | DZ | OFL | IMP | STK */
  681         FPE_FLTSUB,     /* 6F - INV | DNML | DZ | OFL | IMP | STK */
  682         FPE_FLTUND,     /* 70 - UFL | IMP | STK */
  683         FPE_FLTSUB,     /* 71 - INV | UFL | IMP | STK */
  684         FPE_FLTUND,     /* 72 - DNML | UFL | IMP | STK */
  685         FPE_FLTSUB,     /* 73 - INV | DNML | UFL | IMP | STK */
  686         FPE_FLTDIV,     /* 74 - DZ | UFL | IMP | STK */
  687         FPE_FLTSUB,     /* 75 - INV | DZ | UFL | IMP | STK */
  688         FPE_FLTDIV,     /* 76 - DNML | DZ | UFL | IMP | STK */
  689         FPE_FLTSUB,     /* 77 - INV | DNML | DZ | UFL | IMP | STK */
  690         FPE_FLTOVF,     /* 78 - OFL | UFL | IMP | STK */
  691         FPE_FLTSUB,     /* 79 - INV | OFL | UFL | IMP | STK */
  692         FPE_FLTUND,     /* 7A - DNML | OFL | UFL | IMP | STK */
  693         FPE_FLTSUB,     /* 7B - INV | DNML | OFL | UFL | IMP | STK */
  694         FPE_FLTDIV,     /* 7C - DZ | OFL | UFL | IMP | STK */
  695         FPE_FLTSUB,     /* 7D - INV | DZ | OFL | UFL | IMP | STK */
  696         FPE_FLTDIV,     /* 7E - DNML | DZ | OFL | UFL | IMP | STK */
  697         FPE_FLTSUB,     /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */
  698 };
  699 
  700 /*
  701  * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE.
  702  *
  703  * Clearing exceptions is necessary mainly to avoid IRQ13 bugs.  We now
  704  * depend on longjmp() restoring a usable state.  Restoring the state
  705  * or examining it might fail if we didn't clear exceptions.
  706  *
  707  * The error code chosen will be one of the FPE_... macros. It will be
  708  * sent as the second argument to old BSD-style signal handlers and as
  709  * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers.
  710  *
  711  * XXX the FP state is not preserved across signal handlers.  So signal
  712  * handlers cannot afford to do FP unless they preserve the state or
  713  * longjmp() out.  Both preserving the state and longjmp()ing may be
  714  * destroyed by IRQ13 bugs.  Clearing FP exceptions is not an acceptable
  715  * solution for signals other than SIGFPE.
  716  */
  717 int
  718 npxtrap()
  719 {
  720         register_t savecrit;
  721         u_short control, status;
  722 
  723         if (!npx_exists) {
  724                 printf("npxtrap: fpcurthread = %p, curthread = %p, npx_exists = %d\n",
  725                        PCPU_GET(fpcurthread), curthread, npx_exists);
  726                 panic("npxtrap from nowhere");
  727         }
  728         savecrit = intr_disable();
  729 
  730         /*
  731          * Interrupt handling (for another interrupt) may have pushed the
  732          * state to memory.  Fetch the relevant parts of the state from
  733          * wherever they are.
  734          */
  735         if (PCPU_GET(fpcurthread) != curthread) {
  736                 control = GET_FPU_CW(curthread);
  737                 status = GET_FPU_SW(curthread);
  738         } else {
  739                 fnstcw(&control);
  740                 fnstsw(&status);
  741         }
  742 
  743         if (PCPU_GET(fpcurthread) == curthread)
  744                 fnclex();
  745         intr_restore(savecrit);
  746         return (fpetable[status & ((~control & 0x3f) | 0x40)]);
  747 }
  748 
  749 /*
  750  * Implement device not available (DNA) exception
  751  *
  752  * It would be better to switch FP context here (if curthread != fpcurthread)
  753  * and not necessarily for every context switch, but it is too hard to
  754  * access foreign pcb's.
  755  */
  756 
  757 static int err_count = 0;
  758 
  759 int
  760 npxdna(void)
  761 {
  762         struct pcb *pcb;
  763         register_t s;
  764 
  765         if (!npx_exists)
  766                 return (0);
  767         if (PCPU_GET(fpcurthread) == curthread) {
  768                 printf("npxdna: fpcurthread == curthread %d times\n",
  769                     ++err_count);
  770                 stop_emulating();
  771                 return (1);
  772         }
  773         if (PCPU_GET(fpcurthread) != NULL) {
  774                 printf("npxdna: fpcurthread = %p (%d), curthread = %p (%d)\n",
  775                        PCPU_GET(fpcurthread),
  776                        PCPU_GET(fpcurthread)->td_proc->p_pid,
  777                        curthread, curthread->td_proc->p_pid);
  778                 panic("npxdna");
  779         }
  780         s = intr_disable();
  781         stop_emulating();
  782         /*
  783          * Record new context early in case frstor causes an IRQ13.
  784          */
  785         PCPU_SET(fpcurthread, curthread);
  786         pcb = PCPU_GET(curpcb);
  787 
  788 #ifdef CPU_ENABLE_SSE
  789         if (cpu_fxsr)
  790                 fpu_clean_state();
  791 #endif
  792 
  793         if ((pcb->pcb_flags & PCB_NPXINITDONE) == 0) {
  794                 /*
  795                  * This is the first time this thread has used the FPU or
  796                  * the PCB doesn't contain a clean FPU state.  Explicitly
  797                  * load an initial state.
  798                  */
  799                 fpurstor(&npx_initialstate);
  800                 if (pcb->pcb_initial_npxcw != __INITIAL_NPXCW__)
  801                         fldcw(&pcb->pcb_initial_npxcw);
  802                 pcb->pcb_flags |= PCB_NPXINITDONE;
  803         } else {
  804                 /*
  805                  * The following fpurstor() may cause an IRQ13 when the
  806                  * state being restored has a pending error.  The error will
  807                  * appear to have been triggered by the current (npx) user
  808                  * instruction even when that instruction is a no-wait
  809                  * instruction that should not trigger an error (e.g.,
  810                  * fnclex).  On at least one 486 system all of the no-wait
  811                  * instructions are broken the same as frstor, so our
  812                  * treatment does not amplify the breakage.  On at least
  813                  * one 386/Cyrix 387 system, fnclex works correctly while
  814                  * frstor and fnsave are broken, so our treatment breaks
  815                  * fnclex if it is the first FPU instruction after a context
  816                  * switch.
  817                  */
  818                 fpurstor(&pcb->pcb_save);
  819         }
  820         intr_restore(s);
  821 
  822         return (1);
  823 }
  824 
  825 /*
  826  * Wrapper for fnsave instruction, partly to handle hardware bugs.  When npx
  827  * exceptions are reported via IRQ13, spurious IRQ13's may be triggered by
  828  * no-wait npx instructions.  See the Intel application note AP-578 for
  829  * details.  This doesn't cause any additional complications here.  IRQ13's
  830  * are inherently asynchronous unless the CPU is frozen to deliver them --
  831  * one that started in userland may be delivered many instructions later,
  832  * after the process has entered the kernel.  It may even be delivered after
  833  * the fnsave here completes.  A spurious IRQ13 for the fnsave is handled in
  834  * the same way as a very-late-arriving non-spurious IRQ13 from user mode:
  835  * it is normally ignored at first because we set fpcurthread to NULL; it is
  836  * normally retriggered in npxdna() after return to user mode.
  837  *
  838  * npxsave() must be called with interrupts disabled, so that it clears
  839  * fpcurthread atomically with saving the state.  We require callers to do the
  840  * disabling, since most callers need to disable interrupts anyway to call
  841  * npxsave() atomically with checking fpcurthread.
  842  *
  843  * A previous version of npxsave() went to great lengths to excecute fnsave
  844  * with interrupts enabled in case executing it froze the CPU.  This case
  845  * can't happen, at least for Intel CPU/NPX's.  Spurious IRQ13's don't imply
  846  * spurious freezes.
  847  */
  848 void
  849 npxsave(addr)
  850         union savefpu *addr;
  851 {
  852 
  853         stop_emulating();
  854         fpusave(addr);
  855 
  856         start_emulating();
  857         PCPU_SET(fpcurthread, NULL);
  858 }
  859 
  860 /*
  861  * This should be called with interrupts disabled and only when the owning
  862  * FPU thread is non-null.
  863  */
  864 void
  865 npxdrop()
  866 {
  867         struct thread *td;
  868 
  869         /*
  870          * Discard pending exceptions in the !cpu_fxsr case so that unmasked
  871          * ones don't cause a panic on the next frstor.
  872          */
  873 #ifdef CPU_ENABLE_SSE
  874         if (!cpu_fxsr)
  875 #endif
  876                 fnclex();
  877 
  878         td = PCPU_GET(fpcurthread);
  879         PCPU_SET(fpcurthread, NULL);
  880         td->td_pcb->pcb_flags &= ~PCB_NPXINITDONE;
  881         start_emulating();
  882 }
  883 
  884 /*
  885  * Get the state of the FPU without dropping ownership (if possible).
  886  * It returns the FPU ownership status.
  887  */
  888 int
  889 npxgetregs(td, addr)
  890         struct thread *td;
  891         union savefpu *addr;
  892 {
  893         register_t s;
  894 
  895         if (!npx_exists)
  896                 return (_MC_FPOWNED_NONE);
  897 
  898         if ((td->td_pcb->pcb_flags & PCB_NPXINITDONE) == 0) {
  899                 bcopy(&npx_initialstate, addr, sizeof(npx_initialstate));
  900                 SET_FPU_CW(addr, td->td_pcb->pcb_initial_npxcw);
  901                 return (_MC_FPOWNED_NONE);
  902         }
  903         s = intr_disable();
  904         if (td == PCPU_GET(fpcurthread)) {
  905                 fpusave(addr);
  906 #ifdef CPU_ENABLE_SSE
  907                 if (!cpu_fxsr)
  908 #endif
  909                         /*
  910                          * fnsave initializes the FPU and destroys whatever
  911                          * context it contains.  Make sure the FPU owner
  912                          * starts with a clean state next time.
  913                          */
  914                         npxdrop();
  915                 intr_restore(s);
  916                 return (_MC_FPOWNED_FPU);
  917         } else {
  918                 intr_restore(s);
  919                 bcopy(&td->td_pcb->pcb_save, addr, sizeof(*addr));
  920                 return (_MC_FPOWNED_PCB);
  921         }
  922 }
  923 
  924 /*
  925  * Set the state of the FPU.
  926  */
  927 void
  928 npxsetregs(td, addr)
  929         struct thread *td;
  930         union savefpu *addr;
  931 {
  932         register_t s;
  933 
  934         if (!npx_exists)
  935                 return;
  936 
  937         s = intr_disable();
  938         if (td == PCPU_GET(fpcurthread)) {
  939 #ifdef CPU_ENABLE_SSE
  940                 if (!cpu_fxsr)
  941 #endif
  942                         fnclex();       /* As in npxdrop(). */
  943                 fpurstor(addr);
  944                 intr_restore(s);
  945         } else {
  946                 intr_restore(s);
  947                 bcopy(addr, &td->td_pcb->pcb_save, sizeof(*addr));
  948         }
  949         curthread->td_pcb->pcb_flags |= PCB_NPXINITDONE;
  950 }
  951 
  952 static void
  953 fpusave(addr)
  954         union savefpu *addr;
  955 {
  956         
  957 #ifdef CPU_ENABLE_SSE
  958         if (cpu_fxsr)
  959                 fxsave(addr);
  960         else
  961 #endif
  962                 fnsave(addr);
  963 }
  964 
  965 #ifdef CPU_ENABLE_SSE
  966 /*
  967  * On AuthenticAMD processors, the fxrstor instruction does not restore
  968  * the x87's stored last instruction pointer, last data pointer, and last
  969  * opcode values, except in the rare case in which the exception summary
  970  * (ES) bit in the x87 status word is set to 1.
  971  *
  972  * In order to avoid leaking this information across processes, we clean
  973  * these values by performing a dummy load before executing fxrstor().
  974  */
  975 static void
  976 fpu_clean_state(void)
  977 {
  978         static float dummy_variable = 0.0;
  979         u_short status;
  980 
  981         /*
  982          * Clear the ES bit in the x87 status word if it is currently
  983          * set, in order to avoid causing a fault in the upcoming load.
  984          */
  985         fnstsw(&status);
  986         if (status & 0x80)
  987                 fnclex();
  988 
  989         /*
  990          * Load the dummy variable into the x87 stack.  This mangles
  991          * the x87 stack, but we don't care since we're about to call
  992          * fxrstor() anyway.
  993          */
  994         __asm __volatile("ffree %%st(7); fld %0" : : "m" (dummy_variable));
  995 }
  996 #endif /* CPU_ENABLE_SSE */
  997 
  998 static void
  999 fpurstor(addr)
 1000         union savefpu *addr;
 1001 {
 1002 
 1003 #ifdef CPU_ENABLE_SSE
 1004         if (cpu_fxsr)
 1005                 fxrstor(addr);
 1006         else
 1007 #endif
 1008                 frstor(addr);
 1009 }
 1010 
 1011 #ifdef I586_CPU_XXX
 1012 static long
 1013 timezero(funcname, func)
 1014         const char *funcname;
 1015         void (*func)(void *buf, size_t len);
 1016 
 1017 {
 1018         void *buf;
 1019 #define BUFSIZE         1048576
 1020         long usec;
 1021         struct timeval finish, start;
 1022 
 1023         buf = malloc(BUFSIZE, M_TEMP, M_NOWAIT);
 1024         if (buf == NULL)
 1025                 return (BUFSIZE);
 1026         microtime(&start);
 1027         (*func)(buf, BUFSIZE);
 1028         microtime(&finish);
 1029         usec = 1000000 * (finish.tv_sec - start.tv_sec) +
 1030             finish.tv_usec - start.tv_usec;
 1031         if (usec <= 0)
 1032                 usec = 1;
 1033         if (bootverbose)
 1034                 printf("%s bandwidth = %u kBps\n", funcname,
 1035                     (u_int32_t)(((BUFSIZE >> 10) * 1000000) / usec));
 1036         free(buf, M_TEMP);
 1037         return (usec);
 1038 }
 1039 #endif /* I586_CPU */
 1040 
 1041 static device_method_t npx_methods[] = {
 1042         /* Device interface */
 1043         DEVMETHOD(device_identify,      npx_identify),
 1044         DEVMETHOD(device_probe,         npx_probe),
 1045         DEVMETHOD(device_attach,        npx_attach),
 1046         DEVMETHOD(device_detach,        bus_generic_detach),
 1047         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
 1048         DEVMETHOD(device_suspend,       bus_generic_suspend),
 1049         DEVMETHOD(device_resume,        bus_generic_resume),
 1050         
 1051         { 0, 0 }
 1052 };
 1053 
 1054 static driver_t npx_driver = {
 1055         "npx",
 1056         npx_methods,
 1057         1,                      /* no softc */
 1058 };
 1059 
 1060 static devclass_t npx_devclass;
 1061 
 1062 /*
 1063  * We prefer to attach to the root nexus so that the usual case (exception 16)
 1064  * doesn't describe the processor as being `on isa'.
 1065  */
 1066 DRIVER_MODULE(npx, nexus, npx_driver, npx_devclass, 0, 0);
 1067 
 1068 #ifdef DEV_ISA
 1069 /*
 1070  * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI.
 1071  */
 1072 static struct isa_pnp_id npxisa_ids[] = {
 1073         { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */
 1074         { 0 }
 1075 };
 1076 
 1077 static int
 1078 npxisa_probe(device_t dev)
 1079 {
 1080         int result;
 1081         if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, npxisa_ids)) <= 0) {
 1082                 device_quiet(dev);
 1083         }
 1084         return(result);
 1085 }
 1086 
 1087 static int
 1088 npxisa_attach(device_t dev)
 1089 {
 1090         return (0);
 1091 }
 1092 
 1093 static device_method_t npxisa_methods[] = {
 1094         /* Device interface */
 1095         DEVMETHOD(device_probe,         npxisa_probe),
 1096         DEVMETHOD(device_attach,        npxisa_attach),
 1097         DEVMETHOD(device_detach,        bus_generic_detach),
 1098         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
 1099         DEVMETHOD(device_suspend,       bus_generic_suspend),
 1100         DEVMETHOD(device_resume,        bus_generic_resume),
 1101         
 1102         { 0, 0 }
 1103 };
 1104 
 1105 static driver_t npxisa_driver = {
 1106         "npxisa",
 1107         npxisa_methods,
 1108         1,                      /* no softc */
 1109 };
 1110 
 1111 static devclass_t npxisa_devclass;
 1112 
 1113 DRIVER_MODULE(npxisa, isa, npxisa_driver, npxisa_devclass, 0, 0);
 1114 #ifndef PC98
 1115 DRIVER_MODULE(npxisa, acpi, npxisa_driver, npxisa_devclass, 0, 0);
 1116 #endif
 1117 #endif /* DEV_ISA */

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