Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/i386/isa/ppc.c
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1 /*- 2 * Copyright (c) 1997, 1998 Nicolas Souchu 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 #include "ppc.h" 30 31 #if NPPC > 0 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/conf.h> 36 #include <sys/malloc.h> 37 #include <sys/kernel.h> 38 39 #include <machine/clock.h> 40 41 #include <vm/vm.h> 42 #include <vm/vm_param.h> 43 #include <vm/pmap.h> 44 45 #include <i386/isa/isa_device.h> 46 47 #include <dev/ppbus/ppbconf.h> 48 #include <dev/ppbus/ppb_msq.h> 49 50 #include <i386/isa/ppcreg.h> 51 52 #include "opt_ppc.h" 53 54 #define LOG_PPC(function, ppc, string) \ 55 if (bootverbose) printf("%s: %s\n", function, string) 56 57 static int ppcprobe(struct isa_device *); 58 static int ppcattach(struct isa_device *); 59 60 struct isa_driver ppcdriver = { 61 ppcprobe, ppcattach, "ppc" 62 }; 63 64 static struct ppc_data *ppcdata[NPPC]; 65 static int nppc = 0; 66 67 static char *ppc_types[] = { 68 "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306", 69 "82091AA", "Generic", "W83877F", "W83877AF", "Winbond", "PC87334", 0 70 }; 71 72 /* list of available modes */ 73 static char *ppc_avms[] = { 74 "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only", 75 "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only", 76 "ECP/NIBBLE", "ECP/PS2", "ECP/PS2/NIBBLE", "ECP/EPP", 77 "ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0 78 }; 79 80 /* list of current executing modes 81 * Note that few modes do not actually exist. 82 */ 83 static char *ppc_modes[] = { 84 "COMPATIBLE", "NIBBLE", "PS/2", "PS/2", "EPP", 85 "EPP", "EPP", "EPP", "ECP", 86 "ECP", "ECP+PS2", "ECP+PS2", "ECP+EPP", 87 "ECP+EPP", "ECP+EPP", "ECP+EPP", 0 88 }; 89 90 static char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 }; 91 92 /* 93 * BIOS printer list - used by BIOS probe. 94 */ 95 #define BIOS_PPC_PORTS 0x408 96 #define BIOS_PORTS (short *)(KERNBASE+BIOS_PPC_PORTS) 97 #define BIOS_MAX_PPC 4 98 99 /* 100 * All these functions are default actions for IN/OUT operations. 101 * They may be redefined if needed. 102 */ 103 static void ppc_outsb_epp(int unit, char *addr, int cnt) { 104 outsb(ppcdata[unit]->ppc_base + PPC_EPP_DATA, addr, cnt); } 105 static void ppc_outsw_epp(int unit, char *addr, int cnt) { 106 outsw(ppcdata[unit]->ppc_base + PPC_EPP_DATA, addr, cnt); } 107 static void ppc_outsl_epp(int unit, char *addr, int cnt) { 108 outsl(ppcdata[unit]->ppc_base + PPC_EPP_DATA, addr, cnt); } 109 static void ppc_insb_epp(int unit, char *addr, int cnt) { 110 insb(ppcdata[unit]->ppc_base + PPC_EPP_DATA, addr, cnt); } 111 static void ppc_insw_epp(int unit, char *addr, int cnt) { 112 insw(ppcdata[unit]->ppc_base + PPC_EPP_DATA, addr, cnt); } 113 static void ppc_insl_epp(int unit, char *addr, int cnt) { 114 insl(ppcdata[unit]->ppc_base + PPC_EPP_DATA, addr, cnt); } 115 116 static u_char ppc_rdtr(int unit) { return r_dtr(ppcdata[unit]); } 117 static u_char ppc_rstr(int unit) { return r_str(ppcdata[unit]); } 118 static u_char ppc_rctr(int unit) { return r_ctr(ppcdata[unit]); } 119 static u_char ppc_repp(int unit) { return r_epp(ppcdata[unit]); } 120 static u_char ppc_recr(int unit) { return r_ecr(ppcdata[unit]); } 121 static u_char ppc_rfifo(int unit) { return r_fifo(ppcdata[unit]); } 122 123 static void ppc_wdtr(int unit, char byte) { w_dtr(ppcdata[unit], byte); } 124 static void ppc_wstr(int unit, char byte) { w_str(ppcdata[unit], byte); } 125 static void ppc_wctr(int unit, char byte) { w_ctr(ppcdata[unit], byte); } 126 static void ppc_wepp(int unit, char byte) { w_epp(ppcdata[unit], byte); } 127 static void ppc_wecr(int unit, char byte) { w_ecr(ppcdata[unit], byte); } 128 static void ppc_wfifo(int unit, char byte) { w_fifo(ppcdata[unit], byte); } 129 130 static void ppc_reset_epp_timeout(int); 131 static void ppc_ecp_sync(int); 132 static ointhand2_t ppcintr; 133 134 static int ppc_exec_microseq(int, struct ppb_microseq **); 135 static int ppc_generic_setmode(int, int); 136 static int ppc_smclike_setmode(int, int); 137 138 static int ppc_read(int, char *, int, int); 139 static int ppc_write(int, char *, int, int); 140 141 static struct ppb_adapter ppc_smclike_adapter = { 142 143 0, /* no intr handler, filled by chipset dependent code */ 144 145 ppc_reset_epp_timeout, ppc_ecp_sync, 146 147 ppc_exec_microseq, 148 149 ppc_smclike_setmode, ppc_read, ppc_write, 150 151 ppc_outsb_epp, ppc_outsw_epp, ppc_outsl_epp, 152 ppc_insb_epp, ppc_insw_epp, ppc_insl_epp, 153 154 ppc_rdtr, ppc_rstr, ppc_rctr, ppc_repp, ppc_recr, ppc_rfifo, 155 ppc_wdtr, ppc_wstr, ppc_wctr, ppc_wepp, ppc_wecr, ppc_wfifo 156 }; 157 158 static struct ppb_adapter ppc_generic_adapter = { 159 160 0, /* no intr handler, filled by chipset dependent code */ 161 162 ppc_reset_epp_timeout, ppc_ecp_sync, 163 164 ppc_exec_microseq, 165 166 ppc_generic_setmode, ppc_read, ppc_write, 167 168 ppc_outsb_epp, ppc_outsw_epp, ppc_outsl_epp, 169 ppc_insb_epp, ppc_insw_epp, ppc_insl_epp, 170 171 ppc_rdtr, ppc_rstr, ppc_rctr, ppc_repp, ppc_recr, ppc_rfifo, 172 ppc_wdtr, ppc_wstr, ppc_wctr, ppc_wepp, ppc_wecr, ppc_wfifo 173 }; 174 175 /* 176 * ppc_ecp_sync() XXX 177 */ 178 static void 179 ppc_ecp_sync(int unit) { 180 181 struct ppc_data *ppc = ppcdata[unit]; 182 int i, r; 183 184 if (!(ppc->ppc_avm & PPB_ECP)) 185 return; 186 187 r = r_ecr(ppc); 188 if ((r & 0xe0) != PPC_ECR_EPP) 189 return; 190 191 for (i = 0; i < 100; i++) { 192 r = r_ecr(ppc); 193 if (r & 0x1) 194 return; 195 DELAY(100); 196 } 197 198 printf("ppc%d: ECP sync failed as data still " \ 199 "present in FIFO.\n", unit); 200 201 return; 202 } 203 204 /* 205 * ppc_detect_fifo() 206 * 207 * Detect parallel port FIFO 208 */ 209 static int 210 ppc_detect_fifo(struct ppc_data *ppc) 211 { 212 char ecr_sav; 213 char ctr_sav, ctr, cc; 214 short i; 215 216 /* save registers */ 217 ecr_sav = r_ecr(ppc); 218 ctr_sav = r_ctr(ppc); 219 220 /* enter ECP configuration mode, no interrupt, no DMA */ 221 w_ecr(ppc, 0xf4); 222 223 /* read PWord size - transfers in FIFO mode must be PWord aligned */ 224 ppc->ppc_pword = (r_cnfgA(ppc) & PPC_PWORD_MASK); 225 226 /* XXX 16 and 32 bits implementations not supported */ 227 if (ppc->ppc_pword != PPC_PWORD_8) { 228 LOG_PPC(__FUNCTION__, ppc, "PWord not supported"); 229 goto error; 230 } 231 232 w_ecr(ppc, 0x34); /* byte mode, no interrupt, no DMA */ 233 ctr = r_ctr(ppc); 234 w_ctr(ppc, ctr | PCD); /* set direction to 1 */ 235 236 /* enter ECP test mode, no interrupt, no DMA */ 237 w_ecr(ppc, 0xd4); 238 239 /* flush the FIFO */ 240 for (i=0; i<1024; i++) { 241 if (r_ecr(ppc) & PPC_FIFO_EMPTY) 242 break; 243 cc = r_fifo(ppc); 244 } 245 246 if (i >= 1024) { 247 LOG_PPC(__FUNCTION__, ppc, "can't flush FIFO"); 248 goto error; 249 } 250 251 /* enable interrupts, no DMA */ 252 w_ecr(ppc, 0xd0); 253 254 /* determine readIntrThreshold 255 * fill the FIFO until serviceIntr is set 256 */ 257 for (i=0; i<1024; i++) { 258 w_fifo(ppc, (char)i); 259 if (!ppc->ppc_rthr && (r_ecr(ppc) & PPC_SERVICE_INTR)) { 260 /* readThreshold reached */ 261 ppc->ppc_rthr = i+1; 262 } 263 if (r_ecr(ppc) & PPC_FIFO_FULL) { 264 ppc->ppc_fifo = i+1; 265 break; 266 } 267 } 268 269 if (i >= 1024) { 270 LOG_PPC(__FUNCTION__, ppc, "can't fill FIFO"); 271 goto error; 272 } 273 274 w_ecr(ppc, 0xd4); /* test mode, no interrupt, no DMA */ 275 w_ctr(ppc, ctr & ~PCD); /* set direction to 0 */ 276 w_ecr(ppc, 0xd0); /* enable interrupts */ 277 278 /* determine writeIntrThreshold 279 * empty the FIFO until serviceIntr is set 280 */ 281 for (i=ppc->ppc_fifo; i>0; i--) { 282 if (r_fifo(ppc) != (char)(ppc->ppc_fifo-i)) { 283 LOG_PPC(__FUNCTION__, ppc, "invalid data in FIFO"); 284 goto error; 285 } 286 if (r_ecr(ppc) & PPC_SERVICE_INTR) { 287 /* writeIntrThreshold reached */ 288 ppc->ppc_wthr = ppc->ppc_fifo - i+1; 289 } 290 /* if FIFO empty before the last byte, error */ 291 if (i>1 && (r_ecr(ppc) & PPC_FIFO_EMPTY)) { 292 LOG_PPC(__FUNCTION__, ppc, "data lost in FIFO"); 293 goto error; 294 } 295 } 296 297 /* FIFO must be empty after the last byte */ 298 if (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) { 299 LOG_PPC(__FUNCTION__, ppc, "can't empty the FIFO"); 300 goto error; 301 } 302 303 w_ctr(ppc, ctr_sav); 304 w_ecr(ppc, ecr_sav); 305 306 return (0); 307 308 error: 309 w_ctr(ppc, ctr_sav); 310 w_ecr(ppc, ecr_sav); 311 312 return (EINVAL); 313 } 314 315 static int 316 ppc_detect_port(struct ppc_data *ppc) 317 { 318 319 w_ctr(ppc, 0x0c); /* To avoid missing PS2 ports */ 320 w_dtr(ppc, 0xaa); 321 if (r_dtr(ppc) != 0xaa) 322 return (0); 323 324 return (1); 325 } 326 327 /* 328 * ppc_pc873xx_detect 329 * 330 * Probe for a Natsemi PC873xx-family part. 331 * 332 * References in this function are to the National Semiconductor 333 * PC87332 datasheet TL/C/11930, May 1995 revision. 334 */ 335 static int pc873xx_basetab[] = {0x0398, 0x026e, 0x015c, 0x002e, 0}; 336 static int pc873xx_porttab[] = {0x0378, 0x03bc, 0x0278, 0}; 337 static int pc873xx_irqtab[] = {5, 7, 5, 0}; 338 339 static int pc873xx_regstab[] = { 340 PC873_FER, PC873_FAR, PC873_PTR, 341 PC873_FCR, PC873_PCR, PC873_PMC, 342 PC873_TUP, PC873_SID, PC873_PNP0, 343 PC873_PNP1, PC873_LPTBA, -1 344 }; 345 346 static char *pc873xx_rnametab[] = { 347 "FER", "FAR", "PTR", "FCR", "PCR", 348 "PMC", "TUP", "SID", "PNP0", "PNP1", 349 "LPTBA", NULL 350 }; 351 352 static int 353 ppc_pc873xx_detect(struct ppc_data *ppc, int chipset_mode) /* XXX mode never forced */ 354 { 355 static int index = 0; 356 int idport, irq; 357 int ptr, pcr, val, i; 358 359 while ((idport = pc873xx_basetab[index++])) { 360 361 /* XXX should check first to see if this location is already claimed */ 362 363 /* 364 * Pull the 873xx through the power-on ID cycle (2.2,1.). 365 * We can't use this to locate the chip as it may already have 366 * been used by the BIOS. 367 */ 368 (void)inb(idport); (void)inb(idport); 369 (void)inb(idport); (void)inb(idport); 370 371 /* 372 * Read the SID byte. Possible values are : 373 * 374 * 01010xxx PC87334 375 * 0001xxxx PC87332 376 * 01110xxx PC87306 377 */ 378 outb(idport, PC873_SID); 379 val = inb(idport + 1); 380 if ((val & 0xf0) == 0x10) { 381 ppc->ppc_type = NS_PC87332; 382 } else if ((val & 0xf8) == 0x70) { 383 ppc->ppc_type = NS_PC87306; 384 } else if ((val & 0xf8) == 0x50) { 385 ppc->ppc_type = NS_PC87334; 386 } else { 387 if (bootverbose && (val != 0xff)) 388 printf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport, val); 389 continue ; /* not recognised */ 390 } 391 392 /* print registers */ 393 if (bootverbose) { 394 printf("PC873xx"); 395 for (i=0; pc873xx_regstab[i] != -1; i++) { 396 outb(idport, pc873xx_regstab[i]); 397 printf(" %s=0x%x", pc873xx_rnametab[i], 398 inb(idport + 1) & 0xff); 399 } 400 printf("\n"); 401 } 402 403 /* 404 * We think we have one. Is it enabled and where we want it to be? 405 */ 406 outb(idport, PC873_FER); 407 val = inb(idport + 1); 408 if (!(val & PC873_PPENABLE)) { 409 if (bootverbose) 410 printf("PC873xx parallel port disabled\n"); 411 continue; 412 } 413 outb(idport, PC873_FAR); 414 val = inb(idport + 1) & 0x3; 415 /* XXX we should create a driver instance for every port found */ 416 if (pc873xx_porttab[val] != ppc->ppc_base) { 417 if (bootverbose) 418 printf("PC873xx at 0x%x not for driver at port 0x%x\n", 419 pc873xx_porttab[val], ppc->ppc_base); 420 continue; 421 } 422 423 outb(idport, PC873_PTR); 424 ptr = inb(idport + 1); 425 426 /* get irq settings */ 427 if (ppc->ppc_base == 0x378) 428 irq = (ptr & PC873_LPTBIRQ7) ? 7 : 5; 429 else 430 irq = pc873xx_irqtab[val]; 431 432 if (bootverbose) 433 printf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base); 434 435 /* 436 * Check if irq settings are correct 437 */ 438 if (irq != ppc->ppc_irq) { 439 /* 440 * If the chipset is not locked and base address is 0x378, 441 * we have another chance 442 */ 443 if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) { 444 if (ppc->ppc_irq == 7) { 445 outb(idport + 1, (ptr | PC873_LPTBIRQ7)); 446 outb(idport + 1, (ptr | PC873_LPTBIRQ7)); 447 } else { 448 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7)); 449 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7)); 450 } 451 if (bootverbose) 452 printf("PC873xx irq set to %d\n", ppc->ppc_irq); 453 } else { 454 if (bootverbose) 455 printf("PC873xx sorry, can't change irq setting\n"); 456 } 457 } else { 458 if (bootverbose) 459 printf("PC873xx irq settings are correct\n"); 460 } 461 462 outb(idport, PC873_PCR); 463 pcr = inb(idport + 1); 464 465 if ((ptr & PC873_CFGLOCK) || !chipset_mode) { 466 if (bootverbose) 467 printf("PC873xx %s", (ptr & PC873_CFGLOCK)?"locked":"unlocked"); 468 469 ppc->ppc_avm |= PPB_NIBBLE; 470 if (bootverbose) 471 printf(", NIBBLE"); 472 473 if (pcr & PC873_EPPEN) { 474 ppc->ppc_avm |= PPB_EPP; 475 476 if (bootverbose) 477 printf(", EPP"); 478 479 if (pcr & PC873_EPP19) 480 ppc->ppc_epp = EPP_1_9; 481 else 482 ppc->ppc_epp = EPP_1_7; 483 484 if ((ppc->ppc_type == NS_PC87332) && bootverbose) { 485 outb(idport, PC873_PTR); 486 ptr = inb(idport + 1); 487 if (ptr & PC873_EPPRDIR) 488 printf(", Regular mode"); 489 else 490 printf(", Automatic mode"); 491 } 492 } else if (pcr & PC873_ECPEN) { 493 ppc->ppc_avm |= PPB_ECP; 494 if (bootverbose) 495 printf(", ECP"); 496 497 if (pcr & PC873_ECPCLK) { /* XXX */ 498 ppc->ppc_avm |= PPB_PS2; 499 if (bootverbose) 500 printf(", PS/2"); 501 } 502 } else { 503 outb(idport, PC873_PTR); 504 ptr = inb(idport + 1); 505 if (ptr & PC873_EXTENDED) { 506 ppc->ppc_avm |= PPB_SPP; 507 if (bootverbose) 508 printf(", SPP"); 509 } 510 } 511 } else { 512 if (bootverbose) 513 printf("PC873xx unlocked"); 514 515 if (chipset_mode & PPB_ECP) { 516 if ((chipset_mode & PPB_EPP) && bootverbose) 517 printf(", ECP+EPP not supported"); 518 519 pcr &= ~PC873_EPPEN; 520 pcr |= (PC873_ECPEN | PC873_ECPCLK); /* XXX */ 521 outb(idport + 1, pcr); 522 outb(idport + 1, pcr); 523 524 if (bootverbose) 525 printf(", ECP"); 526 527 } else if (chipset_mode & PPB_EPP) { 528 pcr &= ~(PC873_ECPEN | PC873_ECPCLK); 529 pcr |= (PC873_EPPEN | PC873_EPP19); 530 outb(idport + 1, pcr); 531 outb(idport + 1, pcr); 532 533 ppc->ppc_epp = EPP_1_9; /* XXX */ 534 535 if (bootverbose) 536 printf(", EPP1.9"); 537 538 /* enable automatic direction turnover */ 539 if (ppc->ppc_type == NS_PC87332) { 540 outb(idport, PC873_PTR); 541 ptr = inb(idport + 1); 542 ptr &= ~PC873_EPPRDIR; 543 outb(idport + 1, ptr); 544 outb(idport + 1, ptr); 545 546 if (bootverbose) 547 printf(", Automatic mode"); 548 } 549 } else { 550 pcr &= ~(PC873_ECPEN | PC873_ECPCLK | PC873_EPPEN); 551 outb(idport + 1, pcr); 552 outb(idport + 1, pcr); 553 554 /* configure extended bit in PTR */ 555 outb(idport, PC873_PTR); 556 ptr = inb(idport + 1); 557 558 if (chipset_mode & PPB_PS2) { 559 ptr |= PC873_EXTENDED; 560 561 if (bootverbose) 562 printf(", PS/2"); 563 564 } else { 565 /* default to NIBBLE mode */ 566 ptr &= ~PC873_EXTENDED; 567 568 if (bootverbose) 569 printf(", NIBBLE"); 570 } 571 outb(idport + 1, ptr); 572 outb(idport + 1, ptr); 573 } 574 575 ppc->ppc_avm = chipset_mode; 576 } 577 578 if (bootverbose) 579 printf("\n"); 580 581 ppc->ppc_link.adapter = &ppc_generic_adapter; 582 ppc_generic_setmode(ppc->ppc_unit, chipset_mode); 583 584 return(chipset_mode); 585 } 586 return(-1); 587 } 588 589 static int 590 ppc_check_epp_timeout(struct ppc_data *ppc) 591 { 592 ppc_reset_epp_timeout(ppc->ppc_unit); 593 594 return (!(r_str(ppc) & TIMEOUT)); 595 } 596 597 /* 598 * ppc_smc37c66xgt_detect 599 * 600 * SMC FDC37C66xGT configuration. 601 */ 602 static int 603 ppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode) 604 { 605 int s, i; 606 u_char r; 607 int type = -1; 608 int csr = SMC66x_CSR; /* initial value is 0x3F0 */ 609 610 int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 }; 611 612 613 #define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */ 614 615 /* 616 * Detection: enter configuration mode and read CRD register. 617 */ 618 619 s = splhigh(); 620 outb(csr, SMC665_iCODE); 621 outb(csr, SMC665_iCODE); 622 splx(s); 623 624 outb(csr, 0xd); 625 if (inb(cio) == 0x65) { 626 type = SMC_37C665GT; 627 goto config; 628 } 629 630 for (i = 0; i < 2; i++) { 631 s = splhigh(); 632 outb(csr, SMC666_iCODE); 633 outb(csr, SMC666_iCODE); 634 splx(s); 635 636 outb(csr, 0xd); 637 if (inb(cio) == 0x66) { 638 type = SMC_37C666GT; 639 break; 640 } 641 642 /* Another chance, CSR may be hard-configured to be at 0x370 */ 643 csr = SMC666_CSR; 644 } 645 646 config: 647 /* 648 * If chipset not found, do not continue. 649 */ 650 if (type == -1) 651 return (-1); 652 653 /* select CR1 */ 654 outb(csr, 0x1); 655 656 /* read the port's address: bits 0 and 1 of CR1 */ 657 r = inb(cio) & SMC_CR1_ADDR; 658 if (port_address[(int)r] != ppc->ppc_base) 659 return (-1); 660 661 ppc->ppc_type = type; 662 663 /* 664 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration 665 * If SPP mode is detected, try to set ECP+EPP mode 666 */ 667 668 if (bootverbose) { 669 outb(csr, 0x1); 670 printf("ppc%d: SMC registers CR1=0x%x", ppc->ppc_unit, 671 inb(cio) & 0xff); 672 673 outb(csr, 0x4); 674 printf(" CR4=0x%x", inb(cio) & 0xff); 675 } 676 677 /* select CR1 */ 678 outb(csr, 0x1); 679 680 if (!chipset_mode) { 681 /* autodetect mode */ 682 683 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */ 684 if (type == SMC_37C666GT) { 685 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 686 if (bootverbose) 687 printf(" configuration hardwired, supposing " \ 688 "ECP+EPP SPP"); 689 690 } else 691 if ((inb(cio) & SMC_CR1_MODE) == 0) { 692 /* already in extended parallel port mode, read CR4 */ 693 outb(csr, 0x4); 694 r = (inb(cio) & SMC_CR4_EMODE); 695 696 switch (r) { 697 case SMC_SPP: 698 ppc->ppc_avm |= PPB_SPP; 699 if (bootverbose) 700 printf(" SPP"); 701 break; 702 703 case SMC_EPPSPP: 704 ppc->ppc_avm |= PPB_EPP | PPB_SPP; 705 if (bootverbose) 706 printf(" EPP SPP"); 707 break; 708 709 case SMC_ECP: 710 ppc->ppc_avm |= PPB_ECP | PPB_SPP; 711 if (bootverbose) 712 printf(" ECP SPP"); 713 break; 714 715 case SMC_ECPEPP: 716 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 717 if (bootverbose) 718 printf(" ECP+EPP SPP"); 719 break; 720 } 721 } else { 722 /* not an extended port mode */ 723 ppc->ppc_avm |= PPB_SPP; 724 if (bootverbose) 725 printf(" SPP"); 726 } 727 728 } else { 729 /* mode forced */ 730 ppc->ppc_avm = chipset_mode; 731 732 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */ 733 if (type == SMC_37C666GT) 734 goto end_detect; 735 736 r = inb(cio); 737 if ((chipset_mode & (PPB_ECP | PPB_EPP)) == 0) { 738 /* do not use ECP when the mode is not forced to */ 739 outb(cio, r | SMC_CR1_MODE); 740 if (bootverbose) 741 printf(" SPP"); 742 } else { 743 /* an extended mode is selected */ 744 outb(cio, r & ~SMC_CR1_MODE); 745 746 /* read CR4 register and reset mode field */ 747 outb(csr, 0x4); 748 r = inb(cio) & ~SMC_CR4_EMODE; 749 750 if (chipset_mode & PPB_ECP) { 751 if (chipset_mode & PPB_EPP) { 752 outb(cio, r | SMC_ECPEPP); 753 if (bootverbose) 754 printf(" ECP+EPP"); 755 } else { 756 outb(cio, r | SMC_ECP); 757 if (bootverbose) 758 printf(" ECP"); 759 } 760 } else { 761 /* PPB_EPP is set */ 762 outb(cio, r | SMC_EPPSPP); 763 if (bootverbose) 764 printf(" EPP SPP"); 765 } 766 } 767 ppc->ppc_avm = chipset_mode; 768 } 769 770 /* set FIFO threshold to 16 */ 771 if (ppc->ppc_avm & PPB_ECP) { 772 /* select CRA */ 773 outb(csr, 0xa); 774 outb(cio, 16); 775 } 776 777 end_detect: 778 779 if (bootverbose) 780 printf ("\n"); 781 782 if (ppc->ppc_avm & PPB_EPP) { 783 /* select CR4 */ 784 outb(csr, 0x4); 785 r = inb(cio); 786 787 /* 788 * Set the EPP protocol... 789 * Low=EPP 1.9 (1284 standard) and High=EPP 1.7 790 */ 791 if (ppc->ppc_epp == EPP_1_9) 792 outb(cio, (r & ~SMC_CR4_EPPTYPE)); 793 else 794 outb(cio, (r | SMC_CR4_EPPTYPE)); 795 } 796 797 /* end config mode */ 798 outb(csr, 0xaa); 799 800 ppc->ppc_link.adapter = &ppc_smclike_adapter; 801 ppc_smclike_setmode(ppc->ppc_unit, chipset_mode); 802 803 return (chipset_mode); 804 } 805 806 /* 807 * Winbond W83877F stuff 808 * 809 * EFER: extended function enable register 810 * EFIR: extended function index register 811 * EFDR: extended function data register 812 */ 813 #define efir ((efer == 0x250) ? 0x251 : 0x3f0) 814 #define efdr ((efer == 0x250) ? 0x252 : 0x3f1) 815 816 static int w83877f_efers[] = { 0x250, 0x3f0, 0x3f0, 0x250 }; 817 static int w83877f_keys[] = { 0x89, 0x86, 0x87, 0x88 }; 818 static int w83877f_keyiter[] = { 1, 2, 2, 1 }; 819 static int w83877f_hefs[] = { WINB_HEFERE, WINB_HEFRAS, WINB_HEFERE | WINB_HEFRAS, 0 }; 820 821 static int 822 ppc_w83877f_detect(struct ppc_data *ppc, int chipset_mode) 823 { 824 int i, j, efer; 825 unsigned char r, hefere, hefras; 826 827 for (i = 0; i < 4; i ++) { 828 /* first try to enable configuration registers */ 829 efer = w83877f_efers[i]; 830 831 /* write the key to the EFER */ 832 for (j = 0; j < w83877f_keyiter[i]; j ++) 833 outb (efer, w83877f_keys[i]); 834 835 /* then check HEFERE and HEFRAS bits */ 836 outb (efir, 0x0c); 837 hefere = inb(efdr) & WINB_HEFERE; 838 839 outb (efir, 0x16); 840 hefras = inb(efdr) & WINB_HEFRAS; 841 842 /* 843 * HEFRAS HEFERE 844 * 0 1 write 89h to 250h (power-on default) 845 * 1 0 write 86h twice to 3f0h 846 * 1 1 write 87h twice to 3f0h 847 * 0 0 write 88h to 250h 848 */ 849 if ((hefere | hefras) == w83877f_hefs[i]) 850 goto found; 851 } 852 853 return (-1); /* failed */ 854 855 found: 856 /* check base port address - read from CR23 */ 857 outb(efir, 0x23); 858 if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */ 859 return (-1); 860 861 /* read CHIP ID from CR9/bits0-3 */ 862 outb(efir, 0x9); 863 864 switch (inb(efdr) & WINB_CHIPID) { 865 case WINB_W83877F_ID: 866 ppc->ppc_type = WINB_W83877F; 867 break; 868 869 case WINB_W83877AF_ID: 870 ppc->ppc_type = WINB_W83877AF; 871 break; 872 873 default: 874 ppc->ppc_type = WINB_UNKNOWN; 875 } 876 877 if (bootverbose) { 878 /* dump of registers */ 879 printf("ppc%d: 0x%x - ", ppc->ppc_unit, w83877f_keys[i]); 880 for (i = 0; i <= 0xd; i ++) { 881 outb(efir, i); 882 printf("0x%x ", inb(efdr)); 883 } 884 for (i = 0x10; i <= 0x17; i ++) { 885 outb(efir, i); 886 printf("0x%x ", inb(efdr)); 887 } 888 outb(efir, 0x1e); 889 printf("0x%x ", inb(efdr)); 890 for (i = 0x20; i <= 0x29; i ++) { 891 outb(efir, i); 892 printf("0x%x ", inb(efdr)); 893 } 894 printf("\n"); 895 printf("ppc%d:", ppc->ppc_unit); 896 } 897 898 ppc->ppc_link.adapter = &ppc_generic_adapter; 899 900 if (!chipset_mode) { 901 /* autodetect mode */ 902 903 /* select CR0 */ 904 outb(efir, 0x0); 905 r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1); 906 907 /* select CR9 */ 908 outb(efir, 0x9); 909 r |= (inb(efdr) & WINB_PRTMODS2); 910 911 switch (r) { 912 case WINB_W83757: 913 if (bootverbose) 914 printf("ppc%d: W83757 compatible mode\n", 915 ppc->ppc_unit); 916 return (-1); /* generic or SMC-like */ 917 918 case WINB_EXTFDC: 919 case WINB_EXTADP: 920 case WINB_EXT2FDD: 921 case WINB_JOYSTICK: 922 if (bootverbose) 923 printf(" not in parallel port mode\n"); 924 return (-1); 925 926 case (WINB_PARALLEL | WINB_EPP_SPP): 927 ppc->ppc_avm |= PPB_EPP | PPB_SPP; 928 if (bootverbose) 929 printf(" EPP SPP"); 930 break; 931 932 case (WINB_PARALLEL | WINB_ECP): 933 ppc->ppc_avm |= PPB_ECP | PPB_SPP; 934 if (bootverbose) 935 printf(" ECP SPP"); 936 break; 937 938 case (WINB_PARALLEL | WINB_ECP_EPP): 939 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 940 ppc->ppc_link.adapter = &ppc_smclike_adapter; 941 942 if (bootverbose) 943 printf(" ECP+EPP SPP"); 944 break; 945 default: 946 printf("%s: unknown case (0x%x)!\n", __FUNCTION__, r); 947 } 948 949 } else { 950 /* mode forced */ 951 952 /* select CR9 and set PRTMODS2 bit */ 953 outb(efir, 0x9); 954 outb(efdr, inb(efdr) & ~WINB_PRTMODS2); 955 956 /* select CR0 and reset PRTMODSx bits */ 957 outb(efir, 0x0); 958 outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1)); 959 960 if (chipset_mode & PPB_ECP) { 961 if (chipset_mode & PPB_EPP) { 962 outb(efdr, inb(efdr) | WINB_ECP_EPP); 963 if (bootverbose) 964 printf(" ECP+EPP"); 965 966 ppc->ppc_link.adapter = &ppc_smclike_adapter; 967 968 } else { 969 outb(efdr, inb(efdr) | WINB_ECP); 970 if (bootverbose) 971 printf(" ECP"); 972 } 973 } else { 974 /* select EPP_SPP otherwise */ 975 outb(efdr, inb(efdr) | WINB_EPP_SPP); 976 if (bootverbose) 977 printf(" EPP SPP"); 978 } 979 ppc->ppc_avm = chipset_mode; 980 } 981 982 if (bootverbose) 983 printf("\n"); 984 985 /* exit configuration mode */ 986 outb(efer, 0xaa); 987 988 ppc->ppc_link.adapter->setmode(ppc->ppc_unit, chipset_mode); 989 990 return (chipset_mode); 991 } 992 993 /* 994 * ppc_generic_detect 995 */ 996 static int 997 ppc_generic_detect(struct ppc_data *ppc, int chipset_mode) 998 { 999 /* default to generic */ 1000 ppc->ppc_link.adapter = &ppc_generic_adapter; 1001 1002 if (bootverbose) 1003 printf("ppc%d:", ppc->ppc_unit); 1004 1005 if (!chipset_mode) { 1006 /* first, check for ECP */ 1007 w_ecr(ppc, PPC_ECR_PS2); 1008 if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) { 1009 ppc->ppc_avm |= PPB_ECP | PPB_SPP; 1010 if (bootverbose) 1011 printf(" ECP SPP"); 1012 1013 /* search for SMC style ECP+EPP mode */ 1014 w_ecr(ppc, PPC_ECR_EPP); 1015 } 1016 1017 /* try to reset EPP timeout bit */ 1018 if (ppc_check_epp_timeout(ppc)) { 1019 ppc->ppc_avm |= PPB_EPP; 1020 1021 if (ppc->ppc_avm & PPB_ECP) { 1022 /* SMC like chipset found */ 1023 ppc->ppc_type = SMC_LIKE; 1024 ppc->ppc_link.adapter = &ppc_smclike_adapter; 1025 1026 if (bootverbose) 1027 printf(" ECP+EPP"); 1028 } else { 1029 if (bootverbose) 1030 printf(" EPP"); 1031 } 1032 } else { 1033 /* restore to standard mode */ 1034 w_ecr(ppc, PPC_ECR_STD); 1035 } 1036 1037 /* XXX try to detect NIBBLE and PS2 modes */ 1038 ppc->ppc_avm |= PPB_NIBBLE; 1039 1040 if (bootverbose) 1041 printf(" SPP"); 1042 1043 } else { 1044 ppc->ppc_avm = chipset_mode; 1045 } 1046 1047 if (bootverbose) 1048 printf("\n"); 1049 1050 ppc->ppc_link.adapter->setmode(ppc->ppc_unit, chipset_mode); 1051 1052 return (chipset_mode); 1053 } 1054 1055 /* 1056 * ppc_detect() 1057 * 1058 * mode is the mode suggested at boot 1059 */ 1060 static int 1061 ppc_detect(struct ppc_data *ppc, int chipset_mode) { 1062 1063 int i, mode; 1064 1065 /* list of supported chipsets */ 1066 int (*chipset_detect[])(struct ppc_data *, int) = { 1067 ppc_pc873xx_detect, 1068 ppc_smc37c66xgt_detect, 1069 ppc_w83877f_detect, 1070 ppc_generic_detect, 1071 NULL 1072 }; 1073 1074 /* if can't find the port and mode not forced return error */ 1075 if (!ppc_detect_port(ppc) && chipset_mode == 0) 1076 return (EIO); /* failed, port not present */ 1077 1078 /* assume centronics compatible mode is supported */ 1079 ppc->ppc_avm = PPB_COMPATIBLE; 1080 1081 /* we have to differenciate available chipset modes, 1082 * chipset running modes and IEEE-1284 operating modes 1083 * 1084 * after detection, the port must support running in compatible mode 1085 */ 1086 if (ppc->ppc_flags & 0x40) { 1087 if (bootverbose) 1088 printf("ppc: chipset forced to generic\n"); 1089 1090 ppc->ppc_mode = ppc_generic_detect(ppc, chipset_mode); 1091 1092 } else { 1093 for (i=0; chipset_detect[i] != NULL; i++) { 1094 if ((mode = chipset_detect[i](ppc, chipset_mode)) != -1) { 1095 ppc->ppc_mode = mode; 1096 break; 1097 } 1098 } 1099 } 1100 1101 /* configure/detect ECP FIFO */ 1102 if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80)) 1103 ppc_detect_fifo(ppc); 1104 1105 return (0); 1106 } 1107 1108 /* 1109 * ppc_exec_microseq() 1110 * 1111 * Execute a microsequence. 1112 * Microsequence mechanism is supposed to handle fast I/O operations. 1113 */ 1114 static int 1115 ppc_exec_microseq(int unit, struct ppb_microseq **p_msq) 1116 { 1117 struct ppc_data *ppc = ppcdata[unit]; 1118 struct ppb_microseq *mi; 1119 char cc, *p; 1120 int i, iter, len; 1121 int error; 1122 1123 register int reg; 1124 register char mask; 1125 register int accum = 0; 1126 register char *ptr = 0; 1127 1128 struct ppb_microseq *stack = 0; 1129 1130 /* microsequence registers are equivalent to PC-like port registers */ 1131 #define r_reg(register,ppc) (inb((ppc)->ppc_base + register)) 1132 #define w_reg(register,ppc,byte) outb((ppc)->ppc_base + register, byte) 1133 1134 #define INCR_PC (mi ++) /* increment program counter */ 1135 1136 mi = *p_msq; 1137 for (;;) { 1138 switch (mi->opcode) { 1139 case MS_OP_RSET: 1140 cc = r_reg(mi->arg[0].i, ppc); 1141 cc &= (char)mi->arg[2].i; /* clear mask */ 1142 cc |= (char)mi->arg[1].i; /* assert mask */ 1143 w_reg(mi->arg[0].i, ppc, cc); 1144 INCR_PC; 1145 break; 1146 1147 case MS_OP_RASSERT_P: 1148 reg = mi->arg[1].i; 1149 ptr = ppc->ppc_ptr; 1150 1151 if ((len = mi->arg[0].i) == MS_ACCUM) { 1152 accum = ppc->ppc_accum; 1153 for (; accum; accum--) 1154 w_reg(reg, ppc, *ptr++); 1155 ppc->ppc_accum = accum; 1156 } else 1157 for (i=0; i<len; i++) 1158 w_reg(reg, ppc, *ptr++); 1159 ppc->ppc_ptr = ptr; 1160 1161 INCR_PC; 1162 break; 1163 1164 case MS_OP_RFETCH_P: 1165 reg = mi->arg[1].i; 1166 mask = (char)mi->arg[2].i; 1167 ptr = ppc->ppc_ptr; 1168 1169 if ((len = mi->arg[0].i) == MS_ACCUM) { 1170 accum = ppc->ppc_accum; 1171 for (; accum; accum--) 1172 *ptr++ = r_reg(reg, ppc) & mask; 1173 ppc->ppc_accum = accum; 1174 } else 1175 for (i=0; i<len; i++) 1176 *ptr++ = r_reg(reg, ppc) & mask; 1177 ppc->ppc_ptr = ptr; 1178 1179 INCR_PC; 1180 break; 1181 1182 case MS_OP_RFETCH: 1183 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) & 1184 (char)mi->arg[1].i; 1185 INCR_PC; 1186 break; 1187 1188 case MS_OP_RASSERT: 1189 case MS_OP_DELAY: 1190 1191 /* let's suppose the next instr. is the same */ 1192 prefetch: 1193 for (;mi->opcode == MS_OP_RASSERT; INCR_PC) 1194 w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i); 1195 1196 if (mi->opcode == MS_OP_DELAY) { 1197 DELAY(mi->arg[0].i); 1198 INCR_PC; 1199 goto prefetch; 1200 } 1201 break; 1202 1203 case MS_OP_ADELAY: 1204 if (mi->arg[0].i) 1205 tsleep(NULL, PPBPRI, "ppbdelay", 1206 mi->arg[0].i * (hz/1000)); 1207 INCR_PC; 1208 break; 1209 1210 case MS_OP_TRIG: 1211 reg = mi->arg[0].i; 1212 iter = mi->arg[1].i; 1213 p = (char *)mi->arg[2].p; 1214 1215 /* XXX delay limited to 255 us */ 1216 for (i=0; i<iter; i++) { 1217 w_reg(reg, ppc, *p++); 1218 DELAY((unsigned char)*p++); 1219 } 1220 INCR_PC; 1221 break; 1222 1223 case MS_OP_SET: 1224 ppc->ppc_accum = mi->arg[0].i; 1225 INCR_PC; 1226 break; 1227 1228 case MS_OP_DBRA: 1229 if (--ppc->ppc_accum > 0) 1230 mi += mi->arg[0].i; 1231 else 1232 INCR_PC; 1233 break; 1234 1235 case MS_OP_BRSET: 1236 cc = r_str(ppc); 1237 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i) 1238 mi += mi->arg[1].i; 1239 else 1240 INCR_PC; 1241 break; 1242 1243 case MS_OP_BRCLEAR: 1244 cc = r_str(ppc); 1245 if ((cc & (char)mi->arg[0].i) == 0) 1246 mi += mi->arg[1].i; 1247 else 1248 INCR_PC; 1249 break; 1250 1251 case MS_OP_BRSTAT: 1252 cc = r_str(ppc); 1253 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) == 1254 (char)mi->arg[0].i) 1255 mi += mi->arg[2].i; 1256 else 1257 INCR_PC; 1258 break; 1259 1260 case MS_OP_C_CALL: 1261 /* 1262 * If the C call returns !0 then end the microseq. 1263 * The current state of ptr is passed to the C function 1264 */ 1265 if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr))) 1266 return (error); 1267 1268 INCR_PC; 1269 break; 1270 1271 case MS_OP_PTR: 1272 ppc->ppc_ptr = (char *)mi->arg[0].p; 1273 INCR_PC; 1274 break; 1275 1276 case MS_OP_CALL: 1277 if (stack) 1278 panic("%s: too much calls", __FUNCTION__); 1279 1280 if (mi->arg[0].p) { 1281 /* store the state of the actual 1282 * microsequence 1283 */ 1284 stack = mi; 1285 1286 /* jump to the new microsequence */ 1287 mi = (struct ppb_microseq *)mi->arg[0].p; 1288 } else 1289 INCR_PC; 1290 1291 break; 1292 1293 case MS_OP_SUBRET: 1294 /* retrieve microseq and pc state before the call */ 1295 mi = stack; 1296 1297 /* reset the stack */ 1298 stack = 0; 1299 1300 /* XXX return code */ 1301 1302 INCR_PC; 1303 break; 1304 1305 case MS_OP_PUT: 1306 case MS_OP_GET: 1307 case MS_OP_RET: 1308 /* can't return to ppb level during the execution 1309 * of a submicrosequence */ 1310 if (stack) 1311 panic("%s: can't return to ppb level", 1312 __FUNCTION__); 1313 1314 /* update pc for ppb level of execution */ 1315 *p_msq = mi; 1316 1317 /* return to ppb level of execution */ 1318 return (0); 1319 1320 default: 1321 panic("%s: unknown microsequence opcode 0x%x", 1322 __FUNCTION__, mi->opcode); 1323 } 1324 } 1325 1326 /* unreached */ 1327 } 1328 1329 static void 1330 ppcintr(int unit) 1331 { 1332 struct ppc_data *ppc = ppcdata[unit]; 1333 u_char str, ctr, ecr; 1334 1335 str = r_str(ppc); 1336 ctr = r_ctr(ppc); 1337 ecr = r_ecr(ppc); 1338 1339 #if PPC_DEBUG > 1 1340 printf("![%x/%x/%x]", ctr, ecr, str); 1341 #endif 1342 1343 /* don't use ecp mode with IRQENABLE set */ 1344 if (ctr & IRQENABLE) { 1345 /* call upper code */ 1346 ppb_intr(&ppc->ppc_link); 1347 return; 1348 } 1349 1350 /* interrupts are generated by nFault signal 1351 * only in ECP mode */ 1352 if ((str & nFAULT) && (ppc->ppc_mode & PPB_ECP)) { 1353 /* check if ppc driver has programmed the 1354 * nFault interrupt */ 1355 if (ppc->ppc_irqstat & PPC_IRQ_nFAULT) { 1356 1357 w_ecr(ppc, ecr | PPC_nFAULT_INTR); 1358 ppc->ppc_irqstat &= ~PPC_IRQ_nFAULT; 1359 } else { 1360 /* call upper code */ 1361 ppb_intr(&ppc->ppc_link); 1362 return; 1363 } 1364 } 1365 1366 if (ppc->ppc_irqstat & PPC_IRQ_DMA) { 1367 /* disable interrupts (should be done by hardware though) */ 1368 w_ecr(ppc, ecr | PPC_SERVICE_INTR); 1369 ppc->ppc_irqstat &= ~PPC_IRQ_DMA; 1370 ecr = r_ecr(ppc); 1371 1372 /* check if DMA completed */ 1373 if ((ppc->ppc_avm & PPB_ECP) && (ecr & PPC_ENABLE_DMA)) { 1374 #ifdef PPC_DEBUG 1375 printf("a"); 1376 #endif 1377 /* stop DMA */ 1378 w_ecr(ppc, ecr & ~PPC_ENABLE_DMA); 1379 ecr = r_ecr(ppc); 1380 1381 if (ppc->ppc_dmastat == PPC_DMA_STARTED) { 1382 #ifdef PPC_DEBUG 1383 printf("d"); 1384 #endif 1385 isa_dmadone( 1386 ppc->ppc_dmaflags, 1387 ppc->ppc_dmaddr, 1388 ppc->ppc_dmacnt, 1389 ppc->ppc_dmachan); 1390 1391 ppc->ppc_dmastat = PPC_DMA_COMPLETE; 1392 1393 /* wakeup the waiting process */ 1394 wakeup((caddr_t)ppc); 1395 } 1396 } 1397 } else if (ppc->ppc_irqstat & PPC_IRQ_FIFO) { 1398 1399 /* classic interrupt I/O */ 1400 ppc->ppc_irqstat &= ~PPC_IRQ_FIFO; 1401 1402 } 1403 1404 return; 1405 } 1406 1407 static int 1408 ppc_read(int unit, char *buf, int len, int mode) 1409 { 1410 return (EINVAL); 1411 } 1412 1413 /* 1414 * Call this function if you want to send data in any advanced mode 1415 * of your parallel port: FIFO, DMA 1416 * 1417 * If what you want is not possible (no ECP, no DMA...), 1418 * EINVAL is returned 1419 */ 1420 static int 1421 ppc_write(int unit, char *buf, int len, int how) 1422 { 1423 struct ppc_data *ppc = ppcdata[unit]; 1424 char ecr, ecr_sav, ctr, ctr_sav; 1425 int s, error = 0; 1426 int spin; 1427 1428 #ifdef PPC_DEBUG 1429 printf("w"); 1430 #endif 1431 1432 ecr_sav = r_ecr(ppc); 1433 ctr_sav = r_ctr(ppc); 1434 1435 /* 1436 * Send buffer with DMA, FIFO and interrupts 1437 */ 1438 if (ppc->ppc_avm & PPB_ECP) { 1439 1440 if (ppc->ppc_dmachan >= 0) { 1441 1442 /* byte mode, no intr, no DMA, dir=0, flush fifo 1443 */ 1444 ecr = PPC_ECR_STD | PPC_DISABLE_INTR; 1445 w_ecr(ppc, ecr); 1446 1447 /* disable nAck interrupts */ 1448 ctr = r_ctr(ppc); 1449 ctr &= ~IRQENABLE; 1450 w_ctr(ppc, ctr); 1451 1452 ppc->ppc_dmaflags = 0; 1453 ppc->ppc_dmaddr = (caddr_t)buf; 1454 ppc->ppc_dmacnt = (u_int)len; 1455 1456 switch (ppc->ppc_mode) { 1457 case PPB_COMPATIBLE: 1458 /* compatible mode with FIFO, no intr, DMA, dir=0 */ 1459 ecr = PPC_ECR_FIFO | PPC_DISABLE_INTR | PPC_ENABLE_DMA; 1460 break; 1461 case PPB_ECP: 1462 ecr = PPC_ECR_ECP | PPC_DISABLE_INTR | PPC_ENABLE_DMA; 1463 break; 1464 default: 1465 error = EINVAL; 1466 goto error; 1467 } 1468 1469 w_ecr(ppc, ecr); 1470 ecr = r_ecr(ppc); 1471 1472 /* enter splhigh() not to be preempted 1473 * by the dma interrupt, we may miss 1474 * the wakeup otherwise 1475 */ 1476 s = splhigh(); 1477 1478 ppc->ppc_dmastat = PPC_DMA_INIT; 1479 1480 /* enable interrupts */ 1481 ecr &= ~PPC_SERVICE_INTR; 1482 ppc->ppc_irqstat = PPC_IRQ_DMA; 1483 w_ecr(ppc, ecr); 1484 1485 isa_dmastart( 1486 ppc->ppc_dmaflags, 1487 ppc->ppc_dmaddr, 1488 ppc->ppc_dmacnt, 1489 ppc->ppc_dmachan); 1490 #ifdef PPC_DEBUG 1491 printf("s%d", ppc->ppc_dmacnt); 1492 #endif 1493 ppc->ppc_dmastat = PPC_DMA_STARTED; 1494 1495 /* Wait for the DMA completed interrupt. We hope we won't 1496 * miss it, otherwise a signal will be necessary to unlock the 1497 * process. 1498 */ 1499 do { 1500 /* release CPU */ 1501 error = tsleep((caddr_t)ppc, 1502 PPBPRI | PCATCH, "ppcdma", 0); 1503 1504 } while (error == EWOULDBLOCK); 1505 1506 splx(s); 1507 1508 if (error) { 1509 #ifdef PPC_DEBUG 1510 printf("i"); 1511 #endif 1512 /* stop DMA */ 1513 isa_dmadone( 1514 ppc->ppc_dmaflags, ppc->ppc_dmaddr, 1515 ppc->ppc_dmacnt, ppc->ppc_dmachan); 1516 1517 /* no dma, no interrupt, flush the fifo */ 1518 w_ecr(ppc, PPC_ECR_RESET); 1519 1520 ppc->ppc_dmastat = PPC_DMA_INTERRUPTED; 1521 goto error; 1522 } 1523 1524 /* wait for an empty fifo */ 1525 while (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) { 1526 1527 for (spin=100; spin; spin--) 1528 if (r_ecr(ppc) & PPC_FIFO_EMPTY) 1529 goto fifo_empty; 1530 #ifdef PPC_DEBUG 1531 printf("Z"); 1532 #endif 1533 error = tsleep((caddr_t)ppc, PPBPRI | PCATCH, "ppcfifo", hz/100); 1534 if (error != EWOULDBLOCK) { 1535 #ifdef PPC_DEBUG 1536 printf("I"); 1537 #endif 1538 /* no dma, no interrupt, flush the fifo */ 1539 w_ecr(ppc, PPC_ECR_RESET); 1540 1541 ppc->ppc_dmastat = PPC_DMA_INTERRUPTED; 1542 error = EINTR; 1543 goto error; 1544 } 1545 } 1546 1547 fifo_empty: 1548 /* no dma, no interrupt, flush the fifo */ 1549 w_ecr(ppc, PPC_ECR_RESET); 1550 1551 } else 1552 error = EINVAL; /* XXX we should FIFO and 1553 * interrupts */ 1554 } else 1555 error = EINVAL; 1556 1557 error: 1558 1559 /* PDRQ must be kept unasserted until nPDACK is 1560 * deasserted for a minimum of 350ns (SMC datasheet) 1561 * 1562 * Consequence may be a FIFO that never empty 1563 */ 1564 DELAY(1); 1565 1566 w_ecr(ppc, ecr_sav); 1567 w_ctr(ppc, ctr_sav); 1568 1569 return (error); 1570 } 1571 1572 /* 1573 * Configure current operating mode 1574 */ 1575 static int 1576 ppc_generic_setmode(int unit, int mode) 1577 { 1578 struct ppc_data *ppc = ppcdata[unit]; 1579 u_char ecr = 0; 1580 1581 /* check if mode is available */ 1582 if (mode && !(ppc->ppc_avm & mode)) 1583 return (EINVAL); 1584 1585 /* if ECP mode, configure ecr register */ 1586 if (ppc->ppc_avm & PPB_ECP) { 1587 /* return to byte mode (keeping direction bit), 1588 * no interrupt, no DMA to be able to change to 1589 * ECP 1590 */ 1591 w_ecr(ppc, PPC_ECR_RESET); 1592 ecr = PPC_DISABLE_INTR; 1593 1594 if (mode & PPB_EPP) 1595 return (EINVAL); 1596 else if (mode & PPB_ECP) 1597 /* select ECP mode */ 1598 ecr |= PPC_ECR_ECP; 1599 else if (mode & PPB_PS2) 1600 /* select PS2 mode with ECP */ 1601 ecr |= PPC_ECR_PS2; 1602 else 1603 /* select COMPATIBLE/NIBBLE mode */ 1604 ecr |= PPC_ECR_STD; 1605 1606 w_ecr(ppc, ecr); 1607 } 1608 1609 ppc->ppc_mode = mode; 1610 1611 return (0); 1612 } 1613 1614 /* 1615 * The ppc driver is free to choose options like FIFO or DMA 1616 * if ECP mode is available. 1617 * 1618 * The 'RAW' option allows the upper drivers to force the ppc mode 1619 * even with FIFO, DMA available. 1620 */ 1621 int 1622 ppc_smclike_setmode(int unit, int mode) 1623 { 1624 struct ppc_data *ppc = ppcdata[unit]; 1625 u_char ecr = 0; 1626 1627 /* check if mode is available */ 1628 if (mode && !(ppc->ppc_avm & mode)) 1629 return (EINVAL); 1630 1631 /* if ECP mode, configure ecr register */ 1632 if (ppc->ppc_avm & PPB_ECP) { 1633 /* return to byte mode (keeping direction bit), 1634 * no interrupt, no DMA to be able to change to 1635 * ECP or EPP mode 1636 */ 1637 w_ecr(ppc, PPC_ECR_RESET); 1638 ecr = PPC_DISABLE_INTR; 1639 1640 if (mode & PPB_EPP) 1641 /* select EPP mode */ 1642 ecr |= PPC_ECR_EPP; 1643 else if (mode & PPB_ECP) 1644 /* select ECP mode */ 1645 ecr |= PPC_ECR_ECP; 1646 else if (mode & PPB_PS2) 1647 /* select PS2 mode with ECP */ 1648 ecr |= PPC_ECR_PS2; 1649 else 1650 /* select COMPATIBLE/NIBBLE mode */ 1651 ecr |= PPC_ECR_STD; 1652 1653 w_ecr(ppc, ecr); 1654 } 1655 1656 ppc->ppc_mode = mode; 1657 1658 return (0); 1659 } 1660 1661 /* 1662 * EPP timeout, according to the PC87332 manual 1663 * Semantics of clearing EPP timeout bit. 1664 * PC87332 - reading SPP_STR does it... 1665 * SMC - write 1 to EPP timeout bit XXX 1666 * Others - (?) write 0 to EPP timeout bit 1667 */ 1668 static void 1669 ppc_reset_epp_timeout(int unit) 1670 { 1671 struct ppc_data *ppc = ppcdata[unit]; 1672 register char r; 1673 1674 r = r_str(ppc); 1675 w_str(ppc, r | 0x1); 1676 w_str(ppc, r & 0xfe); 1677 1678 return; 1679 } 1680 1681 static int 1682 ppcprobe(struct isa_device *dvp) 1683 { 1684 static short next_bios_ppc = 0; 1685 struct ppc_data *ppc; 1686 1687 /* 1688 * If port not specified, use bios list. 1689 */ 1690 if(dvp->id_iobase < 0) { 1691 if((next_bios_ppc < BIOS_MAX_PPC) && 1692 (*(BIOS_PORTS+next_bios_ppc) != 0) ) { 1693 dvp->id_iobase = *(BIOS_PORTS+next_bios_ppc++); 1694 if (bootverbose) 1695 printf("ppc: parallel port found at 0x%x\n", 1696 dvp->id_iobase); 1697 } else 1698 return (0); 1699 } 1700 1701 /* 1702 * Port was explicitly specified. 1703 * This allows probing of ports unknown to the BIOS. 1704 */ 1705 1706 /* 1707 * Allocate the ppc_data structure. 1708 */ 1709 ppc = malloc(sizeof(struct ppc_data), M_DEVBUF, M_NOWAIT); 1710 if (!ppc) { 1711 printf("ppc: cannot malloc!\n"); 1712 goto error; 1713 } 1714 bzero(ppc, sizeof(struct ppc_data)); 1715 1716 ppc->ppc_base = dvp->id_iobase; 1717 ppc->ppc_unit = dvp->id_unit; 1718 ppc->ppc_type = GENERIC; 1719 1720 /* store boot flags */ 1721 ppc->ppc_flags = dvp->id_flags; 1722 1723 ppc->ppc_mode = PPB_COMPATIBLE; 1724 ppc->ppc_epp = (dvp->id_flags & 0x10) >> 4; 1725 1726 /* 1727 * XXX Try and detect if interrupts are working 1728 */ 1729 if (!(dvp->id_flags & 0x20) && dvp->id_irq) 1730 ppc->ppc_irq = ffs(dvp->id_irq) - 1; 1731 1732 ppc->ppc_dmachan = dvp->id_drq; 1733 1734 ppcdata[ppc->ppc_unit] = ppc; 1735 nppc ++; 1736 1737 /* 1738 * Link the Parallel Port Chipset (adapter) to 1739 * the future ppbus. Default to a generic chipset 1740 */ 1741 ppc->ppc_link.adapter_unit = ppc->ppc_unit; 1742 ppc->ppc_link.adapter = &ppc_generic_adapter; 1743 1744 /* 1745 * Try to detect the chipset and its mode. 1746 */ 1747 if (ppc_detect(ppc, dvp->id_flags & 0xf)) 1748 goto error; 1749 1750 return (1); 1751 1752 error: 1753 return (0); 1754 } 1755 1756 static int 1757 ppcattach(struct isa_device *isdp) 1758 { 1759 struct ppc_data *ppc = ppcdata[isdp->id_unit]; 1760 struct ppb_data *ppbus; 1761 1762 printf("ppc%d: %s chipset (%s) in %s mode%s\n", ppc->ppc_unit, 1763 ppc_types[ppc->ppc_type], ppc_avms[ppc->ppc_avm], 1764 ppc_modes[ppc->ppc_mode], (PPB_IS_EPP(ppc->ppc_mode)) ? 1765 ppc_epp_protocol[ppc->ppc_epp] : ""); 1766 1767 if (ppc->ppc_fifo) 1768 printf("ppc%d: FIFO with %d/%d/%d bytes threshold\n", 1769 ppc->ppc_unit, ppc->ppc_fifo, ppc->ppc_wthr, 1770 ppc->ppc_rthr); 1771 1772 isdp->id_ointr = ppcintr; 1773 1774 /* 1775 * Prepare ppbus data area for upper level code. 1776 */ 1777 ppbus = ppb_alloc_bus(); 1778 1779 if (!ppbus) 1780 return (0); 1781 1782 ppc->ppc_link.ppbus = ppbus; 1783 ppbus->ppb_link = &ppc->ppc_link; 1784 1785 if ((ppc->ppc_avm & PPB_ECP) && (ppc->ppc_dmachan > 0)) { 1786 1787 /* acquire the DMA channel forever */ 1788 isa_dma_acquire(ppc->ppc_dmachan); 1789 isa_dmainit(ppc->ppc_dmachan, 1024); /* nlpt.BUFSIZE */ 1790 } 1791 1792 /* 1793 * Probe the ppbus and attach devices found. 1794 */ 1795 ppb_attachdevs(ppbus); 1796 1797 return (1); 1798 } 1799 #endif
Cache object: edf0e206b0b31112fd745014dfe3a2ba
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