2 * Copyright (c) 1993 The Regents of the University of California.
3 * All rights reserved.
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12 * documentation and/or other materials provided with the distribution.
13 * 4. Neither the name of the University nor the names of its contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
29 * from: Header: timerreg.h,v 1.2 93/02/28 15:08:58 mccanne Exp
30 * $FreeBSD: releng/5.4/sys/i386/isa/timerreg.h 128019 2004-04-07 20:46:16Z imp $
35 * Register definitions for the Intel 8253 Programmable Interval Timer.
37 * This chip has three independent 16-bit down counters that can be
38 * read on the fly. There are three mode registers and three countdown
39 * registers. The countdown registers are addressed directly, via the
40 * first three I/O ports. The three mode registers are accessed via
41 * the fourth I/O port, with two bits in the mode byte indicating the
42 * register. (Why are hardware interfaces always so braindead?).
44 * To write a value into the countdown register, the mode register
45 * is first programmed with a command indicating the which byte of
46 * the two byte register is to be modified. The three possibilities
47 * are load msb (TMR_MR_MSB), load lsb (TMR_MR_LSB), or load lsb then
48 * msb (TMR_MR_BOTH).
50 * To read the current value ("on the fly") from the countdown register,
51 * you write a "latch" command into the mode register, then read the stable
52 * value from the corresponding I/O port. For example, you write
53 * TMR_MR_LATCH into the corresponding mode register. Presumably,
54 * after doing this, a write operation to the I/O port would result
55 * in undefined behavior (but hopefully not fry the chip).
56 * Reading in this manner has no side effects.
58 * [IBM-PC]
59 * The outputs of the three timers are connected as follows:
61 * timer 0 -> irq 0
62 * timer 1 -> dma chan 0 (for dram refresh)
63 * timer 2 -> speaker (via keyboard controller)
65 * Timer 0 is used to call hardclock.
66 * Timer 2 is used to generate console beeps.
68 * [PC-9801]
69 * The outputs of the three timers are connected as follows:
71 * timer 0 -> irq 0
72 * timer 1 -> speaker (via keyboard controller)
73 * timer 2 -> RS232C
75 * Timer 0 is used to call hardclock.
76 * Timer 1 is used to generate console beeps.
80 * Macros for specifying values to be written into a mode register.
82 #define TIMER_CNTR0 (IO_TIMER1 + 0) /* timer 0 counter port */
83 #ifdef PC98
84 #define TIMER_CNTR1 0x3fdb /* timer 1 counter port */
85 #define TIMER_CNTR2 (IO_TIMER1 + 4) /* timer 2 counter port */
86 #define TIMER_MODE (IO_TIMER1 + 6) /* timer mode port */
88 #define TIMER_CNTR1 (IO_TIMER1 + 1) /* timer 1 counter port */
89 #define TIMER_CNTR2 (IO_TIMER1 + 2) /* timer 2 counter port */
90 #define TIMER_MODE (IO_TIMER1 + 3) /* timer mode port */
92 #define TIMER_SEL0 0x00 /* select counter 0 */
93 #define TIMER_SEL1 0x40 /* select counter 1 */
94 #define TIMER_SEL2 0x80 /* select counter 2 */
95 #define TIMER_INTTC 0x00 /* mode 0, intr on terminal cnt */
96 #define TIMER_ONESHOT 0x02 /* mode 1, one shot */
97 #define TIMER_RATEGEN 0x04 /* mode 2, rate generator */
98 #define TIMER_SQWAVE 0x06 /* mode 3, square wave */
99 #define TIMER_SWSTROBE 0x08 /* mode 4, s/w triggered strobe */
100 #define TIMER_HWSTROBE 0x0a /* mode 5, h/w triggered strobe */
101 #define TIMER_LATCH 0x00 /* latch counter for reading */
102 #define TIMER_LSB 0x10 /* r/w counter LSB */
103 #define TIMER_MSB 0x20 /* r/w counter MSB */
104 #define TIMER_16BIT 0x30 /* r/w counter 16 bits, LSB first */
105 #define TIMER_BCD 0x01 /* count in BCD */
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