pci_bus.c

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    1 /*
    2  * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice unmodified, this list of conditions, and the following
   10  *    disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  *
   15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   25  *
   26  * $FreeBSD: releng/5.1/sys/i386/pci/pci_bus.c 111068 2003-02-18 03:36:49Z peter $
   27  *
   28  */
   29 
   30 #include "opt_cpu.h"
   31 
   32 #include <sys/param.h>
   33 #include <sys/systm.h>
   34 #include <sys/bus.h>
   35 #include <sys/kernel.h>
   36 #include <sys/module.h>
   37 #include <sys/malloc.h>
   38 
   39 #include <pci/pcivar.h>
   40 #include <pci/pcireg.h>
   41 #include <pci/pcib_private.h>
   42 #include <isa/isavar.h>
   43 #include <machine/legacyvar.h>
   44 #include <machine/pci_cfgreg.h>
   45 #include <machine/segments.h>
   46 #include <machine/cputypes.h>
   47 #include <machine/pc/bios.h>
   48 #include <machine/md_var.h>
   49 
   50 #include "pcib_if.h"
   51 
   52 static int      pcibios_pcib_route_interrupt(device_t pcib, device_t dev,
   53     int pin);
   54 
   55 static int
   56 nexus_pcib_maxslots(device_t dev)
   57 {
   58         return 31;
   59 }
   60 
   61 /* read configuration space register */
   62 
   63 static u_int32_t
   64 nexus_pcib_read_config(device_t dev, int bus, int slot, int func,
   65                        int reg, int bytes)
   66 {
   67         return(pci_cfgregread(bus, slot, func, reg, bytes));
   68 }
   69 
   70 /* write configuration space register */
   71 
   72 static void
   73 nexus_pcib_write_config(device_t dev, int bus, int slot, int func,
   74                         int reg, u_int32_t data, int bytes)
   75 {
   76         pci_cfgregwrite(bus, slot, func, reg, data, bytes);
   77 }
   78 
   79 /* route interrupt */
   80 
   81 static int
   82 nexus_pcib_route_interrupt(device_t pcib, device_t dev, int pin)
   83 {
   84         return (pcibios_pcib_route_interrupt(pcib, dev, pin));
   85 }
   86 
   87 static const char *
   88 nexus_pcib_is_host_bridge(int bus, int slot, int func,
   89                           u_int32_t id, u_int8_t class, u_int8_t subclass,
   90                           u_int8_t *busnum)
   91 {
   92         const char *s = NULL;
   93         static u_int8_t pxb[4]; /* hack for 450nx */
   94 
   95         *busnum = 0;
   96 
   97         switch (id) {
   98         case 0x12258086:
   99                 s = "Intel 824?? host to PCI bridge";
  100                 /* XXX This is a guess */
  101                 /* *busnum = nexus_pcib_read_config(0, bus, slot, func, 0x41, 1); */
  102                 *busnum = bus;
  103                 break;
  104         case 0x71208086:
  105                 s = "Intel 82810 (i810 GMCH) Host To Hub bridge";
  106                 break;
  107         case 0x71228086:
  108                 s = "Intel 82810-DC100 (i810-DC100 GMCH) Host To Hub bridge";
  109                 break;
  110         case 0x71248086:
  111                 s = "Intel 82810E (i810E GMCH) Host To Hub bridge";
  112                 break;
  113         case 0x11308086:
  114                 s = "Intel 82815 (i815 GMCH) Host To Hub bridge";
  115                 break;
  116         case 0x71808086:
  117                 s = "Intel 82443LX (440 LX) host to PCI bridge";
  118                 break;
  119         case 0x71908086:
  120                 s = "Intel 82443BX (440 BX) host to PCI bridge";
  121                 break;
  122         case 0x71928086:
  123                 s = "Intel 82443BX host to PCI bridge (AGP disabled)";
  124                 break;
  125         case 0x71948086:
  126                 s = "Intel 82443MX host to PCI bridge";
  127                 break;
  128         case 0x71a08086:
  129                 s = "Intel 82443GX host to PCI bridge";
  130                 break;
  131         case 0x71a18086:
  132                 s = "Intel 82443GX host to AGP bridge";
  133                 break;
  134         case 0x71a28086:
  135                 s = "Intel 82443GX host to PCI bridge (AGP disabled)";
  136                 break;
  137         case 0x84c48086:
  138                 s = "Intel 82454KX/GX (Orion) host to PCI bridge";
  139                 *busnum = nexus_pcib_read_config(0, bus, slot, func, 0x4a, 1);
  140                 break;
  141         case 0x84ca8086:
  142                 /*
  143                  * For the 450nx chipset, there is a whole bundle of
  144                  * things pretending to be host bridges. The MIOC will 
  145                  * be seen first and isn't really a pci bridge (the
  146                  * actual busses are attached to the PXB's). We need to 
  147                  * read the registers of the MIOC to figure out the
  148                  * bus numbers for the PXB channels.
  149                  *
  150                  * Since the MIOC doesn't have a pci bus attached, we
  151                  * pretend it wasn't there.
  152                  */
  153                 pxb[0] = nexus_pcib_read_config(0, bus, slot, func,
  154                                                 0xd0, 1); /* BUSNO[0] */
  155                 pxb[1] = nexus_pcib_read_config(0, bus, slot, func,
  156                                                 0xd1, 1) + 1;   /* SUBA[0]+1 */
  157                 pxb[2] = nexus_pcib_read_config(0, bus, slot, func,
  158                                                 0xd3, 1); /* BUSNO[1] */
  159                 pxb[3] = nexus_pcib_read_config(0, bus, slot, func,
  160                                                 0xd4, 1) + 1;   /* SUBA[1]+1 */
  161                 return NULL;
  162         case 0x84cb8086:
  163                 switch (slot) {
  164                 case 0x12:
  165                         s = "Intel 82454NX PXB#0, Bus#A";
  166                         *busnum = pxb[0];
  167                         break;
  168                 case 0x13:
  169                         s = "Intel 82454NX PXB#0, Bus#B";
  170                         *busnum = pxb[1];
  171                         break;
  172                 case 0x14:
  173                         s = "Intel 82454NX PXB#1, Bus#A";
  174                         *busnum = pxb[2];
  175                         break;
  176                 case 0x15:
  177                         s = "Intel 82454NX PXB#1, Bus#B";
  178                         *busnum = pxb[3];
  179                         break;
  180                 }
  181                 break;
  182 
  183                 /* AMD -- vendor 0x1022 */
  184         case 0x30001022:
  185                 s = "AMD Elan SC520 host to PCI bridge";
  186 #ifdef CPU_ELAN
  187                 init_AMD_Elan_sc520();
  188 #else
  189                 printf(
  190 "*** WARNING: missing CPU_ELAN -- timekeeping may be wrong\n");
  191 #endif
  192                 break;
  193         case 0x70061022:
  194                 s = "AMD-751 host to PCI bridge";
  195                 break;
  196         case 0x700e1022:
  197                 s = "AMD-761 host to PCI bridge";
  198                 break;
  199 
  200                 /* SiS -- vendor 0x1039 */
  201         case 0x04961039:
  202                 s = "SiS 85c496";
  203                 break;
  204         case 0x04061039:
  205                 s = "SiS 85c501";
  206                 break;
  207         case 0x06011039:
  208                 s = "SiS 85c601";
  209                 break;
  210         case 0x55911039:
  211                 s = "SiS 5591 host to PCI bridge";
  212                 break;
  213         case 0x00011039:
  214                 s = "SiS 5591 host to AGP bridge";
  215                 break;
  216 
  217                 /* VLSI -- vendor 0x1004 */
  218         case 0x00051004:
  219                 s = "VLSI 82C592 Host to PCI bridge";
  220                 break;
  221 
  222                 /* XXX Here is MVP3, I got the datasheet but NO M/B to test it  */
  223                 /* totally. Please let me know if anything wrong.            -F */
  224                 /* XXX need info on the MVP3 -- any takers? */
  225         case 0x05981106:
  226                 s = "VIA 82C598MVP (Apollo MVP3) host bridge";
  227                 break;
  228 
  229                 /* AcerLabs -- vendor 0x10b9 */
  230                 /* Funny : The datasheet told me vendor id is "10b8",sub-vendor */
  231                 /* id is '10b9" but the register always shows "10b9". -Foxfair  */
  232         case 0x154110b9:
  233                 s = "AcerLabs M1541 (Aladdin-V) PCI host bridge";
  234                 break;
  235 
  236                 /* OPTi -- vendor 0x1045 */
  237         case 0xc7011045:
  238                 s = "OPTi 82C700 host to PCI bridge";
  239                 break;
  240         case 0xc8221045:
  241                 s = "OPTi 82C822 host to PCI Bridge";
  242                 break;
  243 
  244                 /* ServerWorks -- vendor 0x1166 */
  245         case 0x00051166:
  246                 s = "ServerWorks NB6536 2.0HE host to PCI bridge";
  247                 *busnum = nexus_pcib_read_config(0, bus, slot, func, 0x44, 1);
  248                 break;
  249         
  250         case 0x00061166:
  251                 /* FALLTHROUGH */
  252         case 0x00081166:
  253                 /* FALLTHROUGH */
  254         case 0x02011166:
  255                 /* FALLTHROUGH */
  256         case 0x010f1014: /* IBM re-badged ServerWorks chipset */
  257                 s = "ServerWorks host to PCI bridge";
  258                 *busnum = nexus_pcib_read_config(0, bus, slot, func, 0x44, 1);
  259                 break;
  260 
  261         case 0x00091166:
  262                 s = "ServerWorks NB6635 3.0LE host to PCI bridge";
  263                 *busnum = nexus_pcib_read_config(0, bus, slot, func, 0x44, 1);
  264                 break;
  265 
  266         case 0x00101166:
  267                 s = "ServerWorks CIOB30 host to PCI bridge";
  268                 *busnum = nexus_pcib_read_config(0, bus, slot, func, 0x44, 1);
  269                 break;
  270 
  271         case 0x00111166:
  272                 /* FALLTHROUGH */
  273         case 0x03021014: /* IBM re-badged ServerWorks chipset */
  274                 s = "ServerWorks CMIC-HE host to PCI-X bridge";
  275                 *busnum = nexus_pcib_read_config(0, bus, slot, func, 0x44, 1);
  276                 break;
  277 
  278                 /* XXX unknown chipset, but working */
  279         case 0x00171166:
  280                 /* FALLTHROUGH */
  281         case 0x01011166:
  282                 s = "ServerWorks host to PCI bridge(unknown chipset)";
  283                 *busnum = nexus_pcib_read_config(0, bus, slot, func, 0x44, 1);
  284                 break;
  285 
  286                 /* Integrated Micro Solutions -- vendor 0x10e0 */
  287         case 0x884910e0:
  288                 s = "Integrated Micro Solutions VL Bridge";
  289                 break;
  290 
  291         default:
  292                 if (class == PCIC_BRIDGE && subclass == PCIS_BRIDGE_HOST)
  293                         s = "Host to PCI bridge";
  294                 break;
  295         }
  296 
  297         return s;
  298 }
  299 
  300 /*
  301  * Scan the first pci bus for host-pci bridges and add pcib instances
  302  * to the nexus for each bridge.
  303  */
  304 static void
  305 nexus_pcib_identify(driver_t *driver, device_t parent)
  306 {
  307         int bus, slot, func;
  308         u_int8_t  hdrtype;
  309         int found = 0;
  310         int pcifunchigh;
  311         int found824xx = 0;
  312         int found_orion = 0;
  313         device_t child;
  314         devclass_t pci_devclass;
  315 
  316         if (pci_cfgregopen() == 0)
  317                 return;
  318         /*
  319          * Check to see if we haven't already had a PCI bus added
  320          * via some other means.  If we have, bail since otherwise
  321          * we're going to end up duplicating it.
  322          */
  323         if ((pci_devclass = devclass_find("pci")) && 
  324                 devclass_get_device(pci_devclass, 0))
  325                 return;
  326 
  327 
  328         bus = 0;
  329  retry:
  330         for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
  331                 func = 0;
  332                 hdrtype = nexus_pcib_read_config(0, bus, slot, func,
  333                                                  PCIR_HEADERTYPE, 1);
  334                 if ((hdrtype & PCIM_MFDEV) && 
  335                     (!found_orion || hdrtype != 0xff))
  336                         pcifunchigh = 7;
  337                 else
  338                         pcifunchigh = 0;
  339                 for (func = 0; func <= pcifunchigh; func++) {
  340                         /*
  341                          * Read the IDs and class from the device.
  342                          */
  343                         u_int32_t id;
  344                         u_int8_t class, subclass, busnum;
  345                         const char *s;
  346                         device_t *devs;
  347                         int ndevs, i;
  348 
  349                         id = nexus_pcib_read_config(0, bus, slot, func,
  350                                                     PCIR_DEVVENDOR, 4);
  351                         if (id == -1)
  352                                 continue;
  353                         class = nexus_pcib_read_config(0, bus, slot, func,
  354                                                        PCIR_CLASS, 1);
  355                         subclass = nexus_pcib_read_config(0, bus, slot, func,
  356                                                           PCIR_SUBCLASS, 1);
  357 
  358                         s = nexus_pcib_is_host_bridge(bus, slot, func,
  359                                                       id, class, subclass,
  360                                                       &busnum);
  361                         if (s == NULL)
  362                                 continue;
  363 
  364                         /*
  365                          * Check to see if the physical bus has already
  366                          * been seen.  Eg: hybrid 32 and 64 bit host
  367                          * bridges to the same logical bus.
  368                          */
  369                         if (device_get_children(parent, &devs, &ndevs) == 0) {
  370                                 for (i = 0; s != NULL && i < ndevs; i++) {
  371                                         if (strcmp(device_get_name(devs[i]),
  372                                             "pcib") != 0)
  373                                                 continue;
  374                                         if (legacy_get_pcibus(devs[i]) == busnum)
  375                                                 s = NULL;
  376                                 }
  377                                 free(devs, M_TEMP);
  378                         }
  379 
  380                         if (s == NULL)
  381                                 continue;
  382                         /*
  383                          * Add at priority 100 to make sure we
  384                          * go after any motherboard resources
  385                          */
  386                         child = BUS_ADD_CHILD(parent, 100,
  387                                               "pcib", busnum);
  388                         device_set_desc(child, s);
  389                         legacy_set_pcibus(child, busnum);
  390 
  391                         found = 1;
  392                         if (id == 0x12258086)
  393                                 found824xx = 1;
  394                         if (id == 0x84c48086)
  395                                 found_orion = 1;
  396                 }
  397         }
  398         if (found824xx && bus == 0) {
  399                 bus++;
  400                 goto retry;
  401         }
  402 
  403         /*
  404          * Make sure we add at least one bridge since some old
  405          * hardware doesn't actually have a host-pci bridge device.
  406          * Note that pci_cfgregopen() thinks we have PCI devices..
  407          */
  408         if (!found) {
  409                 if (bootverbose)
  410                         printf(
  411         "nexus_pcib_identify: no bridge found, adding pcib0 anyway\n");
  412                 child = BUS_ADD_CHILD(parent, 100, "pcib", 0);
  413                 legacy_set_pcibus(child, 0);
  414         }
  415 }
  416 
  417 static int
  418 nexus_pcib_probe(device_t dev)
  419 {
  420 
  421         if (pci_cfgregopen() == 0)
  422                 return ENXIO;
  423         return 0;
  424 }
  425 
  426 static int
  427 nexus_pcib_attach(device_t dev)
  428 {
  429         device_t child;
  430 
  431         child = device_add_child(dev, "pci", pcib_get_bus(dev));
  432 
  433         return bus_generic_attach(dev);
  434 }
  435 
  436 static int
  437 nexus_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
  438 {
  439 
  440         switch (which) {
  441         case  PCIB_IVAR_BUS:
  442                 *result = legacy_get_pcibus(dev);
  443                 return 0;
  444         }
  445         return ENOENT;
  446 }
  447 
  448 static int
  449 nexus_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
  450 {
  451 
  452         switch (which) {
  453         case  PCIB_IVAR_BUS:
  454                 legacy_set_pcibus(dev, value);
  455                 return 0;
  456         }
  457         return ENOENT;
  458 }
  459 
  460 
  461 static device_method_t nexus_pcib_methods[] = {
  462         /* Device interface */
  463         DEVMETHOD(device_identify,      nexus_pcib_identify),
  464         DEVMETHOD(device_probe,         nexus_pcib_probe),
  465         DEVMETHOD(device_attach,        nexus_pcib_attach),
  466         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
  467         DEVMETHOD(device_suspend,       bus_generic_suspend),
  468         DEVMETHOD(device_resume,        bus_generic_resume),
  469 
  470         /* Bus interface */
  471         DEVMETHOD(bus_print_child,      bus_generic_print_child),
  472         DEVMETHOD(bus_read_ivar,        nexus_pcib_read_ivar),
  473         DEVMETHOD(bus_write_ivar,       nexus_pcib_write_ivar),
  474         DEVMETHOD(bus_alloc_resource,   bus_generic_alloc_resource),
  475         DEVMETHOD(bus_release_resource, bus_generic_release_resource),
  476         DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
  477         DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
  478         DEVMETHOD(bus_setup_intr,       bus_generic_setup_intr),
  479         DEVMETHOD(bus_teardown_intr,    bus_generic_teardown_intr),
  480 
  481         /* pcib interface */
  482         DEVMETHOD(pcib_maxslots,        nexus_pcib_maxslots),
  483         DEVMETHOD(pcib_read_config,     nexus_pcib_read_config),
  484         DEVMETHOD(pcib_write_config,    nexus_pcib_write_config),
  485         DEVMETHOD(pcib_route_interrupt, nexus_pcib_route_interrupt),
  486 
  487         { 0, 0 }
  488 };
  489 
  490 static driver_t nexus_pcib_driver = {
  491         "pcib",
  492         nexus_pcib_methods,
  493         1,
  494 };
  495 
  496 DRIVER_MODULE(pcib, legacy, nexus_pcib_driver, pcib_devclass, 0, 0);
  497 
  498 
  499 /*
  500  * Provide a device to "eat" the host->pci bridges that we dug up above
  501  * and stop them showing up twice on the probes.  This also stops them
  502  * showing up as 'none' in pciconf -l.
  503  */
  504 static int
  505 pci_hostb_probe(device_t dev)
  506 {
  507         u_int32_t id;
  508 
  509         id = pci_get_devid(dev);
  510 
  511         switch (id) {
  512 
  513         /* VIA VT82C596 Power Managment Function */
  514         case 0x30501106:
  515                 return ENXIO;
  516 
  517         default:
  518                 break;
  519         }
  520 
  521         if (pci_get_class(dev) == PCIC_BRIDGE &&
  522             pci_get_subclass(dev) == PCIS_BRIDGE_HOST) {
  523                 device_set_desc(dev, "Host to PCI bridge");
  524                 device_quiet(dev);
  525                 return -10000;
  526         }
  527         return ENXIO;
  528 }
  529 
  530 static int
  531 pci_hostb_attach(device_t dev)
  532 {
  533 
  534         return 0;
  535 }
  536 
  537 static device_method_t pci_hostb_methods[] = {
  538         /* Device interface */
  539         DEVMETHOD(device_probe,         pci_hostb_probe),
  540         DEVMETHOD(device_attach,        pci_hostb_attach),
  541         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
  542         DEVMETHOD(device_suspend,       bus_generic_suspend),
  543         DEVMETHOD(device_resume,        bus_generic_resume),
  544 
  545         { 0, 0 }
  546 };
  547 static driver_t pci_hostb_driver = {
  548         "hostb",
  549         pci_hostb_methods,
  550         1,
  551 };
  552 static devclass_t pci_hostb_devclass;
  553 
  554 DRIVER_MODULE(hostb, pci, pci_hostb_driver, pci_hostb_devclass, 0, 0);
  555 
  556 
  557 /*
  558  * Install placeholder to claim the resources owned by the
  559  * PCI bus interface.  This could be used to extract the 
  560  * config space registers in the extreme case where the PnP
  561  * ID is available and the PCI BIOS isn't, but for now we just
  562  * eat the PnP ID and do nothing else.
  563  *
  564  * XXX we should silence this probe, as it will generally confuse 
  565  * people.
  566  */
  567 static struct isa_pnp_id pcibus_pnp_ids[] = {
  568         { 0x030ad041 /* PNP0A03 */, "PCI Bus" },
  569         { 0 }
  570 };
  571 
  572 static int
  573 pcibus_pnp_probe(device_t dev)
  574 {
  575         int result;
  576         
  577         if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, pcibus_pnp_ids)) <= 0)
  578                 device_quiet(dev);
  579         return(result);
  580 }
  581 
  582 static int
  583 pcibus_pnp_attach(device_t dev)
  584 {
  585         return(0);
  586 }
  587 
  588 static device_method_t pcibus_pnp_methods[] = {
  589         /* Device interface */
  590         DEVMETHOD(device_probe,         pcibus_pnp_probe),
  591         DEVMETHOD(device_attach,        pcibus_pnp_attach),
  592         DEVMETHOD(device_detach,        bus_generic_detach),
  593         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
  594         DEVMETHOD(device_suspend,       bus_generic_suspend),
  595         DEVMETHOD(device_resume,        bus_generic_resume),
  596         { 0, 0 }
  597 };
  598 
  599 static driver_t pcibus_pnp_driver = {
  600         "pcibus_pnp",
  601         pcibus_pnp_methods,
  602         1,              /* no softc */
  603 };
  604 
  605 static devclass_t pcibus_pnp_devclass;
  606 
  607 DRIVER_MODULE(pcibus_pnp, isa, pcibus_pnp_driver, pcibus_pnp_devclass, 0, 0);
  608 
  609 
  610 /*
  611  * Provide a PCI-PCI bridge driver for PCI busses behind PCI-PCI bridges
  612  * that appear in the PCIBIOS Interrupt Routing Table to use the routing
  613  * table for interrupt routing when possible.
  614  */
  615 static int      pcibios_pcib_probe(device_t bus);
  616 
  617 static device_method_t pcibios_pcib_pci_methods[] = {
  618         /* Device interface */
  619         DEVMETHOD(device_probe,         pcibios_pcib_probe),
  620         DEVMETHOD(device_attach,        pcib_attach),
  621         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
  622         DEVMETHOD(device_suspend,       bus_generic_suspend),
  623         DEVMETHOD(device_resume,        bus_generic_resume),
  624 
  625         /* Bus interface */
  626         DEVMETHOD(bus_print_child,      bus_generic_print_child),
  627         DEVMETHOD(bus_read_ivar,        pcib_read_ivar),
  628         DEVMETHOD(bus_write_ivar,       pcib_write_ivar),
  629         DEVMETHOD(bus_alloc_resource,   pcib_alloc_resource),
  630         DEVMETHOD(bus_release_resource, bus_generic_release_resource),
  631         DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
  632         DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
  633         DEVMETHOD(bus_setup_intr,       bus_generic_setup_intr),
  634         DEVMETHOD(bus_teardown_intr,    bus_generic_teardown_intr),
  635 
  636         /* pcib interface */
  637         DEVMETHOD(pcib_maxslots,        pcib_maxslots),
  638         DEVMETHOD(pcib_read_config,     pcib_read_config),
  639         DEVMETHOD(pcib_write_config,    pcib_write_config),
  640         DEVMETHOD(pcib_route_interrupt, pcibios_pcib_route_interrupt),
  641 
  642         {0, 0}
  643 };
  644 
  645 static driver_t pcibios_pcib_driver = {
  646         "pcib",
  647         pcibios_pcib_pci_methods,
  648         sizeof(struct pcib_softc),
  649 };
  650 
  651 DRIVER_MODULE(pcibios_pcib, pci, pcibios_pcib_driver, pcib_devclass, 0, 0);
  652 
  653 static int
  654 pcibios_pcib_probe(device_t dev)
  655 {
  656 
  657         if ((pci_get_class(dev) != PCIC_BRIDGE) ||
  658             (pci_get_subclass(dev) != PCIS_BRIDGE_PCI))
  659                 return (ENXIO);
  660         if (pci_probe_route_table(pcib_get_bus(dev)) == 0)
  661                 return (ENXIO);
  662         device_set_desc(dev, "PCIBIOS PCI-PCI bridge");
  663         return (-2000);
  664 }
  665 
  666 static int
  667 pcibios_pcib_route_interrupt(device_t pcib, device_t dev, int pin)
  668 {
  669         return(pci_cfgintr(pci_get_bus(dev), pci_get_slot(dev), pin,
  670                    pci_get_irq(dev)));
  671 }
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FreeBSD/Linux Kernel Cross Reference sys/i386/pci/pci_bus.c

FreeBSD/Linux Kernel Cross Reference
sys/i386/pci/pci_bus.c
