The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/i386/pci/pci_bus.c

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    1 /*
    2  * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice unmodified, this list of conditions, and the following
   10  *    disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  *
   15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   25  */
   26 
   27 #include <sys/cdefs.h>
   28 __FBSDID("$FreeBSD: releng/5.2/sys/i386/pci/pci_bus.c 121822 2003-10-31 21:00:37Z jhb $");
   29 
   30 #include "opt_cpu.h"
   31 
   32 #include <sys/param.h>
   33 #include <sys/systm.h>
   34 #include <sys/bus.h>
   35 #include <sys/kernel.h>
   36 #include <sys/module.h>
   37 #include <sys/malloc.h>
   38 
   39 #include <dev/pci/pcivar.h>
   40 #include <dev/pci/pcireg.h>
   41 #include <dev/pci/pcib_private.h>
   42 #include <isa/isavar.h>
   43 #include <machine/legacyvar.h>
   44 #include <machine/pci_cfgreg.h>
   45 #include <machine/segments.h>
   46 #include <machine/cputypes.h>
   47 #include <machine/pc/bios.h>
   48 #include <machine/md_var.h>
   49 
   50 #include "pcib_if.h"
   51 
   52 static int      pcibios_pcib_route_interrupt(device_t pcib, device_t dev,
   53     int pin);
   54 
   55 int
   56 legacy_pcib_maxslots(device_t dev)
   57 {
   58         return 31;
   59 }
   60 
   61 /* read configuration space register */
   62 
   63 u_int32_t
   64 legacy_pcib_read_config(device_t dev, int bus, int slot, int func,
   65                         int reg, int bytes)
   66 {
   67         return(pci_cfgregread(bus, slot, func, reg, bytes));
   68 }
   69 
   70 /* write configuration space register */
   71 
   72 void
   73 legacy_pcib_write_config(device_t dev, int bus, int slot, int func,
   74                          int reg, u_int32_t data, int bytes)
   75 {
   76         pci_cfgregwrite(bus, slot, func, reg, data, bytes);
   77 }
   78 
   79 static const char *
   80 legacy_pcib_is_host_bridge(int bus, int slot, int func,
   81                           u_int32_t id, u_int8_t class, u_int8_t subclass,
   82                           u_int8_t *busnum)
   83 {
   84         const char *s = NULL;
   85         static u_int8_t pxb[4]; /* hack for 450nx */
   86 
   87         *busnum = 0;
   88 
   89         switch (id) {
   90         case 0x12258086:
   91                 s = "Intel 824?? host to PCI bridge";
   92                 /* XXX This is a guess */
   93                 /* *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x41, 1); */
   94                 *busnum = bus;
   95                 break;
   96         case 0x71208086:
   97                 s = "Intel 82810 (i810 GMCH) Host To Hub bridge";
   98                 break;
   99         case 0x71228086:
  100                 s = "Intel 82810-DC100 (i810-DC100 GMCH) Host To Hub bridge";
  101                 break;
  102         case 0x71248086:
  103                 s = "Intel 82810E (i810E GMCH) Host To Hub bridge";
  104                 break;
  105         case 0x11308086:
  106                 s = "Intel 82815 (i815 GMCH) Host To Hub bridge";
  107                 break;
  108         case 0x71808086:
  109                 s = "Intel 82443LX (440 LX) host to PCI bridge";
  110                 break;
  111         case 0x71908086:
  112                 s = "Intel 82443BX (440 BX) host to PCI bridge";
  113                 break;
  114         case 0x71928086:
  115                 s = "Intel 82443BX host to PCI bridge (AGP disabled)";
  116                 break;
  117         case 0x71948086:
  118                 s = "Intel 82443MX host to PCI bridge";
  119                 break;
  120         case 0x71a08086:
  121                 s = "Intel 82443GX host to PCI bridge";
  122                 break;
  123         case 0x71a18086:
  124                 s = "Intel 82443GX host to AGP bridge";
  125                 break;
  126         case 0x71a28086:
  127                 s = "Intel 82443GX host to PCI bridge (AGP disabled)";
  128                 break;
  129         case 0x84c48086:
  130                 s = "Intel 82454KX/GX (Orion) host to PCI bridge";
  131                 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x4a, 1);
  132                 break;
  133         case 0x84ca8086:
  134                 /*
  135                  * For the 450nx chipset, there is a whole bundle of
  136                  * things pretending to be host bridges. The MIOC will 
  137                  * be seen first and isn't really a pci bridge (the
  138                  * actual busses are attached to the PXB's). We need to 
  139                  * read the registers of the MIOC to figure out the
  140                  * bus numbers for the PXB channels.
  141                  *
  142                  * Since the MIOC doesn't have a pci bus attached, we
  143                  * pretend it wasn't there.
  144                  */
  145                 pxb[0] = legacy_pcib_read_config(0, bus, slot, func,
  146                                                 0xd0, 1); /* BUSNO[0] */
  147                 pxb[1] = legacy_pcib_read_config(0, bus, slot, func,
  148                                                 0xd1, 1) + 1;   /* SUBA[0]+1 */
  149                 pxb[2] = legacy_pcib_read_config(0, bus, slot, func,
  150                                                 0xd3, 1); /* BUSNO[1] */
  151                 pxb[3] = legacy_pcib_read_config(0, bus, slot, func,
  152                                                 0xd4, 1) + 1;   /* SUBA[1]+1 */
  153                 return NULL;
  154         case 0x84cb8086:
  155                 switch (slot) {
  156                 case 0x12:
  157                         s = "Intel 82454NX PXB#0, Bus#A";
  158                         *busnum = pxb[0];
  159                         break;
  160                 case 0x13:
  161                         s = "Intel 82454NX PXB#0, Bus#B";
  162                         *busnum = pxb[1];
  163                         break;
  164                 case 0x14:
  165                         s = "Intel 82454NX PXB#1, Bus#A";
  166                         *busnum = pxb[2];
  167                         break;
  168                 case 0x15:
  169                         s = "Intel 82454NX PXB#1, Bus#B";
  170                         *busnum = pxb[3];
  171                         break;
  172                 }
  173                 break;
  174 
  175                 /* AMD -- vendor 0x1022 */
  176         case 0x30001022:
  177                 s = "AMD Elan SC520 host to PCI bridge";
  178 #ifdef CPU_ELAN
  179                 init_AMD_Elan_sc520();
  180 #else
  181                 printf(
  182 "*** WARNING: missing CPU_ELAN -- timekeeping may be wrong\n");
  183 #endif
  184                 break;
  185         case 0x70061022:
  186                 s = "AMD-751 host to PCI bridge";
  187                 break;
  188         case 0x700e1022:
  189                 s = "AMD-761 host to PCI bridge";
  190                 break;
  191 
  192                 /* SiS -- vendor 0x1039 */
  193         case 0x04961039:
  194                 s = "SiS 85c496";
  195                 break;
  196         case 0x04061039:
  197                 s = "SiS 85c501";
  198                 break;
  199         case 0x06011039:
  200                 s = "SiS 85c601";
  201                 break;
  202         case 0x55911039:
  203                 s = "SiS 5591 host to PCI bridge";
  204                 break;
  205         case 0x00011039:
  206                 s = "SiS 5591 host to AGP bridge";
  207                 break;
  208 
  209                 /* VLSI -- vendor 0x1004 */
  210         case 0x00051004:
  211                 s = "VLSI 82C592 Host to PCI bridge";
  212                 break;
  213 
  214                 /* XXX Here is MVP3, I got the datasheet but NO M/B to test it  */
  215                 /* totally. Please let me know if anything wrong.            -F */
  216                 /* XXX need info on the MVP3 -- any takers? */
  217         case 0x05981106:
  218                 s = "VIA 82C598MVP (Apollo MVP3) host bridge";
  219                 break;
  220 
  221                 /* AcerLabs -- vendor 0x10b9 */
  222                 /* Funny : The datasheet told me vendor id is "10b8",sub-vendor */
  223                 /* id is '10b9" but the register always shows "10b9". -Foxfair  */
  224         case 0x154110b9:
  225                 s = "AcerLabs M1541 (Aladdin-V) PCI host bridge";
  226                 break;
  227 
  228                 /* OPTi -- vendor 0x1045 */
  229         case 0xc7011045:
  230                 s = "OPTi 82C700 host to PCI bridge";
  231                 break;
  232         case 0xc8221045:
  233                 s = "OPTi 82C822 host to PCI Bridge";
  234                 break;
  235 
  236                 /* ServerWorks -- vendor 0x1166 */
  237         case 0x00051166:
  238                 s = "ServerWorks NB6536 2.0HE host to PCI bridge";
  239                 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
  240                 break;
  241         
  242         case 0x00061166:
  243                 /* FALLTHROUGH */
  244         case 0x00081166:
  245                 /* FALLTHROUGH */
  246         case 0x02011166:
  247                 /* FALLTHROUGH */
  248         case 0x010f1014: /* IBM re-badged ServerWorks chipset */
  249                 s = "ServerWorks host to PCI bridge";
  250                 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
  251                 break;
  252 
  253         case 0x00091166:
  254                 s = "ServerWorks NB6635 3.0LE host to PCI bridge";
  255                 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
  256                 break;
  257 
  258         case 0x00101166:
  259                 s = "ServerWorks CIOB30 host to PCI bridge";
  260                 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
  261                 break;
  262 
  263         case 0x00111166:
  264                 /* FALLTHROUGH */
  265         case 0x03021014: /* IBM re-badged ServerWorks chipset */
  266                 s = "ServerWorks CMIC-HE host to PCI-X bridge";
  267                 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
  268                 break;
  269 
  270                 /* XXX unknown chipset, but working */
  271         case 0x00171166:
  272                 /* FALLTHROUGH */
  273         case 0x01011166:
  274                 s = "ServerWorks host to PCI bridge(unknown chipset)";
  275                 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
  276                 break;
  277 
  278                 /* Integrated Micro Solutions -- vendor 0x10e0 */
  279         case 0x884910e0:
  280                 s = "Integrated Micro Solutions VL Bridge";
  281                 break;
  282 
  283         default:
  284                 if (class == PCIC_BRIDGE && subclass == PCIS_BRIDGE_HOST)
  285                         s = "Host to PCI bridge";
  286                 break;
  287         }
  288 
  289         return s;
  290 }
  291 
  292 /*
  293  * Scan the first pci bus for host-pci bridges and add pcib instances
  294  * to the nexus for each bridge.
  295  */
  296 static void
  297 legacy_pcib_identify(driver_t *driver, device_t parent)
  298 {
  299         int bus, slot, func;
  300         u_int8_t  hdrtype;
  301         int found = 0;
  302         int pcifunchigh;
  303         int found824xx = 0;
  304         int found_orion = 0;
  305         device_t child;
  306         devclass_t pci_devclass;
  307 
  308         if (pci_cfgregopen() == 0)
  309                 return;
  310         /*
  311          * Check to see if we haven't already had a PCI bus added
  312          * via some other means.  If we have, bail since otherwise
  313          * we're going to end up duplicating it.
  314          */
  315         if ((pci_devclass = devclass_find("pci")) && 
  316                 devclass_get_device(pci_devclass, 0))
  317                 return;
  318 
  319 
  320         bus = 0;
  321  retry:
  322         for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
  323                 func = 0;
  324                 hdrtype = legacy_pcib_read_config(0, bus, slot, func,
  325                                                  PCIR_HDRTYPE, 1);
  326                 /*
  327                  * When enumerating bus devices, the standard says that
  328                  * one should check the header type and ignore the slots whose
  329                  * header types that the software doesn't know about.  We use
  330                  * this to filter out devices.
  331                  */
  332                 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
  333                         continue;
  334                 if ((hdrtype & PCIM_MFDEV) && 
  335                     (!found_orion || hdrtype != 0xff))
  336                         pcifunchigh = PCI_FUNCMAX;
  337                 else
  338                         pcifunchigh = 0;
  339                 for (func = 0; func <= pcifunchigh; func++) {
  340                         /*
  341                          * Read the IDs and class from the device.
  342                          */
  343                         u_int32_t id;
  344                         u_int8_t class, subclass, busnum;
  345                         const char *s;
  346                         device_t *devs;
  347                         int ndevs, i;
  348 
  349                         id = legacy_pcib_read_config(0, bus, slot, func,
  350                                                     PCIR_DEVVENDOR, 4);
  351                         if (id == -1)
  352                                 continue;
  353                         class = legacy_pcib_read_config(0, bus, slot, func,
  354                                                        PCIR_CLASS, 1);
  355                         subclass = legacy_pcib_read_config(0, bus, slot, func,
  356                                                           PCIR_SUBCLASS, 1);
  357 
  358                         s = legacy_pcib_is_host_bridge(bus, slot, func,
  359                                                       id, class, subclass,
  360                                                       &busnum);
  361                         if (s == NULL)
  362                                 continue;
  363 
  364                         /*
  365                          * Check to see if the physical bus has already
  366                          * been seen.  Eg: hybrid 32 and 64 bit host
  367                          * bridges to the same logical bus.
  368                          */
  369                         if (device_get_children(parent, &devs, &ndevs) == 0) {
  370                                 for (i = 0; s != NULL && i < ndevs; i++) {
  371                                         if (strcmp(device_get_name(devs[i]),
  372                                             "pcib") != 0)
  373                                                 continue;
  374                                         if (legacy_get_pcibus(devs[i]) == busnum)
  375                                                 s = NULL;
  376                                 }
  377                                 free(devs, M_TEMP);
  378                         }
  379 
  380                         if (s == NULL)
  381                                 continue;
  382                         /*
  383                          * Add at priority 100 to make sure we
  384                          * go after any motherboard resources
  385                          */
  386                         child = BUS_ADD_CHILD(parent, 100,
  387                                               "pcib", busnum);
  388                         device_set_desc(child, s);
  389                         legacy_set_pcibus(child, busnum);
  390 
  391                         found = 1;
  392                         if (id == 0x12258086)
  393                                 found824xx = 1;
  394                         if (id == 0x84c48086)
  395                                 found_orion = 1;
  396                 }
  397         }
  398         if (found824xx && bus == 0) {
  399                 bus++;
  400                 goto retry;
  401         }
  402 
  403         /*
  404          * Make sure we add at least one bridge since some old
  405          * hardware doesn't actually have a host-pci bridge device.
  406          * Note that pci_cfgregopen() thinks we have PCI devices..
  407          */
  408         if (!found) {
  409                 if (bootverbose)
  410                         printf(
  411         "legacy_pcib_identify: no bridge found, adding pcib0 anyway\n");
  412                 child = BUS_ADD_CHILD(parent, 100, "pcib", 0);
  413                 legacy_set_pcibus(child, 0);
  414         }
  415 }
  416 
  417 static int
  418 legacy_pcib_probe(device_t dev)
  419 {
  420 
  421         if (pci_cfgregopen() == 0)
  422                 return ENXIO;
  423         return -100;
  424 }
  425 
  426 int
  427 legacy_pcib_attach(device_t dev)
  428 {
  429 
  430         device_add_child(dev, "pci", pcib_get_bus(dev));
  431 
  432         return bus_generic_attach(dev);
  433 }
  434 
  435 int
  436 legacy_pcib_read_ivar(device_t dev, device_t child, int which,
  437     uintptr_t *result)
  438 {
  439 
  440         switch (which) {
  441         case  PCIB_IVAR_BUS:
  442                 *result = legacy_get_pcibus(dev);
  443                 return 0;
  444         }
  445         return ENOENT;
  446 }
  447 
  448 int
  449 legacy_pcib_write_ivar(device_t dev, device_t child, int which,
  450     uintptr_t value)
  451 {
  452 
  453         switch (which) {
  454         case  PCIB_IVAR_BUS:
  455                 legacy_set_pcibus(dev, value);
  456                 return 0;
  457         }
  458         return ENOENT;
  459 }
  460 
  461 
  462 static device_method_t legacy_pcib_methods[] = {
  463         /* Device interface */
  464         DEVMETHOD(device_identify,      legacy_pcib_identify),
  465         DEVMETHOD(device_probe,         legacy_pcib_probe),
  466         DEVMETHOD(device_attach,        legacy_pcib_attach),
  467         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
  468         DEVMETHOD(device_suspend,       bus_generic_suspend),
  469         DEVMETHOD(device_resume,        bus_generic_resume),
  470 
  471         /* Bus interface */
  472         DEVMETHOD(bus_print_child,      bus_generic_print_child),
  473         DEVMETHOD(bus_read_ivar,        legacy_pcib_read_ivar),
  474         DEVMETHOD(bus_write_ivar,       legacy_pcib_write_ivar),
  475         DEVMETHOD(bus_alloc_resource,   bus_generic_alloc_resource),
  476         DEVMETHOD(bus_release_resource, bus_generic_release_resource),
  477         DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
  478         DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
  479         DEVMETHOD(bus_setup_intr,       bus_generic_setup_intr),
  480         DEVMETHOD(bus_teardown_intr,    bus_generic_teardown_intr),
  481 
  482         /* pcib interface */
  483         DEVMETHOD(pcib_maxslots,        legacy_pcib_maxslots),
  484         DEVMETHOD(pcib_read_config,     legacy_pcib_read_config),
  485         DEVMETHOD(pcib_write_config,    legacy_pcib_write_config),
  486         DEVMETHOD(pcib_route_interrupt, pcibios_pcib_route_interrupt),
  487 
  488         { 0, 0 }
  489 };
  490 
  491 static driver_t legacy_pcib_driver = {
  492         "pcib",
  493         legacy_pcib_methods,
  494         1,
  495 };
  496 
  497 DRIVER_MODULE(pcib, legacy, legacy_pcib_driver, pcib_devclass, 0, 0);
  498 
  499 
  500 /*
  501  * Provide a device to "eat" the host->pci bridges that we dug up above
  502  * and stop them showing up twice on the probes.  This also stops them
  503  * showing up as 'none' in pciconf -l.
  504  */
  505 static int
  506 pci_hostb_probe(device_t dev)
  507 {
  508         u_int32_t id;
  509 
  510         id = pci_get_devid(dev);
  511 
  512         switch (id) {
  513 
  514         /* VIA VT82C596 Power Managment Function */
  515         case 0x30501106:
  516                 return ENXIO;
  517 
  518         default:
  519                 break;
  520         }
  521 
  522         if (pci_get_class(dev) == PCIC_BRIDGE &&
  523             pci_get_subclass(dev) == PCIS_BRIDGE_HOST) {
  524                 device_set_desc(dev, "Host to PCI bridge");
  525                 device_quiet(dev);
  526                 return -10000;
  527         }
  528         return ENXIO;
  529 }
  530 
  531 static int
  532 pci_hostb_attach(device_t dev)
  533 {
  534 
  535         return 0;
  536 }
  537 
  538 static device_method_t pci_hostb_methods[] = {
  539         /* Device interface */
  540         DEVMETHOD(device_probe,         pci_hostb_probe),
  541         DEVMETHOD(device_attach,        pci_hostb_attach),
  542         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
  543         DEVMETHOD(device_suspend,       bus_generic_suspend),
  544         DEVMETHOD(device_resume,        bus_generic_resume),
  545 
  546         { 0, 0 }
  547 };
  548 static driver_t pci_hostb_driver = {
  549         "hostb",
  550         pci_hostb_methods,
  551         1,
  552 };
  553 static devclass_t pci_hostb_devclass;
  554 
  555 DRIVER_MODULE(hostb, pci, pci_hostb_driver, pci_hostb_devclass, 0, 0);
  556 
  557 
  558 /*
  559  * Install placeholder to claim the resources owned by the
  560  * PCI bus interface.  This could be used to extract the 
  561  * config space registers in the extreme case where the PnP
  562  * ID is available and the PCI BIOS isn't, but for now we just
  563  * eat the PnP ID and do nothing else.
  564  *
  565  * XXX we should silence this probe, as it will generally confuse 
  566  * people.
  567  */
  568 static struct isa_pnp_id pcibus_pnp_ids[] = {
  569         { 0x030ad041 /* PNP0A03 */, "PCI Bus" },
  570         { 0 }
  571 };
  572 
  573 static int
  574 pcibus_pnp_probe(device_t dev)
  575 {
  576         int result;
  577         
  578         if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, pcibus_pnp_ids)) <= 0)
  579                 device_quiet(dev);
  580         return(result);
  581 }
  582 
  583 static int
  584 pcibus_pnp_attach(device_t dev)
  585 {
  586         return(0);
  587 }
  588 
  589 static device_method_t pcibus_pnp_methods[] = {
  590         /* Device interface */
  591         DEVMETHOD(device_probe,         pcibus_pnp_probe),
  592         DEVMETHOD(device_attach,        pcibus_pnp_attach),
  593         DEVMETHOD(device_detach,        bus_generic_detach),
  594         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
  595         DEVMETHOD(device_suspend,       bus_generic_suspend),
  596         DEVMETHOD(device_resume,        bus_generic_resume),
  597         { 0, 0 }
  598 };
  599 
  600 static driver_t pcibus_pnp_driver = {
  601         "pcibus_pnp",
  602         pcibus_pnp_methods,
  603         1,              /* no softc */
  604 };
  605 
  606 static devclass_t pcibus_pnp_devclass;
  607 
  608 DRIVER_MODULE(pcibus_pnp, isa, pcibus_pnp_driver, pcibus_pnp_devclass, 0, 0);
  609 
  610 
  611 /*
  612  * Provide a PCI-PCI bridge driver for PCI busses behind PCI-PCI bridges
  613  * that appear in the PCIBIOS Interrupt Routing Table to use the routing
  614  * table for interrupt routing when possible.
  615  */
  616 static int      pcibios_pcib_probe(device_t bus);
  617 
  618 static device_method_t pcibios_pcib_pci_methods[] = {
  619         /* Device interface */
  620         DEVMETHOD(device_probe,         pcibios_pcib_probe),
  621         DEVMETHOD(device_attach,        pcib_attach),
  622         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
  623         DEVMETHOD(device_suspend,       bus_generic_suspend),
  624         DEVMETHOD(device_resume,        bus_generic_resume),
  625 
  626         /* Bus interface */
  627         DEVMETHOD(bus_print_child,      bus_generic_print_child),
  628         DEVMETHOD(bus_read_ivar,        pcib_read_ivar),
  629         DEVMETHOD(bus_write_ivar,       pcib_write_ivar),
  630         DEVMETHOD(bus_alloc_resource,   pcib_alloc_resource),
  631         DEVMETHOD(bus_release_resource, bus_generic_release_resource),
  632         DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
  633         DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
  634         DEVMETHOD(bus_setup_intr,       bus_generic_setup_intr),
  635         DEVMETHOD(bus_teardown_intr,    bus_generic_teardown_intr),
  636 
  637         /* pcib interface */
  638         DEVMETHOD(pcib_maxslots,        pcib_maxslots),
  639         DEVMETHOD(pcib_read_config,     pcib_read_config),
  640         DEVMETHOD(pcib_write_config,    pcib_write_config),
  641         DEVMETHOD(pcib_route_interrupt, pcibios_pcib_route_interrupt),
  642 
  643         {0, 0}
  644 };
  645 
  646 static driver_t pcibios_pcib_driver = {
  647         "pcib",
  648         pcibios_pcib_pci_methods,
  649         sizeof(struct pcib_softc),
  650 };
  651 
  652 DRIVER_MODULE(pcibios_pcib, pci, pcibios_pcib_driver, pcib_devclass, 0, 0);
  653 
  654 static int
  655 pcibios_pcib_probe(device_t dev)
  656 {
  657         int bus;
  658 
  659         if ((pci_get_class(dev) != PCIC_BRIDGE) ||
  660             (pci_get_subclass(dev) != PCIS_BRIDGE_PCI))
  661                 return (ENXIO);
  662         bus = pci_read_config(dev, PCIR_SECBUS_1, 1);
  663         if (bus == 0)
  664                 return (ENXIO);
  665         if (pci_probe_route_table(bus) == 0)
  666                 return (ENXIO);
  667         device_set_desc(dev, "PCIBIOS PCI-PCI bridge");
  668         return (-2000);
  669 }
  670 
  671 static int
  672 pcibios_pcib_route_interrupt(device_t pcib, device_t dev, int pin)
  673 {
  674         return(pci_cfgintr(pci_get_bus(dev), pci_get_slot(dev), pin,
  675                    pci_get_irq(dev)));
  676 }

Cache object: bf601ba1ec9f027ca05fa0d839783678


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