FreeBSD/Linux Kernel Cross Reference
sys/i386/pci/pci_bus.c
1 /*-
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD: src/sys/i386/pci/pci_bus.c,v 1.112.2.5 2005/02/14 11:23:42 obrien Exp $");
29
30 #include "opt_cpu.h"
31
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/bus.h>
35 #include <sys/kernel.h>
36 #include <sys/malloc.h>
37 #include <sys/module.h>
38 #include <sys/sysctl.h>
39
40 #include <dev/pci/pcivar.h>
41 #include <dev/pci/pcireg.h>
42 #include <dev/pci/pcib_private.h>
43 #include <isa/isavar.h>
44 #ifdef CPU_ELAN
45 #include <machine/md_var.h>
46 #endif
47 #include <machine/legacyvar.h>
48 #include <machine/pci_cfgreg.h>
49 #include <machine/resource.h>
50
51 #include "pcib_if.h"
52
53 static int pcibios_pcib_route_interrupt(device_t pcib, device_t dev,
54 int pin);
55
56 int
57 legacy_pcib_maxslots(device_t dev)
58 {
59 return 31;
60 }
61
62 /* read configuration space register */
63
64 u_int32_t
65 legacy_pcib_read_config(device_t dev, int bus, int slot, int func,
66 int reg, int bytes)
67 {
68 return(pci_cfgregread(bus, slot, func, reg, bytes));
69 }
70
71 /* write configuration space register */
72
73 void
74 legacy_pcib_write_config(device_t dev, int bus, int slot, int func,
75 int reg, u_int32_t data, int bytes)
76 {
77 pci_cfgregwrite(bus, slot, func, reg, data, bytes);
78 }
79
80 static const char *
81 legacy_pcib_is_host_bridge(int bus, int slot, int func,
82 uint32_t id, uint8_t class, uint8_t subclass,
83 uint8_t *busnum)
84 {
85 const char *s = NULL;
86 static uint8_t pxb[4]; /* hack for 450nx */
87
88 *busnum = 0;
89
90 switch (id) {
91 case 0x12258086:
92 s = "Intel 824?? host to PCI bridge";
93 /* XXX This is a guess */
94 /* *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x41, 1); */
95 *busnum = bus;
96 break;
97 case 0x71208086:
98 s = "Intel 82810 (i810 GMCH) Host To Hub bridge";
99 break;
100 case 0x71228086:
101 s = "Intel 82810-DC100 (i810-DC100 GMCH) Host To Hub bridge";
102 break;
103 case 0x71248086:
104 s = "Intel 82810E (i810E GMCH) Host To Hub bridge";
105 break;
106 case 0x11308086:
107 s = "Intel 82815 (i815 GMCH) Host To Hub bridge";
108 break;
109 case 0x71808086:
110 s = "Intel 82443LX (440 LX) host to PCI bridge";
111 break;
112 case 0x71908086:
113 s = "Intel 82443BX (440 BX) host to PCI bridge";
114 break;
115 case 0x71928086:
116 s = "Intel 82443BX host to PCI bridge (AGP disabled)";
117 break;
118 case 0x71948086:
119 s = "Intel 82443MX host to PCI bridge";
120 break;
121 case 0x71a08086:
122 s = "Intel 82443GX host to PCI bridge";
123 break;
124 case 0x71a18086:
125 s = "Intel 82443GX host to AGP bridge";
126 break;
127 case 0x71a28086:
128 s = "Intel 82443GX host to PCI bridge (AGP disabled)";
129 break;
130 case 0x84c48086:
131 s = "Intel 82454KX/GX (Orion) host to PCI bridge";
132 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x4a, 1);
133 break;
134 case 0x84ca8086:
135 /*
136 * For the 450nx chipset, there is a whole bundle of
137 * things pretending to be host bridges. The MIOC will
138 * be seen first and isn't really a pci bridge (the
139 * actual busses are attached to the PXB's). We need to
140 * read the registers of the MIOC to figure out the
141 * bus numbers for the PXB channels.
142 *
143 * Since the MIOC doesn't have a pci bus attached, we
144 * pretend it wasn't there.
145 */
146 pxb[0] = legacy_pcib_read_config(0, bus, slot, func,
147 0xd0, 1); /* BUSNO[0] */
148 pxb[1] = legacy_pcib_read_config(0, bus, slot, func,
149 0xd1, 1) + 1; /* SUBA[0]+1 */
150 pxb[2] = legacy_pcib_read_config(0, bus, slot, func,
151 0xd3, 1); /* BUSNO[1] */
152 pxb[3] = legacy_pcib_read_config(0, bus, slot, func,
153 0xd4, 1) + 1; /* SUBA[1]+1 */
154 return NULL;
155 case 0x84cb8086:
156 switch (slot) {
157 case 0x12:
158 s = "Intel 82454NX PXB#0, Bus#A";
159 *busnum = pxb[0];
160 break;
161 case 0x13:
162 s = "Intel 82454NX PXB#0, Bus#B";
163 *busnum = pxb[1];
164 break;
165 case 0x14:
166 s = "Intel 82454NX PXB#1, Bus#A";
167 *busnum = pxb[2];
168 break;
169 case 0x15:
170 s = "Intel 82454NX PXB#1, Bus#B";
171 *busnum = pxb[3];
172 break;
173 }
174 break;
175
176 /* AMD -- vendor 0x1022 */
177 case 0x30001022:
178 s = "AMD Elan SC520 host to PCI bridge";
179 #ifdef CPU_ELAN
180 init_AMD_Elan_sc520();
181 #else
182 printf(
183 "*** WARNING: missing CPU_ELAN -- timekeeping may be wrong\n");
184 #endif
185 break;
186 case 0x70061022:
187 s = "AMD-751 host to PCI bridge";
188 break;
189 case 0x700e1022:
190 s = "AMD-761 host to PCI bridge";
191 break;
192
193 /* SiS -- vendor 0x1039 */
194 case 0x04961039:
195 s = "SiS 85c496";
196 break;
197 case 0x04061039:
198 s = "SiS 85c501";
199 break;
200 case 0x06011039:
201 s = "SiS 85c601";
202 break;
203 case 0x55911039:
204 s = "SiS 5591 host to PCI bridge";
205 break;
206 case 0x00011039:
207 s = "SiS 5591 host to AGP bridge";
208 break;
209
210 /* VLSI -- vendor 0x1004 */
211 case 0x00051004:
212 s = "VLSI 82C592 Host to PCI bridge";
213 break;
214
215 /* XXX Here is MVP3, I got the datasheet but NO M/B to test it */
216 /* totally. Please let me know if anything wrong. -F */
217 /* XXX need info on the MVP3 -- any takers? */
218 case 0x05981106:
219 s = "VIA 82C598MVP (Apollo MVP3) host bridge";
220 break;
221
222 /* AcerLabs -- vendor 0x10b9 */
223 /* Funny : The datasheet told me vendor id is "10b8",sub-vendor */
224 /* id is '10b9" but the register always shows "10b9". -Foxfair */
225 case 0x154110b9:
226 s = "AcerLabs M1541 (Aladdin-V) PCI host bridge";
227 break;
228
229 /* OPTi -- vendor 0x1045 */
230 case 0xc7011045:
231 s = "OPTi 82C700 host to PCI bridge";
232 break;
233 case 0xc8221045:
234 s = "OPTi 82C822 host to PCI Bridge";
235 break;
236
237 /* ServerWorks -- vendor 0x1166 */
238 case 0x00051166:
239 s = "ServerWorks NB6536 2.0HE host to PCI bridge";
240 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
241 break;
242
243 case 0x00061166:
244 /* FALLTHROUGH */
245 case 0x00081166:
246 /* FALLTHROUGH */
247 case 0x02011166:
248 /* FALLTHROUGH */
249 case 0x010f1014: /* IBM re-badged ServerWorks chipset */
250 s = "ServerWorks host to PCI bridge";
251 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
252 break;
253
254 case 0x00091166:
255 s = "ServerWorks NB6635 3.0LE host to PCI bridge";
256 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
257 break;
258
259 case 0x00101166:
260 s = "ServerWorks CIOB30 host to PCI bridge";
261 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
262 break;
263
264 case 0x00111166:
265 /* FALLTHROUGH */
266 case 0x03021014: /* IBM re-badged ServerWorks chipset */
267 s = "ServerWorks CMIC-HE host to PCI-X bridge";
268 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
269 break;
270
271 /* XXX unknown chipset, but working */
272 case 0x00171166:
273 /* FALLTHROUGH */
274 case 0x01011166:
275 s = "ServerWorks host to PCI bridge(unknown chipset)";
276 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
277 break;
278
279 /* Integrated Micro Solutions -- vendor 0x10e0 */
280 case 0x884910e0:
281 s = "Integrated Micro Solutions VL Bridge";
282 break;
283
284 default:
285 if (class == PCIC_BRIDGE && subclass == PCIS_BRIDGE_HOST)
286 s = "Host to PCI bridge";
287 break;
288 }
289
290 return s;
291 }
292
293 /*
294 * Scan the first pci bus for host-pci bridges and add pcib instances
295 * to the nexus for each bridge.
296 */
297 static void
298 legacy_pcib_identify(driver_t *driver, device_t parent)
299 {
300 int bus, slot, func;
301 u_int8_t hdrtype;
302 int found = 0;
303 int pcifunchigh;
304 int found824xx = 0;
305 int found_orion = 0;
306 device_t child;
307 devclass_t pci_devclass;
308
309 if (pci_cfgregopen() == 0)
310 return;
311 /*
312 * Check to see if we haven't already had a PCI bus added
313 * via some other means. If we have, bail since otherwise
314 * we're going to end up duplicating it.
315 */
316 if ((pci_devclass = devclass_find("pci")) &&
317 devclass_get_device(pci_devclass, 0))
318 return;
319
320
321 bus = 0;
322 retry:
323 for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
324 func = 0;
325 hdrtype = legacy_pcib_read_config(0, bus, slot, func,
326 PCIR_HDRTYPE, 1);
327 /*
328 * When enumerating bus devices, the standard says that
329 * one should check the header type and ignore the slots whose
330 * header types that the software doesn't know about. We use
331 * this to filter out devices.
332 */
333 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
334 continue;
335 if ((hdrtype & PCIM_MFDEV) &&
336 (!found_orion || hdrtype != 0xff))
337 pcifunchigh = PCI_FUNCMAX;
338 else
339 pcifunchigh = 0;
340 for (func = 0; func <= pcifunchigh; func++) {
341 /*
342 * Read the IDs and class from the device.
343 */
344 u_int32_t id;
345 u_int8_t class, subclass, busnum;
346 const char *s;
347 device_t *devs;
348 int ndevs, i;
349
350 id = legacy_pcib_read_config(0, bus, slot, func,
351 PCIR_DEVVENDOR, 4);
352 if (id == -1)
353 continue;
354 class = legacy_pcib_read_config(0, bus, slot, func,
355 PCIR_CLASS, 1);
356 subclass = legacy_pcib_read_config(0, bus, slot, func,
357 PCIR_SUBCLASS, 1);
358
359 s = legacy_pcib_is_host_bridge(bus, slot, func,
360 id, class, subclass,
361 &busnum);
362 if (s == NULL)
363 continue;
364
365 /*
366 * Check to see if the physical bus has already
367 * been seen. Eg: hybrid 32 and 64 bit host
368 * bridges to the same logical bus.
369 */
370 if (device_get_children(parent, &devs, &ndevs) == 0) {
371 for (i = 0; s != NULL && i < ndevs; i++) {
372 if (strcmp(device_get_name(devs[i]),
373 "pcib") != 0)
374 continue;
375 if (legacy_get_pcibus(devs[i]) == busnum)
376 s = NULL;
377 }
378 free(devs, M_TEMP);
379 }
380
381 if (s == NULL)
382 continue;
383 /*
384 * Add at priority 100 to make sure we
385 * go after any motherboard resources
386 */
387 child = BUS_ADD_CHILD(parent, 100,
388 "pcib", busnum);
389 device_set_desc(child, s);
390 legacy_set_pcibus(child, busnum);
391
392 found = 1;
393 if (id == 0x12258086)
394 found824xx = 1;
395 if (id == 0x84c48086)
396 found_orion = 1;
397 }
398 }
399 if (found824xx && bus == 0) {
400 bus++;
401 goto retry;
402 }
403
404 /*
405 * Make sure we add at least one bridge since some old
406 * hardware doesn't actually have a host-pci bridge device.
407 * Note that pci_cfgregopen() thinks we have PCI devices..
408 */
409 if (!found) {
410 if (bootverbose)
411 printf(
412 "legacy_pcib_identify: no bridge found, adding pcib0 anyway\n");
413 child = BUS_ADD_CHILD(parent, 100, "pcib", 0);
414 legacy_set_pcibus(child, 0);
415 }
416 }
417
418 static int
419 legacy_pcib_probe(device_t dev)
420 {
421
422 if (pci_cfgregopen() == 0)
423 return ENXIO;
424 return -100;
425 }
426
427 static int
428 legacy_pcib_attach(device_t dev)
429 {
430 device_t pir;
431 int bus;
432
433 /*
434 * Look for a PCI BIOS interrupt routing table as that will be
435 * our method of routing interrupts if we have one.
436 */
437 bus = pcib_get_bus(dev);
438 if (pci_pir_probe(bus, 0)) {
439 pir = BUS_ADD_CHILD(device_get_parent(dev), 0, "pir", 0);
440 if (pir != NULL)
441 device_probe_and_attach(pir);
442 }
443 device_add_child(dev, "pci", bus);
444 return bus_generic_attach(dev);
445 }
446
447 int
448 legacy_pcib_read_ivar(device_t dev, device_t child, int which,
449 uintptr_t *result)
450 {
451
452 switch (which) {
453 case PCIB_IVAR_BUS:
454 *result = legacy_get_pcibus(dev);
455 return 0;
456 }
457 return ENOENT;
458 }
459
460 int
461 legacy_pcib_write_ivar(device_t dev, device_t child, int which,
462 uintptr_t value)
463 {
464
465 switch (which) {
466 case PCIB_IVAR_BUS:
467 legacy_set_pcibus(dev, value);
468 return 0;
469 }
470 return ENOENT;
471 }
472
473 SYSCTL_DECL(_hw_pci);
474
475 static unsigned long legacy_host_mem_start = 0x80000000;
476 TUNABLE_ULONG("hw.pci.host_mem_start", &legacy_host_mem_start);
477 SYSCTL_ULONG(_hw_pci, OID_AUTO, host_mem_start, CTLFLAG_RDTUN,
478 &legacy_host_mem_start, 0x80000000,
479 "Limit the host bridge memory to being above this address. Must be\n\
480 set at boot via a tunable.");
481
482 static struct resource *
483 legacy_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
484 u_long start, u_long end, u_long count, u_int flags)
485 {
486 /*
487 * If no memory preference is given, use upper 32MB slot most
488 * bioses use for their memory window. Typically other bridges
489 * before us get in the way to assert their preferences on memory.
490 * Hardcoding like this sucks, so a more MD/MI way needs to be
491 * found to do it. This is typically only used on older laptops
492 * that don't have pci busses behind pci bridge, so assuming > 32MB
493 * is liekly OK.
494 *
495 * However, this can cause problems for other chipsets, so we make
496 * this tunable by hw.pci.host_mem_start.
497 */
498 if (type == SYS_RES_MEMORY && start == 0UL && end == ~0UL)
499 start = legacy_host_mem_start;
500 return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
501 count, flags));
502 }
503
504 static device_method_t legacy_pcib_methods[] = {
505 /* Device interface */
506 DEVMETHOD(device_identify, legacy_pcib_identify),
507 DEVMETHOD(device_probe, legacy_pcib_probe),
508 DEVMETHOD(device_attach, legacy_pcib_attach),
509 DEVMETHOD(device_shutdown, bus_generic_shutdown),
510 DEVMETHOD(device_suspend, bus_generic_suspend),
511 DEVMETHOD(device_resume, bus_generic_resume),
512
513 /* Bus interface */
514 DEVMETHOD(bus_print_child, bus_generic_print_child),
515 DEVMETHOD(bus_read_ivar, legacy_pcib_read_ivar),
516 DEVMETHOD(bus_write_ivar, legacy_pcib_write_ivar),
517 DEVMETHOD(bus_alloc_resource, legacy_pcib_alloc_resource),
518 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
519 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
520 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
521 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
522 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
523
524 /* pcib interface */
525 DEVMETHOD(pcib_maxslots, legacy_pcib_maxslots),
526 DEVMETHOD(pcib_read_config, legacy_pcib_read_config),
527 DEVMETHOD(pcib_write_config, legacy_pcib_write_config),
528 DEVMETHOD(pcib_route_interrupt, pcibios_pcib_route_interrupt),
529
530 { 0, 0 }
531 };
532
533 static driver_t legacy_pcib_driver = {
534 "pcib",
535 legacy_pcib_methods,
536 1,
537 };
538
539 DRIVER_MODULE(pcib, legacy, legacy_pcib_driver, pcib_devclass, 0, 0);
540
541
542 /*
543 * Provide a device to "eat" the host->pci bridges that we dug up above
544 * and stop them showing up twice on the probes. This also stops them
545 * showing up as 'none' in pciconf -l.
546 */
547 static int
548 pci_hostb_probe(device_t dev)
549 {
550 u_int32_t id;
551
552 id = pci_get_devid(dev);
553
554 switch (id) {
555
556 /* VIA VT82C596 Power Managment Function */
557 case 0x30501106:
558 return ENXIO;
559
560 default:
561 break;
562 }
563
564 if (pci_get_class(dev) == PCIC_BRIDGE &&
565 pci_get_subclass(dev) == PCIS_BRIDGE_HOST) {
566 device_set_desc(dev, "Host to PCI bridge");
567 device_quiet(dev);
568 return -10000;
569 }
570 return ENXIO;
571 }
572
573 static int
574 pci_hostb_attach(device_t dev)
575 {
576
577 return 0;
578 }
579
580 static device_method_t pci_hostb_methods[] = {
581 /* Device interface */
582 DEVMETHOD(device_probe, pci_hostb_probe),
583 DEVMETHOD(device_attach, pci_hostb_attach),
584 DEVMETHOD(device_shutdown, bus_generic_shutdown),
585 DEVMETHOD(device_suspend, bus_generic_suspend),
586 DEVMETHOD(device_resume, bus_generic_resume),
587
588 { 0, 0 }
589 };
590 static driver_t pci_hostb_driver = {
591 "hostb",
592 pci_hostb_methods,
593 1,
594 };
595 static devclass_t pci_hostb_devclass;
596
597 DRIVER_MODULE(hostb, pci, pci_hostb_driver, pci_hostb_devclass, 0, 0);
598
599
600 /*
601 * Install placeholder to claim the resources owned by the
602 * PCI bus interface. This could be used to extract the
603 * config space registers in the extreme case where the PnP
604 * ID is available and the PCI BIOS isn't, but for now we just
605 * eat the PnP ID and do nothing else.
606 *
607 * XXX we should silence this probe, as it will generally confuse
608 * people.
609 */
610 static struct isa_pnp_id pcibus_pnp_ids[] = {
611 { 0x030ad041 /* PNP0A03 */, "PCI Bus" },
612 { 0 }
613 };
614
615 static int
616 pcibus_pnp_probe(device_t dev)
617 {
618 int result;
619
620 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, pcibus_pnp_ids)) <= 0)
621 device_quiet(dev);
622 return(result);
623 }
624
625 static int
626 pcibus_pnp_attach(device_t dev)
627 {
628 return(0);
629 }
630
631 static device_method_t pcibus_pnp_methods[] = {
632 /* Device interface */
633 DEVMETHOD(device_probe, pcibus_pnp_probe),
634 DEVMETHOD(device_attach, pcibus_pnp_attach),
635 DEVMETHOD(device_detach, bus_generic_detach),
636 DEVMETHOD(device_shutdown, bus_generic_shutdown),
637 DEVMETHOD(device_suspend, bus_generic_suspend),
638 DEVMETHOD(device_resume, bus_generic_resume),
639 { 0, 0 }
640 };
641
642 static driver_t pcibus_pnp_driver = {
643 "pcibus_pnp",
644 pcibus_pnp_methods,
645 1, /* no softc */
646 };
647
648 static devclass_t pcibus_pnp_devclass;
649
650 DRIVER_MODULE(pcibus_pnp, isa, pcibus_pnp_driver, pcibus_pnp_devclass, 0, 0);
651
652
653 /*
654 * Provide a PCI-PCI bridge driver for PCI busses behind PCI-PCI bridges
655 * that appear in the PCIBIOS Interrupt Routing Table to use the routing
656 * table for interrupt routing when possible.
657 */
658 static int pcibios_pcib_probe(device_t bus);
659
660 static device_method_t pcibios_pcib_pci_methods[] = {
661 /* Device interface */
662 DEVMETHOD(device_probe, pcibios_pcib_probe),
663 DEVMETHOD(device_attach, pcib_attach),
664 DEVMETHOD(device_shutdown, bus_generic_shutdown),
665 DEVMETHOD(device_suspend, bus_generic_suspend),
666 DEVMETHOD(device_resume, bus_generic_resume),
667
668 /* Bus interface */
669 DEVMETHOD(bus_print_child, bus_generic_print_child),
670 DEVMETHOD(bus_read_ivar, pcib_read_ivar),
671 DEVMETHOD(bus_write_ivar, pcib_write_ivar),
672 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource),
673 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
674 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
675 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
676 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
677 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
678
679 /* pcib interface */
680 DEVMETHOD(pcib_maxslots, pcib_maxslots),
681 DEVMETHOD(pcib_read_config, pcib_read_config),
682 DEVMETHOD(pcib_write_config, pcib_write_config),
683 DEVMETHOD(pcib_route_interrupt, pcibios_pcib_route_interrupt),
684
685 {0, 0}
686 };
687
688 static driver_t pcibios_pcib_driver = {
689 "pcib",
690 pcibios_pcib_pci_methods,
691 sizeof(struct pcib_softc),
692 };
693
694 DRIVER_MODULE(pcibios_pcib, pci, pcibios_pcib_driver, pcib_devclass, 0, 0);
695
696 static int
697 pcibios_pcib_probe(device_t dev)
698 {
699 int bus;
700
701 if ((pci_get_class(dev) != PCIC_BRIDGE) ||
702 (pci_get_subclass(dev) != PCIS_BRIDGE_PCI))
703 return (ENXIO);
704 bus = pci_read_config(dev, PCIR_SECBUS_1, 1);
705 if (bus == 0)
706 return (ENXIO);
707 if (!pci_pir_probe(bus, 1))
708 return (ENXIO);
709 device_set_desc(dev, "PCIBIOS PCI-PCI bridge");
710 return (-2000);
711 }
712
713 static int
714 pcibios_pcib_route_interrupt(device_t pcib, device_t dev, int pin)
715 {
716 return (pci_pir_route_interrupt(pci_get_bus(dev), pci_get_slot(dev),
717 pci_get_function(dev), pin));
718 }
Cache object: 07efcab000c8f73064255ebb7327e01f
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