The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/i386/pci/pci_bus.c

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    1 /*-
    2  * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice unmodified, this list of conditions, and the following
   10  *    disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  *
   15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   25  */
   26 
   27 #include <sys/cdefs.h>
   28 __FBSDID("$FreeBSD: releng/6.3/sys/i386/pci/pci_bus.c 171855 2007-08-15 20:56:10Z jhb $");
   29 
   30 #include "opt_cpu.h"
   31 
   32 #include <sys/param.h>
   33 #include <sys/systm.h>
   34 #include <sys/bus.h>
   35 #include <sys/kernel.h>
   36 #include <sys/malloc.h>
   37 #include <sys/module.h>
   38 #include <sys/sysctl.h>
   39 
   40 #include <dev/pci/pcivar.h>
   41 #include <dev/pci/pcireg.h>
   42 #include <dev/pci/pcib_private.h>
   43 #include <isa/isavar.h>
   44 #ifdef CPU_ELAN
   45 #include <machine/md_var.h>
   46 #endif
   47 #include <machine/legacyvar.h>
   48 #include <machine/pci_cfgreg.h>
   49 #include <machine/resource.h>
   50 
   51 #include "pcib_if.h"
   52 
   53 static int      pcibios_pcib_route_interrupt(device_t pcib, device_t dev,
   54     int pin);
   55 
   56 int
   57 legacy_pcib_maxslots(device_t dev)
   58 {
   59         return 31;
   60 }
   61 
   62 /* read configuration space register */
   63 
   64 u_int32_t
   65 legacy_pcib_read_config(device_t dev, int bus, int slot, int func,
   66                         int reg, int bytes)
   67 {
   68         return(pci_cfgregread(bus, slot, func, reg, bytes));
   69 }
   70 
   71 /* write configuration space register */
   72 
   73 void
   74 legacy_pcib_write_config(device_t dev, int bus, int slot, int func,
   75                          int reg, u_int32_t data, int bytes)
   76 {
   77         pci_cfgregwrite(bus, slot, func, reg, data, bytes);
   78 }
   79 
   80 /* Pass MSI requests up to the nexus. */
   81 
   82 static int
   83 legacy_pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount,
   84     int *irqs)
   85 {
   86         device_t bus;
   87 
   88         bus = device_get_parent(pcib);
   89         return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount,
   90             irqs));
   91 }
   92 
   93 static int
   94 legacy_pcib_alloc_msix(device_t pcib, device_t dev, int *irq)
   95 {
   96         device_t bus;
   97 
   98         bus = device_get_parent(pcib);
   99         return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq));
  100 }
  101 
  102 static int
  103 legacy_pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr,
  104     uint32_t *data)
  105 {
  106         device_t bus;
  107 
  108         bus = device_get_parent(pcib);
  109         return (PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data));
  110 }
  111 
  112 static const char *
  113 legacy_pcib_is_host_bridge(int bus, int slot, int func,
  114                           uint32_t id, uint8_t class, uint8_t subclass,
  115                           uint8_t *busnum)
  116 {
  117         const char *s = NULL;
  118         static uint8_t pxb[4];  /* hack for 450nx */
  119 
  120         *busnum = 0;
  121 
  122         switch (id) {
  123         case 0x12258086:
  124                 s = "Intel 824?? host to PCI bridge";
  125                 /* XXX This is a guess */
  126                 /* *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x41, 1); */
  127                 *busnum = bus;
  128                 break;
  129         case 0x71208086:
  130                 s = "Intel 82810 (i810 GMCH) Host To Hub bridge";
  131                 break;
  132         case 0x71228086:
  133                 s = "Intel 82810-DC100 (i810-DC100 GMCH) Host To Hub bridge";
  134                 break;
  135         case 0x71248086:
  136                 s = "Intel 82810E (i810E GMCH) Host To Hub bridge";
  137                 break;
  138         case 0x11308086:
  139                 s = "Intel 82815 (i815 GMCH) Host To Hub bridge";
  140                 break;
  141         case 0x71808086:
  142                 s = "Intel 82443LX (440 LX) host to PCI bridge";
  143                 break;
  144         case 0x71908086:
  145                 s = "Intel 82443BX (440 BX) host to PCI bridge";
  146                 break;
  147         case 0x71928086:
  148                 s = "Intel 82443BX host to PCI bridge (AGP disabled)";
  149                 break;
  150         case 0x71948086:
  151                 s = "Intel 82443MX host to PCI bridge";
  152                 break;
  153         case 0x71a08086:
  154                 s = "Intel 82443GX host to PCI bridge";
  155                 break;
  156         case 0x71a18086:
  157                 s = "Intel 82443GX host to AGP bridge";
  158                 break;
  159         case 0x71a28086:
  160                 s = "Intel 82443GX host to PCI bridge (AGP disabled)";
  161                 break;
  162         case 0x84c48086:
  163                 s = "Intel 82454KX/GX (Orion) host to PCI bridge";
  164                 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x4a, 1);
  165                 break;
  166         case 0x84ca8086:
  167                 /*
  168                  * For the 450nx chipset, there is a whole bundle of
  169                  * things pretending to be host bridges. The MIOC will
  170                  * be seen first and isn't really a pci bridge (the
  171                  * actual busses are attached to the PXB's). We need to
  172                  * read the registers of the MIOC to figure out the
  173                  * bus numbers for the PXB channels.
  174                  *
  175                  * Since the MIOC doesn't have a pci bus attached, we
  176                  * pretend it wasn't there.
  177                  */
  178                 pxb[0] = legacy_pcib_read_config(0, bus, slot, func,
  179                                                 0xd0, 1); /* BUSNO[0] */
  180                 pxb[1] = legacy_pcib_read_config(0, bus, slot, func,
  181                                                 0xd1, 1) + 1;   /* SUBA[0]+1 */
  182                 pxb[2] = legacy_pcib_read_config(0, bus, slot, func,
  183                                                 0xd3, 1); /* BUSNO[1] */
  184                 pxb[3] = legacy_pcib_read_config(0, bus, slot, func,
  185                                                 0xd4, 1) + 1;   /* SUBA[1]+1 */
  186                 return NULL;
  187         case 0x84cb8086:
  188                 switch (slot) {
  189                 case 0x12:
  190                         s = "Intel 82454NX PXB#0, Bus#A";
  191                         *busnum = pxb[0];
  192                         break;
  193                 case 0x13:
  194                         s = "Intel 82454NX PXB#0, Bus#B";
  195                         *busnum = pxb[1];
  196                         break;
  197                 case 0x14:
  198                         s = "Intel 82454NX PXB#1, Bus#A";
  199                         *busnum = pxb[2];
  200                         break;
  201                 case 0x15:
  202                         s = "Intel 82454NX PXB#1, Bus#B";
  203                         *busnum = pxb[3];
  204                         break;
  205                 }
  206                 break;
  207 
  208                 /* AMD -- vendor 0x1022 */
  209         case 0x30001022:
  210                 s = "AMD Elan SC520 host to PCI bridge";
  211 #ifdef CPU_ELAN
  212                 init_AMD_Elan_sc520();
  213 #else
  214                 printf(
  215 "*** WARNING: missing CPU_ELAN -- timekeeping may be wrong\n");
  216 #endif
  217                 break;
  218         case 0x70061022:
  219                 s = "AMD-751 host to PCI bridge";
  220                 break;
  221         case 0x700e1022:
  222                 s = "AMD-761 host to PCI bridge";
  223                 break;
  224 
  225                 /* SiS -- vendor 0x1039 */
  226         case 0x04961039:
  227                 s = "SiS 85c496";
  228                 break;
  229         case 0x04061039:
  230                 s = "SiS 85c501";
  231                 break;
  232         case 0x06011039:
  233                 s = "SiS 85c601";
  234                 break;
  235         case 0x55911039:
  236                 s = "SiS 5591 host to PCI bridge";
  237                 break;
  238         case 0x00011039:
  239                 s = "SiS 5591 host to AGP bridge";
  240                 break;
  241 
  242                 /* VLSI -- vendor 0x1004 */
  243         case 0x00051004:
  244                 s = "VLSI 82C592 Host to PCI bridge";
  245                 break;
  246 
  247                 /* XXX Here is MVP3, I got the datasheet but NO M/B to test it  */
  248                 /* totally. Please let me know if anything wrong.            -F */
  249                 /* XXX need info on the MVP3 -- any takers? */
  250         case 0x05981106:
  251                 s = "VIA 82C598MVP (Apollo MVP3) host bridge";
  252                 break;
  253 
  254                 /* AcerLabs -- vendor 0x10b9 */
  255                 /* Funny : The datasheet told me vendor id is "10b8",sub-vendor */
  256                 /* id is '10b9" but the register always shows "10b9". -Foxfair  */
  257         case 0x154110b9:
  258                 s = "AcerLabs M1541 (Aladdin-V) PCI host bridge";
  259                 break;
  260 
  261                 /* OPTi -- vendor 0x1045 */
  262         case 0xc7011045:
  263                 s = "OPTi 82C700 host to PCI bridge";
  264                 break;
  265         case 0xc8221045:
  266                 s = "OPTi 82C822 host to PCI Bridge";
  267                 break;
  268 
  269                 /* ServerWorks -- vendor 0x1166 */
  270         case 0x00051166:
  271                 s = "ServerWorks NB6536 2.0HE host to PCI bridge";
  272                 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
  273                 break;
  274 
  275         case 0x00061166:
  276                 /* FALLTHROUGH */
  277         case 0x00081166:
  278                 /* FALLTHROUGH */
  279         case 0x02011166:
  280                 /* FALLTHROUGH */
  281         case 0x010f1014: /* IBM re-badged ServerWorks chipset */
  282                 s = "ServerWorks host to PCI bridge";
  283                 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
  284                 break;
  285 
  286         case 0x00091166:
  287                 s = "ServerWorks NB6635 3.0LE host to PCI bridge";
  288                 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
  289                 break;
  290 
  291         case 0x00101166:
  292                 s = "ServerWorks CIOB30 host to PCI bridge";
  293                 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
  294                 break;
  295 
  296         case 0x00111166:
  297                 /* FALLTHROUGH */
  298         case 0x03021014: /* IBM re-badged ServerWorks chipset */
  299                 s = "ServerWorks CMIC-HE host to PCI-X bridge";
  300                 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
  301                 break;
  302 
  303                 /* XXX unknown chipset, but working */
  304         case 0x00171166:
  305                 /* FALLTHROUGH */
  306         case 0x01011166:
  307                 s = "ServerWorks host to PCI bridge(unknown chipset)";
  308                 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
  309                 break;
  310 
  311                 /* Compaq/HP -- vendor 0x0e11 */
  312         case 0x60100e11:
  313                 s = "Compaq/HP Model 6010 HotPlug PCI Bridge";
  314                 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0xc8, 1);
  315                 break;
  316 
  317                 /* Integrated Micro Solutions -- vendor 0x10e0 */
  318         case 0x884910e0:
  319                 s = "Integrated Micro Solutions VL Bridge";
  320                 break;
  321 
  322         default:
  323                 if (class == PCIC_BRIDGE && subclass == PCIS_BRIDGE_HOST)
  324                         s = "Host to PCI bridge";
  325                 break;
  326         }
  327 
  328         return s;
  329 }
  330 
  331 /*
  332  * Scan the first pci bus for host-pci bridges and add pcib instances
  333  * to the nexus for each bridge.
  334  */
  335 static void
  336 legacy_pcib_identify(driver_t *driver, device_t parent)
  337 {
  338         int bus, slot, func;
  339         u_int8_t  hdrtype;
  340         int found = 0;
  341         int pcifunchigh;
  342         int found824xx = 0;
  343         int found_orion = 0;
  344         device_t child;
  345         devclass_t pci_devclass;
  346 
  347         if (pci_cfgregopen() == 0)
  348                 return;
  349         /*
  350          * Check to see if we haven't already had a PCI bus added
  351          * via some other means.  If we have, bail since otherwise
  352          * we're going to end up duplicating it.
  353          */
  354         if ((pci_devclass = devclass_find("pci")) &&
  355                 devclass_get_device(pci_devclass, 0))
  356                 return;
  357 
  358 
  359         bus = 0;
  360  retry:
  361         for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
  362                 func = 0;
  363                 hdrtype = legacy_pcib_read_config(0, bus, slot, func,
  364                                                  PCIR_HDRTYPE, 1);
  365                 /*
  366                  * When enumerating bus devices, the standard says that
  367                  * one should check the header type and ignore the slots whose
  368                  * header types that the software doesn't know about.  We use
  369                  * this to filter out devices.
  370                  */
  371                 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
  372                         continue;
  373                 if ((hdrtype & PCIM_MFDEV) &&
  374                     (!found_orion || hdrtype != 0xff))
  375                         pcifunchigh = PCI_FUNCMAX;
  376                 else
  377                         pcifunchigh = 0;
  378                 for (func = 0; func <= pcifunchigh; func++) {
  379                         /*
  380                          * Read the IDs and class from the device.
  381                          */
  382                         u_int32_t id;
  383                         u_int8_t class, subclass, busnum;
  384                         const char *s;
  385                         device_t *devs;
  386                         int ndevs, i;
  387 
  388                         id = legacy_pcib_read_config(0, bus, slot, func,
  389                                                     PCIR_DEVVENDOR, 4);
  390                         if (id == -1)
  391                                 continue;
  392                         class = legacy_pcib_read_config(0, bus, slot, func,
  393                                                        PCIR_CLASS, 1);
  394                         subclass = legacy_pcib_read_config(0, bus, slot, func,
  395                                                           PCIR_SUBCLASS, 1);
  396 
  397                         s = legacy_pcib_is_host_bridge(bus, slot, func,
  398                                                       id, class, subclass,
  399                                                       &busnum);
  400                         if (s == NULL)
  401                                 continue;
  402 
  403                         /*
  404                          * Check to see if the physical bus has already
  405                          * been seen.  Eg: hybrid 32 and 64 bit host
  406                          * bridges to the same logical bus.
  407                          */
  408                         if (device_get_children(parent, &devs, &ndevs) == 0) {
  409                                 for (i = 0; s != NULL && i < ndevs; i++) {
  410                                         if (strcmp(device_get_name(devs[i]),
  411                                             "pcib") != 0)
  412                                                 continue;
  413                                         if (legacy_get_pcibus(devs[i]) == busnum)
  414                                                 s = NULL;
  415                                 }
  416                                 free(devs, M_TEMP);
  417                         }
  418 
  419                         if (s == NULL)
  420                                 continue;
  421                         /*
  422                          * Add at priority 100 to make sure we
  423                          * go after any motherboard resources
  424                          */
  425                         child = BUS_ADD_CHILD(parent, 100,
  426                                               "pcib", busnum);
  427                         device_set_desc(child, s);
  428                         legacy_set_pcibus(child, busnum);
  429 
  430                         found = 1;
  431                         if (id == 0x12258086)
  432                                 found824xx = 1;
  433                         if (id == 0x84c48086)
  434                                 found_orion = 1;
  435                 }
  436         }
  437         if (found824xx && bus == 0) {
  438                 bus++;
  439                 goto retry;
  440         }
  441 
  442         /*
  443          * Make sure we add at least one bridge since some old
  444          * hardware doesn't actually have a host-pci bridge device.
  445          * Note that pci_cfgregopen() thinks we have PCI devices..
  446          */
  447         if (!found) {
  448                 if (bootverbose)
  449                         printf(
  450         "legacy_pcib_identify: no bridge found, adding pcib0 anyway\n");
  451                 child = BUS_ADD_CHILD(parent, 100, "pcib", 0);
  452                 legacy_set_pcibus(child, 0);
  453         }
  454 }
  455 
  456 static int
  457 legacy_pcib_probe(device_t dev)
  458 {
  459 
  460         if (pci_cfgregopen() == 0)
  461                 return ENXIO;
  462         return -100;
  463 }
  464 
  465 static int
  466 legacy_pcib_attach(device_t dev)
  467 {
  468         device_t pir;
  469         int bus;
  470 
  471         /*
  472          * Look for a PCI BIOS interrupt routing table as that will be
  473          * our method of routing interrupts if we have one.
  474          */
  475         bus = pcib_get_bus(dev);
  476         if (pci_pir_probe(bus, 0)) {
  477                 pir = BUS_ADD_CHILD(device_get_parent(dev), 0, "pir", 0);
  478                 if (pir != NULL)
  479                         device_probe_and_attach(pir);
  480         }
  481         device_add_child(dev, "pci", bus);
  482         return bus_generic_attach(dev);
  483 }
  484 
  485 int
  486 legacy_pcib_read_ivar(device_t dev, device_t child, int which,
  487     uintptr_t *result)
  488 {
  489 
  490         switch (which) {
  491         case  PCIB_IVAR_BUS:
  492                 *result = legacy_get_pcibus(dev);
  493                 return 0;
  494         }
  495         return ENOENT;
  496 }
  497 
  498 int
  499 legacy_pcib_write_ivar(device_t dev, device_t child, int which,
  500     uintptr_t value)
  501 {
  502 
  503         switch (which) {
  504         case  PCIB_IVAR_BUS:
  505                 legacy_set_pcibus(dev, value);
  506                 return 0;
  507         }
  508         return ENOENT;
  509 }
  510 
  511 SYSCTL_DECL(_hw_pci);
  512 
  513 static unsigned long legacy_host_mem_start = 0x80000000;
  514 TUNABLE_ULONG("hw.pci.host_mem_start", &legacy_host_mem_start);
  515 SYSCTL_ULONG(_hw_pci, OID_AUTO, host_mem_start, CTLFLAG_RDTUN,
  516     &legacy_host_mem_start, 0x80000000,
  517     "Limit the host bridge memory to being above this address.  Must be\n\
  518 set at boot via a tunable.");
  519 
  520 struct resource *
  521 legacy_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
  522     u_long start, u_long end, u_long count, u_int flags)
  523 {
  524     /*
  525      * If no memory preference is given, use upper 32MB slot most
  526      * bioses use for their memory window.  Typically other bridges
  527      * before us get in the way to assert their preferences on memory.
  528      * Hardcoding like this sucks, so a more MD/MI way needs to be
  529      * found to do it.  This is typically only used on older laptops
  530      * that don't have pci busses behind pci bridge, so assuming > 32MB
  531      * is liekly OK.
  532      *
  533      * However, this can cause problems for other chipsets, so we make
  534      * this tunable by hw.pci.host_mem_start.
  535      */
  536     if (type == SYS_RES_MEMORY && start == 0UL && end == ~0UL)
  537         start = legacy_host_mem_start;
  538     if (type == SYS_RES_IOPORT && start == 0UL && end == ~0UL)
  539         start = 0x1000;
  540     return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
  541         count, flags));
  542 }
  543 
  544 static device_method_t legacy_pcib_methods[] = {
  545         /* Device interface */
  546         DEVMETHOD(device_identify,      legacy_pcib_identify),
  547         DEVMETHOD(device_probe,         legacy_pcib_probe),
  548         DEVMETHOD(device_attach,        legacy_pcib_attach),
  549         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
  550         DEVMETHOD(device_suspend,       bus_generic_suspend),
  551         DEVMETHOD(device_resume,        bus_generic_resume),
  552 
  553         /* Bus interface */
  554         DEVMETHOD(bus_print_child,      bus_generic_print_child),
  555         DEVMETHOD(bus_read_ivar,        legacy_pcib_read_ivar),
  556         DEVMETHOD(bus_write_ivar,       legacy_pcib_write_ivar),
  557         DEVMETHOD(bus_alloc_resource,   legacy_pcib_alloc_resource),
  558         DEVMETHOD(bus_release_resource, bus_generic_release_resource),
  559         DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
  560         DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
  561         DEVMETHOD(bus_setup_intr,       bus_generic_setup_intr),
  562         DEVMETHOD(bus_teardown_intr,    bus_generic_teardown_intr),
  563 
  564         /* pcib interface */
  565         DEVMETHOD(pcib_maxslots,        legacy_pcib_maxslots),
  566         DEVMETHOD(pcib_read_config,     legacy_pcib_read_config),
  567         DEVMETHOD(pcib_write_config,    legacy_pcib_write_config),
  568         DEVMETHOD(pcib_route_interrupt, pcibios_pcib_route_interrupt),
  569         DEVMETHOD(pcib_alloc_msi,       legacy_pcib_alloc_msi),
  570         DEVMETHOD(pcib_release_msi,     pcib_release_msi),
  571         DEVMETHOD(pcib_alloc_msix,      legacy_pcib_alloc_msix),
  572         DEVMETHOD(pcib_release_msix,    pcib_release_msix),
  573         DEVMETHOD(pcib_map_msi,         legacy_pcib_map_msi),
  574 
  575         { 0, 0 }
  576 };
  577 
  578 static devclass_t hostb_devclass;
  579 
  580 DEFINE_CLASS_0(pcib, legacy_pcib_driver, legacy_pcib_methods, 1);
  581 DRIVER_MODULE(pcib, legacy, legacy_pcib_driver, hostb_devclass, 0, 0);
  582 
  583 
  584 /*
  585  * Provide a device to "eat" the host->pci bridges that we dug up above
  586  * and stop them showing up twice on the probes.  This also stops them
  587  * showing up as 'none' in pciconf -l.
  588  */
  589 static int
  590 pci_hostb_probe(device_t dev)
  591 {
  592         u_int32_t id;
  593 
  594         id = pci_get_devid(dev);
  595 
  596         switch (id) {
  597 
  598         /* VIA VT82C596 Power Managment Function */
  599         case 0x30501106:
  600                 return ENXIO;
  601 
  602         default:
  603                 break;
  604         }
  605 
  606         if (pci_get_class(dev) == PCIC_BRIDGE &&
  607             pci_get_subclass(dev) == PCIS_BRIDGE_HOST) {
  608                 device_set_desc(dev, "Host to PCI bridge");
  609                 device_quiet(dev);
  610                 return -10000;
  611         }
  612         return ENXIO;
  613 }
  614 
  615 static int
  616 pci_hostb_attach(device_t dev)
  617 {
  618 
  619         return 0;
  620 }
  621 
  622 static device_method_t pci_hostb_methods[] = {
  623         /* Device interface */
  624         DEVMETHOD(device_probe,         pci_hostb_probe),
  625         DEVMETHOD(device_attach,        pci_hostb_attach),
  626         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
  627         DEVMETHOD(device_suspend,       bus_generic_suspend),
  628         DEVMETHOD(device_resume,        bus_generic_resume),
  629 
  630         { 0, 0 }
  631 };
  632 static driver_t pci_hostb_driver = {
  633         "hostb",
  634         pci_hostb_methods,
  635         1,
  636 };
  637 static devclass_t pci_hostb_devclass;
  638 
  639 DRIVER_MODULE(hostb, pci, pci_hostb_driver, pci_hostb_devclass, 0, 0);
  640 
  641 
  642 /*
  643  * Install placeholder to claim the resources owned by the
  644  * PCI bus interface.  This could be used to extract the
  645  * config space registers in the extreme case where the PnP
  646  * ID is available and the PCI BIOS isn't, but for now we just
  647  * eat the PnP ID and do nothing else.
  648  *
  649  * XXX we should silence this probe, as it will generally confuse
  650  * people.
  651  */
  652 static struct isa_pnp_id pcibus_pnp_ids[] = {
  653         { 0x030ad041 /* PNP0A03 */, "PCI Bus" },
  654         { 0 }
  655 };
  656 
  657 static int
  658 pcibus_pnp_probe(device_t dev)
  659 {
  660         int result;
  661 
  662         if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, pcibus_pnp_ids)) <= 0)
  663                 device_quiet(dev);
  664         return(result);
  665 }
  666 
  667 static int
  668 pcibus_pnp_attach(device_t dev)
  669 {
  670         return(0);
  671 }
  672 
  673 static device_method_t pcibus_pnp_methods[] = {
  674         /* Device interface */
  675         DEVMETHOD(device_probe,         pcibus_pnp_probe),
  676         DEVMETHOD(device_attach,        pcibus_pnp_attach),
  677         DEVMETHOD(device_detach,        bus_generic_detach),
  678         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
  679         DEVMETHOD(device_suspend,       bus_generic_suspend),
  680         DEVMETHOD(device_resume,        bus_generic_resume),
  681         { 0, 0 }
  682 };
  683 
  684 static devclass_t pcibus_pnp_devclass;
  685 
  686 DEFINE_CLASS_0(pcibus_pnp, pcibus_pnp_driver, pcibus_pnp_methods, 1);
  687 DRIVER_MODULE(pcibus_pnp, isa, pcibus_pnp_driver, pcibus_pnp_devclass, 0, 0);
  688 
  689 
  690 /*
  691  * Provide a PCI-PCI bridge driver for PCI busses behind PCI-PCI bridges
  692  * that appear in the PCIBIOS Interrupt Routing Table to use the routing
  693  * table for interrupt routing when possible.
  694  */
  695 static int      pcibios_pcib_probe(device_t bus);
  696 
  697 static device_method_t pcibios_pcib_pci_methods[] = {
  698         /* Device interface */
  699         DEVMETHOD(device_probe,         pcibios_pcib_probe),
  700         DEVMETHOD(device_attach,        pcib_attach),
  701         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
  702         DEVMETHOD(device_suspend,       bus_generic_suspend),
  703         DEVMETHOD(device_resume,        bus_generic_resume),
  704 
  705         /* Bus interface */
  706         DEVMETHOD(bus_print_child,      bus_generic_print_child),
  707         DEVMETHOD(bus_read_ivar,        pcib_read_ivar),
  708         DEVMETHOD(bus_write_ivar,       pcib_write_ivar),
  709         DEVMETHOD(bus_alloc_resource,   pcib_alloc_resource),
  710         DEVMETHOD(bus_release_resource, bus_generic_release_resource),
  711         DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
  712         DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
  713         DEVMETHOD(bus_setup_intr,       bus_generic_setup_intr),
  714         DEVMETHOD(bus_teardown_intr,    bus_generic_teardown_intr),
  715 
  716         /* pcib interface */
  717         DEVMETHOD(pcib_maxslots,        pcib_maxslots),
  718         DEVMETHOD(pcib_read_config,     pcib_read_config),
  719         DEVMETHOD(pcib_write_config,    pcib_write_config),
  720         DEVMETHOD(pcib_route_interrupt, pcibios_pcib_route_interrupt),
  721         DEVMETHOD(pcib_alloc_msi,       pcib_alloc_msi),
  722         DEVMETHOD(pcib_release_msi,     pcib_release_msi),
  723         DEVMETHOD(pcib_alloc_msix,      pcib_alloc_msix),
  724         DEVMETHOD(pcib_release_msix,    pcib_release_msix),
  725         DEVMETHOD(pcib_map_msi,         pcib_map_msi),
  726 
  727         {0, 0}
  728 };
  729 
  730 static devclass_t pcib_devclass;
  731 
  732 DEFINE_CLASS_0(pcib, pcibios_pcib_driver, pcibios_pcib_pci_methods,
  733     sizeof(struct pcib_softc));
  734 DRIVER_MODULE(pcibios_pcib, pci, pcibios_pcib_driver, pcib_devclass, 0, 0);
  735 
  736 static int
  737 pcibios_pcib_probe(device_t dev)
  738 {
  739         int bus;
  740 
  741         if ((pci_get_class(dev) != PCIC_BRIDGE) ||
  742             (pci_get_subclass(dev) != PCIS_BRIDGE_PCI))
  743                 return (ENXIO);
  744         bus = pci_read_config(dev, PCIR_SECBUS_1, 1);
  745         if (bus == 0)
  746                 return (ENXIO);
  747         if (!pci_pir_probe(bus, 1))
  748                 return (ENXIO);
  749         device_set_desc(dev, "PCIBIOS PCI-PCI bridge");
  750         return (-2000);
  751 }
  752 
  753 static int
  754 pcibios_pcib_route_interrupt(device_t pcib, device_t dev, int pin)
  755 {
  756         return (pci_pir_route_interrupt(pci_get_bus(dev), pci_get_slot(dev),
  757                 pci_get_function(dev), pin));
  758 }

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