FreeBSD/Linux Kernel Cross Reference
sys/i386/pci/pci_bus.c
1 /*-
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD: releng/8.2/sys/i386/pci/pci_bus.c 216123 2010-12-02 15:58:54Z jhb $");
29
30 #include "opt_cpu.h"
31
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/bus.h>
35 #include <sys/kernel.h>
36 #include <sys/malloc.h>
37 #include <sys/module.h>
38 #include <sys/sysctl.h>
39
40 #include <dev/pci/pcivar.h>
41 #include <dev/pci/pcireg.h>
42 #include <dev/pci/pcib_private.h>
43 #include <isa/isavar.h>
44 #ifdef CPU_ELAN
45 #include <machine/md_var.h>
46 #endif
47 #include <machine/legacyvar.h>
48 #include <machine/pci_cfgreg.h>
49 #include <machine/resource.h>
50
51 #include "pcib_if.h"
52
53 static int pcibios_pcib_route_interrupt(device_t pcib, device_t dev,
54 int pin);
55
56 int
57 legacy_pcib_maxslots(device_t dev)
58 {
59 return 31;
60 }
61
62 /* read configuration space register */
63
64 u_int32_t
65 legacy_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
66 u_int reg, int bytes)
67 {
68 return(pci_cfgregread(bus, slot, func, reg, bytes));
69 }
70
71 /* write configuration space register */
72
73 void
74 legacy_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
75 u_int reg, u_int32_t data, int bytes)
76 {
77 pci_cfgregwrite(bus, slot, func, reg, data, bytes);
78 }
79
80 /* Pass MSI requests up to the nexus. */
81
82 static int
83 legacy_pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount,
84 int *irqs)
85 {
86 device_t bus;
87
88 bus = device_get_parent(pcib);
89 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount,
90 irqs));
91 }
92
93 static int
94 legacy_pcib_alloc_msix(device_t pcib, device_t dev, int *irq)
95 {
96 device_t bus;
97
98 bus = device_get_parent(pcib);
99 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq));
100 }
101
102 static int
103 legacy_pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr,
104 uint32_t *data)
105 {
106 device_t bus;
107
108 bus = device_get_parent(pcib);
109 return (PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data));
110 }
111
112 static const char *
113 legacy_pcib_is_host_bridge(int bus, int slot, int func,
114 uint32_t id, uint8_t class, uint8_t subclass,
115 uint8_t *busnum)
116 {
117 const char *s = NULL;
118 static uint8_t pxb[4]; /* hack for 450nx */
119
120 *busnum = 0;
121
122 switch (id) {
123 case 0x12258086:
124 s = "Intel 824?? host to PCI bridge";
125 /* XXX This is a guess */
126 /* *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x41, 1); */
127 *busnum = bus;
128 break;
129 case 0x71208086:
130 s = "Intel 82810 (i810 GMCH) Host To Hub bridge";
131 break;
132 case 0x71228086:
133 s = "Intel 82810-DC100 (i810-DC100 GMCH) Host To Hub bridge";
134 break;
135 case 0x71248086:
136 s = "Intel 82810E (i810E GMCH) Host To Hub bridge";
137 break;
138 case 0x11308086:
139 s = "Intel 82815 (i815 GMCH) Host To Hub bridge";
140 break;
141 case 0x71808086:
142 s = "Intel 82443LX (440 LX) host to PCI bridge";
143 break;
144 case 0x71908086:
145 s = "Intel 82443BX (440 BX) host to PCI bridge";
146 break;
147 case 0x71928086:
148 s = "Intel 82443BX host to PCI bridge (AGP disabled)";
149 break;
150 case 0x71948086:
151 s = "Intel 82443MX host to PCI bridge";
152 break;
153 case 0x71a08086:
154 s = "Intel 82443GX host to PCI bridge";
155 break;
156 case 0x71a18086:
157 s = "Intel 82443GX host to AGP bridge";
158 break;
159 case 0x71a28086:
160 s = "Intel 82443GX host to PCI bridge (AGP disabled)";
161 break;
162 case 0x84c48086:
163 s = "Intel 82454KX/GX (Orion) host to PCI bridge";
164 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x4a, 1);
165 break;
166 case 0x84ca8086:
167 /*
168 * For the 450nx chipset, there is a whole bundle of
169 * things pretending to be host bridges. The MIOC will
170 * be seen first and isn't really a pci bridge (the
171 * actual busses are attached to the PXB's). We need to
172 * read the registers of the MIOC to figure out the
173 * bus numbers for the PXB channels.
174 *
175 * Since the MIOC doesn't have a pci bus attached, we
176 * pretend it wasn't there.
177 */
178 pxb[0] = legacy_pcib_read_config(0, bus, slot, func,
179 0xd0, 1); /* BUSNO[0] */
180 pxb[1] = legacy_pcib_read_config(0, bus, slot, func,
181 0xd1, 1) + 1; /* SUBA[0]+1 */
182 pxb[2] = legacy_pcib_read_config(0, bus, slot, func,
183 0xd3, 1); /* BUSNO[1] */
184 pxb[3] = legacy_pcib_read_config(0, bus, slot, func,
185 0xd4, 1) + 1; /* SUBA[1]+1 */
186 return NULL;
187 case 0x84cb8086:
188 switch (slot) {
189 case 0x12:
190 s = "Intel 82454NX PXB#0, Bus#A";
191 *busnum = pxb[0];
192 break;
193 case 0x13:
194 s = "Intel 82454NX PXB#0, Bus#B";
195 *busnum = pxb[1];
196 break;
197 case 0x14:
198 s = "Intel 82454NX PXB#1, Bus#A";
199 *busnum = pxb[2];
200 break;
201 case 0x15:
202 s = "Intel 82454NX PXB#1, Bus#B";
203 *busnum = pxb[3];
204 break;
205 }
206 break;
207 case 0x1A308086:
208 s = "Intel 82845 Host to PCI bridge";
209 break;
210
211 /* AMD -- vendor 0x1022 */
212 case 0x30001022:
213 s = "AMD Elan SC520 host to PCI bridge";
214 #ifdef CPU_ELAN
215 init_AMD_Elan_sc520();
216 #else
217 printf(
218 "*** WARNING: missing CPU_ELAN -- timekeeping may be wrong\n");
219 #endif
220 break;
221 case 0x70061022:
222 s = "AMD-751 host to PCI bridge";
223 break;
224 case 0x700e1022:
225 s = "AMD-761 host to PCI bridge";
226 break;
227
228 /* SiS -- vendor 0x1039 */
229 case 0x04961039:
230 s = "SiS 85c496";
231 break;
232 case 0x04061039:
233 s = "SiS 85c501";
234 break;
235 case 0x06011039:
236 s = "SiS 85c601";
237 break;
238 case 0x55911039:
239 s = "SiS 5591 host to PCI bridge";
240 break;
241 case 0x00011039:
242 s = "SiS 5591 host to AGP bridge";
243 break;
244
245 /* VLSI -- vendor 0x1004 */
246 case 0x00051004:
247 s = "VLSI 82C592 Host to PCI bridge";
248 break;
249
250 /* XXX Here is MVP3, I got the datasheet but NO M/B to test it */
251 /* totally. Please let me know if anything wrong. -F */
252 /* XXX need info on the MVP3 -- any takers? */
253 case 0x05981106:
254 s = "VIA 82C598MVP (Apollo MVP3) host bridge";
255 break;
256
257 /* AcerLabs -- vendor 0x10b9 */
258 /* Funny : The datasheet told me vendor id is "10b8",sub-vendor */
259 /* id is '10b9" but the register always shows "10b9". -Foxfair */
260 case 0x154110b9:
261 s = "AcerLabs M1541 (Aladdin-V) PCI host bridge";
262 break;
263
264 /* OPTi -- vendor 0x1045 */
265 case 0xc7011045:
266 s = "OPTi 82C700 host to PCI bridge";
267 break;
268 case 0xc8221045:
269 s = "OPTi 82C822 host to PCI Bridge";
270 break;
271
272 /* ServerWorks -- vendor 0x1166 */
273 case 0x00051166:
274 s = "ServerWorks NB6536 2.0HE host to PCI bridge";
275 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
276 break;
277
278 case 0x00061166:
279 /* FALLTHROUGH */
280 case 0x00081166:
281 /* FALLTHROUGH */
282 case 0x02011166:
283 /* FALLTHROUGH */
284 case 0x010f1014: /* IBM re-badged ServerWorks chipset */
285 s = "ServerWorks host to PCI bridge";
286 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
287 break;
288
289 case 0x00091166:
290 s = "ServerWorks NB6635 3.0LE host to PCI bridge";
291 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
292 break;
293
294 case 0x00101166:
295 s = "ServerWorks CIOB30 host to PCI bridge";
296 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
297 break;
298
299 case 0x00111166:
300 /* FALLTHROUGH */
301 case 0x03021014: /* IBM re-badged ServerWorks chipset */
302 s = "ServerWorks CMIC-HE host to PCI-X bridge";
303 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
304 break;
305
306 /* XXX unknown chipset, but working */
307 case 0x00171166:
308 /* FALLTHROUGH */
309 case 0x01011166:
310 case 0x01101166:
311 case 0x02251166:
312 s = "ServerWorks host to PCI bridge(unknown chipset)";
313 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
314 break;
315
316 /* Compaq/HP -- vendor 0x0e11 */
317 case 0x60100e11:
318 s = "Compaq/HP Model 6010 HotPlug PCI Bridge";
319 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0xc8, 1);
320 break;
321
322 /* Integrated Micro Solutions -- vendor 0x10e0 */
323 case 0x884910e0:
324 s = "Integrated Micro Solutions VL Bridge";
325 break;
326
327 default:
328 if (class == PCIC_BRIDGE && subclass == PCIS_BRIDGE_HOST)
329 s = "Host to PCI bridge";
330 break;
331 }
332
333 return s;
334 }
335
336 /*
337 * Scan the first pci bus for host-pci bridges and add pcib instances
338 * to the nexus for each bridge.
339 */
340 static void
341 legacy_pcib_identify(driver_t *driver, device_t parent)
342 {
343 int bus, slot, func;
344 u_int8_t hdrtype;
345 int found = 0;
346 int pcifunchigh;
347 int found824xx = 0;
348 int found_orion = 0;
349 device_t child;
350 devclass_t pci_devclass;
351
352 if (pci_cfgregopen() == 0)
353 return;
354 /*
355 * Check to see if we haven't already had a PCI bus added
356 * via some other means. If we have, bail since otherwise
357 * we're going to end up duplicating it.
358 */
359 if ((pci_devclass = devclass_find("pci")) &&
360 devclass_get_device(pci_devclass, 0))
361 return;
362
363
364 bus = 0;
365 retry:
366 for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
367 func = 0;
368 hdrtype = legacy_pcib_read_config(0, bus, slot, func,
369 PCIR_HDRTYPE, 1);
370 /*
371 * When enumerating bus devices, the standard says that
372 * one should check the header type and ignore the slots whose
373 * header types that the software doesn't know about. We use
374 * this to filter out devices.
375 */
376 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
377 continue;
378 if ((hdrtype & PCIM_MFDEV) &&
379 (!found_orion || hdrtype != 0xff))
380 pcifunchigh = PCI_FUNCMAX;
381 else
382 pcifunchigh = 0;
383 for (func = 0; func <= pcifunchigh; func++) {
384 /*
385 * Read the IDs and class from the device.
386 */
387 u_int32_t id;
388 u_int8_t class, subclass, busnum;
389 const char *s;
390 device_t *devs;
391 int ndevs, i;
392
393 id = legacy_pcib_read_config(0, bus, slot, func,
394 PCIR_DEVVENDOR, 4);
395 if (id == -1)
396 continue;
397 class = legacy_pcib_read_config(0, bus, slot, func,
398 PCIR_CLASS, 1);
399 subclass = legacy_pcib_read_config(0, bus, slot, func,
400 PCIR_SUBCLASS, 1);
401
402 s = legacy_pcib_is_host_bridge(bus, slot, func,
403 id, class, subclass,
404 &busnum);
405 if (s == NULL)
406 continue;
407
408 /*
409 * Check to see if the physical bus has already
410 * been seen. Eg: hybrid 32 and 64 bit host
411 * bridges to the same logical bus.
412 */
413 if (device_get_children(parent, &devs, &ndevs) == 0) {
414 for (i = 0; s != NULL && i < ndevs; i++) {
415 if (strcmp(device_get_name(devs[i]),
416 "pcib") != 0)
417 continue;
418 if (legacy_get_pcibus(devs[i]) == busnum)
419 s = NULL;
420 }
421 free(devs, M_TEMP);
422 }
423
424 if (s == NULL)
425 continue;
426 /*
427 * Add at priority 100 to make sure we
428 * go after any motherboard resources
429 */
430 child = BUS_ADD_CHILD(parent, 100,
431 "pcib", busnum);
432 device_set_desc(child, s);
433 legacy_set_pcibus(child, busnum);
434
435 found = 1;
436 if (id == 0x12258086)
437 found824xx = 1;
438 if (id == 0x84c48086)
439 found_orion = 1;
440 }
441 }
442 if (found824xx && bus == 0) {
443 bus++;
444 goto retry;
445 }
446
447 /*
448 * Make sure we add at least one bridge since some old
449 * hardware doesn't actually have a host-pci bridge device.
450 * Note that pci_cfgregopen() thinks we have PCI devices..
451 */
452 if (!found) {
453 if (bootverbose)
454 printf(
455 "legacy_pcib_identify: no bridge found, adding pcib0 anyway\n");
456 child = BUS_ADD_CHILD(parent, 100, "pcib", 0);
457 legacy_set_pcibus(child, 0);
458 }
459 }
460
461 static int
462 legacy_pcib_probe(device_t dev)
463 {
464
465 if (pci_cfgregopen() == 0)
466 return ENXIO;
467 return -100;
468 }
469
470 static int
471 legacy_pcib_attach(device_t dev)
472 {
473 device_t pir;
474 int bus;
475
476 /*
477 * Look for a PCI BIOS interrupt routing table as that will be
478 * our method of routing interrupts if we have one.
479 */
480 bus = pcib_get_bus(dev);
481 if (pci_pir_probe(bus, 0)) {
482 pir = BUS_ADD_CHILD(device_get_parent(dev), 0, "pir", 0);
483 if (pir != NULL)
484 device_probe_and_attach(pir);
485 }
486 device_add_child(dev, "pci", bus);
487 return bus_generic_attach(dev);
488 }
489
490 int
491 legacy_pcib_read_ivar(device_t dev, device_t child, int which,
492 uintptr_t *result)
493 {
494
495 switch (which) {
496 case PCIB_IVAR_DOMAIN:
497 *result = 0;
498 return 0;
499 case PCIB_IVAR_BUS:
500 *result = legacy_get_pcibus(dev);
501 return 0;
502 }
503 return ENOENT;
504 }
505
506 int
507 legacy_pcib_write_ivar(device_t dev, device_t child, int which,
508 uintptr_t value)
509 {
510
511 switch (which) {
512 case PCIB_IVAR_DOMAIN:
513 return EINVAL;
514 case PCIB_IVAR_BUS:
515 legacy_set_pcibus(dev, value);
516 return 0;
517 }
518 return ENOENT;
519 }
520
521 SYSCTL_DECL(_hw_pci);
522
523 static unsigned long legacy_host_mem_start = 0x80000000;
524 TUNABLE_ULONG("hw.pci.host_mem_start", &legacy_host_mem_start);
525 SYSCTL_ULONG(_hw_pci, OID_AUTO, host_mem_start, CTLFLAG_RDTUN,
526 &legacy_host_mem_start, 0x80000000,
527 "Limit the host bridge memory to being above this address. Must be\n\
528 set at boot via a tunable.");
529
530 struct resource *
531 legacy_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
532 u_long start, u_long end, u_long count, u_int flags)
533 {
534 /*
535 * If no memory preference is given, use upper 32MB slot most
536 * bioses use for their memory window. Typically other bridges
537 * before us get in the way to assert their preferences on memory.
538 * Hardcoding like this sucks, so a more MD/MI way needs to be
539 * found to do it. This is typically only used on older laptops
540 * that don't have pci busses behind pci bridge, so assuming > 32MB
541 * is liekly OK.
542 *
543 * However, this can cause problems for other chipsets, so we make
544 * this tunable by hw.pci.host_mem_start.
545 */
546 if (type == SYS_RES_MEMORY && start == 0UL && end == ~0UL)
547 start = legacy_host_mem_start;
548 if (type == SYS_RES_IOPORT && start == 0UL && end == ~0UL)
549 start = 0x1000;
550 return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
551 count, flags));
552 }
553
554 static device_method_t legacy_pcib_methods[] = {
555 /* Device interface */
556 DEVMETHOD(device_identify, legacy_pcib_identify),
557 DEVMETHOD(device_probe, legacy_pcib_probe),
558 DEVMETHOD(device_attach, legacy_pcib_attach),
559 DEVMETHOD(device_shutdown, bus_generic_shutdown),
560 DEVMETHOD(device_suspend, bus_generic_suspend),
561 DEVMETHOD(device_resume, bus_generic_resume),
562
563 /* Bus interface */
564 DEVMETHOD(bus_print_child, bus_generic_print_child),
565 DEVMETHOD(bus_read_ivar, legacy_pcib_read_ivar),
566 DEVMETHOD(bus_write_ivar, legacy_pcib_write_ivar),
567 DEVMETHOD(bus_alloc_resource, legacy_pcib_alloc_resource),
568 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
569 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
570 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
571 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
572 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
573
574 /* pcib interface */
575 DEVMETHOD(pcib_maxslots, legacy_pcib_maxslots),
576 DEVMETHOD(pcib_read_config, legacy_pcib_read_config),
577 DEVMETHOD(pcib_write_config, legacy_pcib_write_config),
578 DEVMETHOD(pcib_route_interrupt, pcibios_pcib_route_interrupt),
579 DEVMETHOD(pcib_alloc_msi, legacy_pcib_alloc_msi),
580 DEVMETHOD(pcib_release_msi, pcib_release_msi),
581 DEVMETHOD(pcib_alloc_msix, legacy_pcib_alloc_msix),
582 DEVMETHOD(pcib_release_msix, pcib_release_msix),
583 DEVMETHOD(pcib_map_msi, legacy_pcib_map_msi),
584
585 { 0, 0 }
586 };
587
588 static devclass_t hostb_devclass;
589
590 DEFINE_CLASS_0(pcib, legacy_pcib_driver, legacy_pcib_methods, 1);
591 DRIVER_MODULE(pcib, legacy, legacy_pcib_driver, hostb_devclass, 0, 0);
592
593
594 /*
595 * Install placeholder to claim the resources owned by the
596 * PCI bus interface. This could be used to extract the
597 * config space registers in the extreme case where the PnP
598 * ID is available and the PCI BIOS isn't, but for now we just
599 * eat the PnP ID and do nothing else.
600 *
601 * XXX we should silence this probe, as it will generally confuse
602 * people.
603 */
604 static struct isa_pnp_id pcibus_pnp_ids[] = {
605 { 0x030ad041 /* PNP0A03 */, "PCI Bus" },
606 { 0x080ad041 /* PNP0A08 */, "PCIe Bus" },
607 { 0 }
608 };
609
610 static int
611 pcibus_pnp_probe(device_t dev)
612 {
613 int result;
614
615 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, pcibus_pnp_ids)) <= 0)
616 device_quiet(dev);
617 return(result);
618 }
619
620 static int
621 pcibus_pnp_attach(device_t dev)
622 {
623 return(0);
624 }
625
626 static device_method_t pcibus_pnp_methods[] = {
627 /* Device interface */
628 DEVMETHOD(device_probe, pcibus_pnp_probe),
629 DEVMETHOD(device_attach, pcibus_pnp_attach),
630 DEVMETHOD(device_detach, bus_generic_detach),
631 DEVMETHOD(device_shutdown, bus_generic_shutdown),
632 DEVMETHOD(device_suspend, bus_generic_suspend),
633 DEVMETHOD(device_resume, bus_generic_resume),
634 { 0, 0 }
635 };
636
637 static devclass_t pcibus_pnp_devclass;
638
639 DEFINE_CLASS_0(pcibus_pnp, pcibus_pnp_driver, pcibus_pnp_methods, 1);
640 DRIVER_MODULE(pcibus_pnp, isa, pcibus_pnp_driver, pcibus_pnp_devclass, 0, 0);
641
642
643 /*
644 * Provide a PCI-PCI bridge driver for PCI busses behind PCI-PCI bridges
645 * that appear in the PCIBIOS Interrupt Routing Table to use the routing
646 * table for interrupt routing when possible.
647 */
648 static int pcibios_pcib_probe(device_t bus);
649
650 static device_method_t pcibios_pcib_pci_methods[] = {
651 /* Device interface */
652 DEVMETHOD(device_probe, pcibios_pcib_probe),
653 DEVMETHOD(device_attach, pcib_attach),
654 DEVMETHOD(device_shutdown, bus_generic_shutdown),
655 DEVMETHOD(device_suspend, bus_generic_suspend),
656 DEVMETHOD(device_resume, bus_generic_resume),
657
658 /* Bus interface */
659 DEVMETHOD(bus_print_child, bus_generic_print_child),
660 DEVMETHOD(bus_read_ivar, pcib_read_ivar),
661 DEVMETHOD(bus_write_ivar, pcib_write_ivar),
662 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource),
663 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
664 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
665 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
666 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
667 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
668
669 /* pcib interface */
670 DEVMETHOD(pcib_maxslots, pcib_maxslots),
671 DEVMETHOD(pcib_read_config, pcib_read_config),
672 DEVMETHOD(pcib_write_config, pcib_write_config),
673 DEVMETHOD(pcib_route_interrupt, pcibios_pcib_route_interrupt),
674 DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi),
675 DEVMETHOD(pcib_release_msi, pcib_release_msi),
676 DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix),
677 DEVMETHOD(pcib_release_msix, pcib_release_msix),
678 DEVMETHOD(pcib_map_msi, pcib_map_msi),
679
680 {0, 0}
681 };
682
683 static devclass_t pcib_devclass;
684
685 DEFINE_CLASS_0(pcib, pcibios_pcib_driver, pcibios_pcib_pci_methods,
686 sizeof(struct pcib_softc));
687 DRIVER_MODULE(pcibios_pcib, pci, pcibios_pcib_driver, pcib_devclass, 0, 0);
688
689 static int
690 pcibios_pcib_probe(device_t dev)
691 {
692 int bus;
693
694 if ((pci_get_class(dev) != PCIC_BRIDGE) ||
695 (pci_get_subclass(dev) != PCIS_BRIDGE_PCI))
696 return (ENXIO);
697 bus = pci_read_config(dev, PCIR_SECBUS_1, 1);
698 if (bus == 0)
699 return (ENXIO);
700 if (!pci_pir_probe(bus, 1))
701 return (ENXIO);
702 device_set_desc(dev, "PCIBIOS PCI-PCI bridge");
703 return (-2000);
704 }
705
706 static int
707 pcibios_pcib_route_interrupt(device_t pcib, device_t dev, int pin)
708 {
709 return (pci_pir_route_interrupt(pci_get_bus(dev), pci_get_slot(dev),
710 pci_get_function(dev), pin));
711 }
Cache object: 2ffdd41560a3a41fc5953d45a38fa045
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