The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/i386/pci/pci_bus.c

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    1 /*-
    2  * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice unmodified, this list of conditions, and the following
   10  *    disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  *
   15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   25  */
   26 
   27 #include <sys/cdefs.h>
   28 __FBSDID("$FreeBSD: releng/8.3/sys/i386/pci/pci_bus.c 230714 2012-01-29 01:22:48Z marius $");
   29 
   30 #include "opt_cpu.h"
   31 
   32 #include <sys/param.h>
   33 #include <sys/systm.h>
   34 #include <sys/bus.h>
   35 #include <sys/kernel.h>
   36 #include <sys/malloc.h>
   37 #include <sys/module.h>
   38 #include <sys/rman.h>
   39 #include <sys/sysctl.h>
   40 
   41 #include <dev/pci/pcivar.h>
   42 #include <dev/pci/pcireg.h>
   43 #include <dev/pci/pcib_private.h>
   44 #include <isa/isavar.h>
   45 #ifdef CPU_ELAN
   46 #include <machine/md_var.h>
   47 #endif
   48 #include <machine/legacyvar.h>
   49 #include <machine/pci_cfgreg.h>
   50 #include <machine/resource.h>
   51 
   52 #include "pcib_if.h"
   53 
   54 static int      pcibios_pcib_route_interrupt(device_t pcib, device_t dev,
   55     int pin);
   56 
   57 int
   58 legacy_pcib_maxslots(device_t dev)
   59 {
   60         return 31;
   61 }
   62 
   63 /* read configuration space register */
   64 
   65 u_int32_t
   66 legacy_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
   67                         u_int reg, int bytes)
   68 {
   69         return(pci_cfgregread(bus, slot, func, reg, bytes));
   70 }
   71 
   72 /* write configuration space register */
   73 
   74 void
   75 legacy_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
   76                          u_int reg, u_int32_t data, int bytes)
   77 {
   78         pci_cfgregwrite(bus, slot, func, reg, data, bytes);
   79 }
   80 
   81 /* Pass MSI requests up to the nexus. */
   82 
   83 static int
   84 legacy_pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount,
   85     int *irqs)
   86 {
   87         device_t bus;
   88 
   89         bus = device_get_parent(pcib);
   90         return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount,
   91             irqs));
   92 }
   93 
   94 static int
   95 legacy_pcib_alloc_msix(device_t pcib, device_t dev, int *irq)
   96 {
   97         device_t bus;
   98 
   99         bus = device_get_parent(pcib);
  100         return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq));
  101 }
  102 
  103 static int
  104 legacy_pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr,
  105     uint32_t *data)
  106 {
  107         device_t bus;
  108 
  109         bus = device_get_parent(pcib);
  110         return (PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data));
  111 }
  112 
  113 static const char *
  114 legacy_pcib_is_host_bridge(int bus, int slot, int func,
  115                           uint32_t id, uint8_t class, uint8_t subclass,
  116                           uint8_t *busnum)
  117 {
  118         const char *s = NULL;
  119         static uint8_t pxb[4];  /* hack for 450nx */
  120 
  121         *busnum = 0;
  122 
  123         switch (id) {
  124         case 0x12258086:
  125                 s = "Intel 824?? host to PCI bridge";
  126                 /* XXX This is a guess */
  127                 /* *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x41, 1); */
  128                 *busnum = bus;
  129                 break;
  130         case 0x71208086:
  131                 s = "Intel 82810 (i810 GMCH) Host To Hub bridge";
  132                 break;
  133         case 0x71228086:
  134                 s = "Intel 82810-DC100 (i810-DC100 GMCH) Host To Hub bridge";
  135                 break;
  136         case 0x71248086:
  137                 s = "Intel 82810E (i810E GMCH) Host To Hub bridge";
  138                 break;
  139         case 0x11308086:
  140                 s = "Intel 82815 (i815 GMCH) Host To Hub bridge";
  141                 break;
  142         case 0x71808086:
  143                 s = "Intel 82443LX (440 LX) host to PCI bridge";
  144                 break;
  145         case 0x71908086:
  146                 s = "Intel 82443BX (440 BX) host to PCI bridge";
  147                 break;
  148         case 0x71928086:
  149                 s = "Intel 82443BX host to PCI bridge (AGP disabled)";
  150                 break;
  151         case 0x71948086:
  152                 s = "Intel 82443MX host to PCI bridge";
  153                 break;
  154         case 0x71a08086:
  155                 s = "Intel 82443GX host to PCI bridge";
  156                 break;
  157         case 0x71a18086:
  158                 s = "Intel 82443GX host to AGP bridge";
  159                 break;
  160         case 0x71a28086:
  161                 s = "Intel 82443GX host to PCI bridge (AGP disabled)";
  162                 break;
  163         case 0x84c48086:
  164                 s = "Intel 82454KX/GX (Orion) host to PCI bridge";
  165                 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x4a, 1);
  166                 break;
  167         case 0x84ca8086:
  168                 /*
  169                  * For the 450nx chipset, there is a whole bundle of
  170                  * things pretending to be host bridges. The MIOC will
  171                  * be seen first and isn't really a pci bridge (the
  172                  * actual busses are attached to the PXB's). We need to
  173                  * read the registers of the MIOC to figure out the
  174                  * bus numbers for the PXB channels.
  175                  *
  176                  * Since the MIOC doesn't have a pci bus attached, we
  177                  * pretend it wasn't there.
  178                  */
  179                 pxb[0] = legacy_pcib_read_config(0, bus, slot, func,
  180                                                 0xd0, 1); /* BUSNO[0] */
  181                 pxb[1] = legacy_pcib_read_config(0, bus, slot, func,
  182                                                 0xd1, 1) + 1;   /* SUBA[0]+1 */
  183                 pxb[2] = legacy_pcib_read_config(0, bus, slot, func,
  184                                                 0xd3, 1); /* BUSNO[1] */
  185                 pxb[3] = legacy_pcib_read_config(0, bus, slot, func,
  186                                                 0xd4, 1) + 1;   /* SUBA[1]+1 */
  187                 return NULL;
  188         case 0x84cb8086:
  189                 switch (slot) {
  190                 case 0x12:
  191                         s = "Intel 82454NX PXB#0, Bus#A";
  192                         *busnum = pxb[0];
  193                         break;
  194                 case 0x13:
  195                         s = "Intel 82454NX PXB#0, Bus#B";
  196                         *busnum = pxb[1];
  197                         break;
  198                 case 0x14:
  199                         s = "Intel 82454NX PXB#1, Bus#A";
  200                         *busnum = pxb[2];
  201                         break;
  202                 case 0x15:
  203                         s = "Intel 82454NX PXB#1, Bus#B";
  204                         *busnum = pxb[3];
  205                         break;
  206                 }
  207                 break;
  208         case 0x1A308086:
  209                 s = "Intel 82845 Host to PCI bridge";
  210                 break;
  211 
  212                 /* AMD -- vendor 0x1022 */
  213         case 0x30001022:
  214                 s = "AMD Elan SC520 host to PCI bridge";
  215 #ifdef CPU_ELAN
  216                 init_AMD_Elan_sc520();
  217 #else
  218                 printf(
  219 "*** WARNING: missing CPU_ELAN -- timekeeping may be wrong\n");
  220 #endif
  221                 break;
  222         case 0x70061022:
  223                 s = "AMD-751 host to PCI bridge";
  224                 break;
  225         case 0x700e1022:
  226                 s = "AMD-761 host to PCI bridge";
  227                 break;
  228 
  229                 /* SiS -- vendor 0x1039 */
  230         case 0x04961039:
  231                 s = "SiS 85c496";
  232                 break;
  233         case 0x04061039:
  234                 s = "SiS 85c501";
  235                 break;
  236         case 0x06011039:
  237                 s = "SiS 85c601";
  238                 break;
  239         case 0x55911039:
  240                 s = "SiS 5591 host to PCI bridge";
  241                 break;
  242         case 0x00011039:
  243                 s = "SiS 5591 host to AGP bridge";
  244                 break;
  245 
  246                 /* VLSI -- vendor 0x1004 */
  247         case 0x00051004:
  248                 s = "VLSI 82C592 Host to PCI bridge";
  249                 break;
  250 
  251                 /* XXX Here is MVP3, I got the datasheet but NO M/B to test it  */
  252                 /* totally. Please let me know if anything wrong.            -F */
  253                 /* XXX need info on the MVP3 -- any takers? */
  254         case 0x05981106:
  255                 s = "VIA 82C598MVP (Apollo MVP3) host bridge";
  256                 break;
  257 
  258                 /* AcerLabs -- vendor 0x10b9 */
  259                 /* Funny : The datasheet told me vendor id is "10b8",sub-vendor */
  260                 /* id is '10b9" but the register always shows "10b9". -Foxfair  */
  261         case 0x154110b9:
  262                 s = "AcerLabs M1541 (Aladdin-V) PCI host bridge";
  263                 break;
  264 
  265                 /* OPTi -- vendor 0x1045 */
  266         case 0xc7011045:
  267                 s = "OPTi 82C700 host to PCI bridge";
  268                 break;
  269         case 0xc8221045:
  270                 s = "OPTi 82C822 host to PCI Bridge";
  271                 break;
  272 
  273                 /* ServerWorks -- vendor 0x1166 */
  274         case 0x00051166:
  275                 s = "ServerWorks NB6536 2.0HE host to PCI bridge";
  276                 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
  277                 break;
  278 
  279         case 0x00061166:
  280                 /* FALLTHROUGH */
  281         case 0x00081166:
  282                 /* FALLTHROUGH */
  283         case 0x02011166:
  284                 /* FALLTHROUGH */
  285         case 0x010f1014: /* IBM re-badged ServerWorks chipset */
  286                 s = "ServerWorks host to PCI bridge";
  287                 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
  288                 break;
  289 
  290         case 0x00091166:
  291                 s = "ServerWorks NB6635 3.0LE host to PCI bridge";
  292                 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
  293                 break;
  294 
  295         case 0x00101166:
  296                 s = "ServerWorks CIOB30 host to PCI bridge";
  297                 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
  298                 break;
  299 
  300         case 0x00111166:
  301                 /* FALLTHROUGH */
  302         case 0x03021014: /* IBM re-badged ServerWorks chipset */
  303                 s = "ServerWorks CMIC-HE host to PCI-X bridge";
  304                 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
  305                 break;
  306 
  307                 /* XXX unknown chipset, but working */
  308         case 0x00171166:
  309                 /* FALLTHROUGH */
  310         case 0x01011166:
  311         case 0x01101166:
  312         case 0x02251166:
  313                 s = "ServerWorks host to PCI bridge(unknown chipset)";
  314                 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
  315                 break;
  316 
  317                 /* Compaq/HP -- vendor 0x0e11 */
  318         case 0x60100e11:
  319                 s = "Compaq/HP Model 6010 HotPlug PCI Bridge";
  320                 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0xc8, 1);
  321                 break;
  322 
  323                 /* Integrated Micro Solutions -- vendor 0x10e0 */
  324         case 0x884910e0:
  325                 s = "Integrated Micro Solutions VL Bridge";
  326                 break;
  327 
  328         default:
  329                 if (class == PCIC_BRIDGE && subclass == PCIS_BRIDGE_HOST)
  330                         s = "Host to PCI bridge";
  331                 break;
  332         }
  333 
  334         return s;
  335 }
  336 
  337 /*
  338  * Scan the first pci bus for host-pci bridges and add pcib instances
  339  * to the nexus for each bridge.
  340  */
  341 static void
  342 legacy_pcib_identify(driver_t *driver, device_t parent)
  343 {
  344         int bus, slot, func;
  345         u_int8_t  hdrtype;
  346         int found = 0;
  347         int pcifunchigh;
  348         int found824xx = 0;
  349         int found_orion = 0;
  350         device_t child;
  351         devclass_t pci_devclass;
  352 
  353         if (pci_cfgregopen() == 0)
  354                 return;
  355         /*
  356          * Check to see if we haven't already had a PCI bus added
  357          * via some other means.  If we have, bail since otherwise
  358          * we're going to end up duplicating it.
  359          */
  360         if ((pci_devclass = devclass_find("pci")) &&
  361                 devclass_get_device(pci_devclass, 0))
  362                 return;
  363 
  364 
  365         bus = 0;
  366  retry:
  367         for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
  368                 func = 0;
  369                 hdrtype = legacy_pcib_read_config(0, bus, slot, func,
  370                                                  PCIR_HDRTYPE, 1);
  371                 /*
  372                  * When enumerating bus devices, the standard says that
  373                  * one should check the header type and ignore the slots whose
  374                  * header types that the software doesn't know about.  We use
  375                  * this to filter out devices.
  376                  */
  377                 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
  378                         continue;
  379                 if ((hdrtype & PCIM_MFDEV) &&
  380                     (!found_orion || hdrtype != 0xff))
  381                         pcifunchigh = PCI_FUNCMAX;
  382                 else
  383                         pcifunchigh = 0;
  384                 for (func = 0; func <= pcifunchigh; func++) {
  385                         /*
  386                          * Read the IDs and class from the device.
  387                          */
  388                         u_int32_t id;
  389                         u_int8_t class, subclass, busnum;
  390                         const char *s;
  391                         device_t *devs;
  392                         int ndevs, i;
  393 
  394                         id = legacy_pcib_read_config(0, bus, slot, func,
  395                                                     PCIR_DEVVENDOR, 4);
  396                         if (id == -1)
  397                                 continue;
  398                         class = legacy_pcib_read_config(0, bus, slot, func,
  399                                                        PCIR_CLASS, 1);
  400                         subclass = legacy_pcib_read_config(0, bus, slot, func,
  401                                                           PCIR_SUBCLASS, 1);
  402 
  403                         s = legacy_pcib_is_host_bridge(bus, slot, func,
  404                                                       id, class, subclass,
  405                                                       &busnum);
  406                         if (s == NULL)
  407                                 continue;
  408 
  409                         /*
  410                          * Check to see if the physical bus has already
  411                          * been seen.  Eg: hybrid 32 and 64 bit host
  412                          * bridges to the same logical bus.
  413                          */
  414                         if (device_get_children(parent, &devs, &ndevs) == 0) {
  415                                 for (i = 0; s != NULL && i < ndevs; i++) {
  416                                         if (strcmp(device_get_name(devs[i]),
  417                                             "pcib") != 0)
  418                                                 continue;
  419                                         if (legacy_get_pcibus(devs[i]) == busnum)
  420                                                 s = NULL;
  421                                 }
  422                                 free(devs, M_TEMP);
  423                         }
  424 
  425                         if (s == NULL)
  426                                 continue;
  427                         /*
  428                          * Add at priority 100 to make sure we
  429                          * go after any motherboard resources
  430                          */
  431                         child = BUS_ADD_CHILD(parent, 100,
  432                                               "pcib", busnum);
  433                         device_set_desc(child, s);
  434                         legacy_set_pcibus(child, busnum);
  435 
  436                         found = 1;
  437                         if (id == 0x12258086)
  438                                 found824xx = 1;
  439                         if (id == 0x84c48086)
  440                                 found_orion = 1;
  441                 }
  442         }
  443         if (found824xx && bus == 0) {
  444                 bus++;
  445                 goto retry;
  446         }
  447 
  448         /*
  449          * Make sure we add at least one bridge since some old
  450          * hardware doesn't actually have a host-pci bridge device.
  451          * Note that pci_cfgregopen() thinks we have PCI devices..
  452          */
  453         if (!found) {
  454                 if (bootverbose)
  455                         printf(
  456         "legacy_pcib_identify: no bridge found, adding pcib0 anyway\n");
  457                 child = BUS_ADD_CHILD(parent, 100, "pcib", 0);
  458                 legacy_set_pcibus(child, 0);
  459         }
  460 }
  461 
  462 static int
  463 legacy_pcib_probe(device_t dev)
  464 {
  465 
  466         if (pci_cfgregopen() == 0)
  467                 return ENXIO;
  468         return -100;
  469 }
  470 
  471 static int
  472 legacy_pcib_attach(device_t dev)
  473 {
  474         device_t pir;
  475         int bus;
  476 
  477         /*
  478          * Look for a PCI BIOS interrupt routing table as that will be
  479          * our method of routing interrupts if we have one.
  480          */
  481         bus = pcib_get_bus(dev);
  482         if (pci_pir_probe(bus, 0)) {
  483                 pir = BUS_ADD_CHILD(device_get_parent(dev), 0, "pir", 0);
  484                 if (pir != NULL)
  485                         device_probe_and_attach(pir);
  486         }
  487         device_add_child(dev, "pci", bus);
  488         return bus_generic_attach(dev);
  489 }
  490 
  491 int
  492 legacy_pcib_read_ivar(device_t dev, device_t child, int which,
  493     uintptr_t *result)
  494 {
  495 
  496         switch (which) {
  497         case  PCIB_IVAR_DOMAIN:
  498                 *result = 0;
  499                 return 0;
  500         case  PCIB_IVAR_BUS:
  501                 *result = legacy_get_pcibus(dev);
  502                 return 0;
  503         }
  504         return ENOENT;
  505 }
  506 
  507 int
  508 legacy_pcib_write_ivar(device_t dev, device_t child, int which,
  509     uintptr_t value)
  510 {
  511 
  512         switch (which) {
  513         case  PCIB_IVAR_DOMAIN:
  514                 return EINVAL;
  515         case  PCIB_IVAR_BUS:
  516                 legacy_set_pcibus(dev, value);
  517                 return 0;
  518         }
  519         return ENOENT;
  520 }
  521 
  522 SYSCTL_DECL(_hw_pci);
  523 
  524 static unsigned long legacy_host_mem_start = 0x80000000;
  525 TUNABLE_ULONG("hw.pci.host_mem_start", &legacy_host_mem_start);
  526 SYSCTL_ULONG(_hw_pci, OID_AUTO, host_mem_start, CTLFLAG_RDTUN,
  527     &legacy_host_mem_start, 0x80000000,
  528     "Limit the host bridge memory to being above this address.  Must be\n\
  529 set at boot via a tunable.");
  530 
  531 struct resource *
  532 legacy_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
  533     u_long start, u_long end, u_long count, u_int flags)
  534 {
  535     /*
  536      * If no memory preference is given, use upper 32MB slot most
  537      * bioses use for their memory window.  Typically other bridges
  538      * before us get in the way to assert their preferences on memory.
  539      * Hardcoding like this sucks, so a more MD/MI way needs to be
  540      * found to do it.  This is typically only used on older laptops
  541      * that don't have pci busses behind pci bridge, so assuming > 32MB
  542      * is liekly OK.
  543      *
  544      * However, this can cause problems for other chipsets, so we make
  545      * this tunable by hw.pci.host_mem_start.
  546      */
  547     if (type == SYS_RES_MEMORY && start == 0UL && end == ~0UL)
  548         start = legacy_host_mem_start;
  549     if (type == SYS_RES_IOPORT && start == 0UL && end == ~0UL)
  550         start = 0x1000;
  551     return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
  552         count, flags));
  553 }
  554 
  555 static device_method_t legacy_pcib_methods[] = {
  556         /* Device interface */
  557         DEVMETHOD(device_identify,      legacy_pcib_identify),
  558         DEVMETHOD(device_probe,         legacy_pcib_probe),
  559         DEVMETHOD(device_attach,        legacy_pcib_attach),
  560         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
  561         DEVMETHOD(device_suspend,       bus_generic_suspend),
  562         DEVMETHOD(device_resume,        bus_generic_resume),
  563 
  564         /* Bus interface */
  565         DEVMETHOD(bus_read_ivar,        legacy_pcib_read_ivar),
  566         DEVMETHOD(bus_write_ivar,       legacy_pcib_write_ivar),
  567         DEVMETHOD(bus_alloc_resource,   legacy_pcib_alloc_resource),
  568         DEVMETHOD(bus_adjust_resource,  bus_generic_adjust_resource),
  569         DEVMETHOD(bus_release_resource, bus_generic_release_resource),
  570         DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
  571         DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
  572         DEVMETHOD(bus_setup_intr,       bus_generic_setup_intr),
  573         DEVMETHOD(bus_teardown_intr,    bus_generic_teardown_intr),
  574 
  575         /* pcib interface */
  576         DEVMETHOD(pcib_maxslots,        legacy_pcib_maxslots),
  577         DEVMETHOD(pcib_read_config,     legacy_pcib_read_config),
  578         DEVMETHOD(pcib_write_config,    legacy_pcib_write_config),
  579         DEVMETHOD(pcib_route_interrupt, pcibios_pcib_route_interrupt),
  580         DEVMETHOD(pcib_alloc_msi,       legacy_pcib_alloc_msi),
  581         DEVMETHOD(pcib_release_msi,     pcib_release_msi),
  582         DEVMETHOD(pcib_alloc_msix,      legacy_pcib_alloc_msix),
  583         DEVMETHOD(pcib_release_msix,    pcib_release_msix),
  584         DEVMETHOD(pcib_map_msi,         legacy_pcib_map_msi),
  585 
  586         DEVMETHOD_END
  587 };
  588 
  589 static devclass_t hostb_devclass;
  590 
  591 DEFINE_CLASS_0(pcib, legacy_pcib_driver, legacy_pcib_methods, 1);
  592 DRIVER_MODULE(pcib, legacy, legacy_pcib_driver, hostb_devclass, 0, 0);
  593 
  594 
  595 /*
  596  * Install placeholder to claim the resources owned by the
  597  * PCI bus interface.  This could be used to extract the
  598  * config space registers in the extreme case where the PnP
  599  * ID is available and the PCI BIOS isn't, but for now we just
  600  * eat the PnP ID and do nothing else.
  601  *
  602  * XXX we should silence this probe, as it will generally confuse
  603  * people.
  604  */
  605 static struct isa_pnp_id pcibus_pnp_ids[] = {
  606         { 0x030ad041 /* PNP0A03 */, "PCI Bus" },
  607         { 0x080ad041 /* PNP0A08 */, "PCIe Bus" },
  608         { 0 }
  609 };
  610 
  611 static int
  612 pcibus_pnp_probe(device_t dev)
  613 {
  614         int result;
  615 
  616         if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, pcibus_pnp_ids)) <= 0)
  617                 device_quiet(dev);
  618         return(result);
  619 }
  620 
  621 static int
  622 pcibus_pnp_attach(device_t dev)
  623 {
  624         return(0);
  625 }
  626 
  627 static device_method_t pcibus_pnp_methods[] = {
  628         /* Device interface */
  629         DEVMETHOD(device_probe,         pcibus_pnp_probe),
  630         DEVMETHOD(device_attach,        pcibus_pnp_attach),
  631         DEVMETHOD(device_detach,        bus_generic_detach),
  632         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
  633         DEVMETHOD(device_suspend,       bus_generic_suspend),
  634         DEVMETHOD(device_resume,        bus_generic_resume),
  635         { 0, 0 }
  636 };
  637 
  638 static devclass_t pcibus_pnp_devclass;
  639 
  640 DEFINE_CLASS_0(pcibus_pnp, pcibus_pnp_driver, pcibus_pnp_methods, 1);
  641 DRIVER_MODULE(pcibus_pnp, isa, pcibus_pnp_driver, pcibus_pnp_devclass, 0, 0);
  642 
  643 
  644 /*
  645  * Provide a PCI-PCI bridge driver for PCI busses behind PCI-PCI bridges
  646  * that appear in the PCIBIOS Interrupt Routing Table to use the routing
  647  * table for interrupt routing when possible.
  648  */
  649 static int      pcibios_pcib_probe(device_t bus);
  650 
  651 static device_method_t pcibios_pcib_pci_methods[] = {
  652         /* Device interface */
  653         DEVMETHOD(device_probe,         pcibios_pcib_probe),
  654         DEVMETHOD(device_attach,        pcib_attach),
  655         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
  656         DEVMETHOD(device_suspend,       bus_generic_suspend),
  657         DEVMETHOD(device_resume,        bus_generic_resume),
  658 
  659         /* Bus interface */
  660         DEVMETHOD(bus_read_ivar,        pcib_read_ivar),
  661         DEVMETHOD(bus_write_ivar,       pcib_write_ivar),
  662         DEVMETHOD(bus_alloc_resource,   pcib_alloc_resource),
  663         DEVMETHOD(bus_release_resource, bus_generic_release_resource),
  664         DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
  665         DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
  666         DEVMETHOD(bus_setup_intr,       bus_generic_setup_intr),
  667         DEVMETHOD(bus_teardown_intr,    bus_generic_teardown_intr),
  668 
  669         /* pcib interface */
  670         DEVMETHOD(pcib_maxslots,        pcib_maxslots),
  671         DEVMETHOD(pcib_read_config,     pcib_read_config),
  672         DEVMETHOD(pcib_write_config,    pcib_write_config),
  673         DEVMETHOD(pcib_route_interrupt, pcibios_pcib_route_interrupt),
  674         DEVMETHOD(pcib_alloc_msi,       pcib_alloc_msi),
  675         DEVMETHOD(pcib_release_msi,     pcib_release_msi),
  676         DEVMETHOD(pcib_alloc_msix,      pcib_alloc_msix),
  677         DEVMETHOD(pcib_release_msix,    pcib_release_msix),
  678         DEVMETHOD(pcib_map_msi,         pcib_map_msi),
  679 
  680         DEVMETHOD_END
  681 };
  682 
  683 static devclass_t pcib_devclass;
  684 
  685 DEFINE_CLASS_0(pcib, pcibios_pcib_driver, pcibios_pcib_pci_methods,
  686     sizeof(struct pcib_softc));
  687 DRIVER_MODULE(pcibios_pcib, pci, pcibios_pcib_driver, pcib_devclass, 0, 0);
  688 
  689 static int
  690 pcibios_pcib_probe(device_t dev)
  691 {
  692         int bus;
  693 
  694         if ((pci_get_class(dev) != PCIC_BRIDGE) ||
  695             (pci_get_subclass(dev) != PCIS_BRIDGE_PCI))
  696                 return (ENXIO);
  697         bus = pci_read_config(dev, PCIR_SECBUS_1, 1);
  698         if (bus == 0)
  699                 return (ENXIO);
  700         if (!pci_pir_probe(bus, 1))
  701                 return (ENXIO);
  702         device_set_desc(dev, "PCIBIOS PCI-PCI bridge");
  703         return (-2000);
  704 }
  705 
  706 static int
  707 pcibios_pcib_route_interrupt(device_t pcib, device_t dev, int pin)
  708 {
  709         return (pci_pir_route_interrupt(pci_get_bus(dev), pci_get_slot(dev),
  710                 pci_get_function(dev), pin));
  711 }

Cache object: d05c0ef5226063040810cac645e05604


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