FreeBSD/Linux Kernel Cross Reference
sys/i386/pci/pci_bus.c
1 /*-
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29
30 #include "opt_cpu.h"
31
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/bus.h>
35 #include <sys/kernel.h>
36 #include <sys/malloc.h>
37 #include <sys/module.h>
38 #include <sys/rman.h>
39 #include <sys/sysctl.h>
40
41 #include <dev/pci/pcivar.h>
42 #include <dev/pci/pcireg.h>
43 #include <dev/pci/pcib_private.h>
44 #include <isa/isavar.h>
45 #ifdef CPU_ELAN
46 #include <machine/md_var.h>
47 #endif
48 #include <machine/legacyvar.h>
49 #include <machine/pci_cfgreg.h>
50 #include <machine/resource.h>
51
52 #include "pcib_if.h"
53
54 static int pcibios_pcib_route_interrupt(device_t pcib, device_t dev,
55 int pin);
56
57 int
58 legacy_pcib_maxslots(device_t dev)
59 {
60 return 31;
61 }
62
63 /* read configuration space register */
64
65 u_int32_t
66 legacy_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
67 u_int reg, int bytes)
68 {
69 return(pci_cfgregread(bus, slot, func, reg, bytes));
70 }
71
72 /* write configuration space register */
73
74 void
75 legacy_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
76 u_int reg, u_int32_t data, int bytes)
77 {
78 pci_cfgregwrite(bus, slot, func, reg, data, bytes);
79 }
80
81 /* Pass MSI requests up to the nexus. */
82
83 static int
84 legacy_pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount,
85 int *irqs)
86 {
87 device_t bus;
88
89 bus = device_get_parent(pcib);
90 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount,
91 irqs));
92 }
93
94 static int
95 legacy_pcib_alloc_msix(device_t pcib, device_t dev, int *irq)
96 {
97 device_t bus;
98
99 bus = device_get_parent(pcib);
100 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq));
101 }
102
103 int
104 legacy_pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr,
105 uint32_t *data)
106 {
107 device_t bus, hostb;
108 int error, func, slot;
109
110 bus = device_get_parent(pcib);
111 error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data);
112 if (error)
113 return (error);
114
115 slot = legacy_get_pcislot(pcib);
116 func = legacy_get_pcifunc(pcib);
117 if (slot == -1 || func == -1)
118 return (0);
119 hostb = pci_find_bsf(0, slot, func);
120 KASSERT(hostb != NULL, ("%s: missing hostb for 0:%d:%d", __func__,
121 slot, func));
122 pci_ht_map_msi(hostb, *addr);
123 return (0);
124
125 }
126
127 static const char *
128 legacy_pcib_is_host_bridge(int bus, int slot, int func,
129 uint32_t id, uint8_t class, uint8_t subclass,
130 uint8_t *busnum)
131 {
132 const char *s = NULL;
133 static uint8_t pxb[4]; /* hack for 450nx */
134
135 *busnum = 0;
136
137 switch (id) {
138 case 0x12258086:
139 s = "Intel 824?? host to PCI bridge";
140 /* XXX This is a guess */
141 /* *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x41, 1); */
142 *busnum = bus;
143 break;
144 case 0x71208086:
145 s = "Intel 82810 (i810 GMCH) Host To Hub bridge";
146 break;
147 case 0x71228086:
148 s = "Intel 82810-DC100 (i810-DC100 GMCH) Host To Hub bridge";
149 break;
150 case 0x71248086:
151 s = "Intel 82810E (i810E GMCH) Host To Hub bridge";
152 break;
153 case 0x11308086:
154 s = "Intel 82815 (i815 GMCH) Host To Hub bridge";
155 break;
156 case 0x71808086:
157 s = "Intel 82443LX (440 LX) host to PCI bridge";
158 break;
159 case 0x71908086:
160 s = "Intel 82443BX (440 BX) host to PCI bridge";
161 break;
162 case 0x71928086:
163 s = "Intel 82443BX host to PCI bridge (AGP disabled)";
164 break;
165 case 0x71948086:
166 s = "Intel 82443MX host to PCI bridge";
167 break;
168 case 0x71a08086:
169 s = "Intel 82443GX host to PCI bridge";
170 break;
171 case 0x71a18086:
172 s = "Intel 82443GX host to AGP bridge";
173 break;
174 case 0x71a28086:
175 s = "Intel 82443GX host to PCI bridge (AGP disabled)";
176 break;
177 case 0x84c48086:
178 s = "Intel 82454KX/GX (Orion) host to PCI bridge";
179 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x4a, 1);
180 break;
181 case 0x84ca8086:
182 /*
183 * For the 450nx chipset, there is a whole bundle of
184 * things pretending to be host bridges. The MIOC will
185 * be seen first and isn't really a pci bridge (the
186 * actual busses are attached to the PXB's). We need to
187 * read the registers of the MIOC to figure out the
188 * bus numbers for the PXB channels.
189 *
190 * Since the MIOC doesn't have a pci bus attached, we
191 * pretend it wasn't there.
192 */
193 pxb[0] = legacy_pcib_read_config(0, bus, slot, func,
194 0xd0, 1); /* BUSNO[0] */
195 pxb[1] = legacy_pcib_read_config(0, bus, slot, func,
196 0xd1, 1) + 1; /* SUBA[0]+1 */
197 pxb[2] = legacy_pcib_read_config(0, bus, slot, func,
198 0xd3, 1); /* BUSNO[1] */
199 pxb[3] = legacy_pcib_read_config(0, bus, slot, func,
200 0xd4, 1) + 1; /* SUBA[1]+1 */
201 return NULL;
202 case 0x84cb8086:
203 switch (slot) {
204 case 0x12:
205 s = "Intel 82454NX PXB#0, Bus#A";
206 *busnum = pxb[0];
207 break;
208 case 0x13:
209 s = "Intel 82454NX PXB#0, Bus#B";
210 *busnum = pxb[1];
211 break;
212 case 0x14:
213 s = "Intel 82454NX PXB#1, Bus#A";
214 *busnum = pxb[2];
215 break;
216 case 0x15:
217 s = "Intel 82454NX PXB#1, Bus#B";
218 *busnum = pxb[3];
219 break;
220 }
221 break;
222 case 0x1A308086:
223 s = "Intel 82845 Host to PCI bridge";
224 break;
225
226 /* AMD -- vendor 0x1022 */
227 case 0x30001022:
228 s = "AMD Elan SC520 host to PCI bridge";
229 #ifdef CPU_ELAN
230 init_AMD_Elan_sc520();
231 #else
232 printf(
233 "*** WARNING: missing CPU_ELAN -- timekeeping may be wrong\n");
234 #endif
235 break;
236 case 0x70061022:
237 s = "AMD-751 host to PCI bridge";
238 break;
239 case 0x700e1022:
240 s = "AMD-761 host to PCI bridge";
241 break;
242
243 /* SiS -- vendor 0x1039 */
244 case 0x04961039:
245 s = "SiS 85c496";
246 break;
247 case 0x04061039:
248 s = "SiS 85c501";
249 break;
250 case 0x06011039:
251 s = "SiS 85c601";
252 break;
253 case 0x55911039:
254 s = "SiS 5591 host to PCI bridge";
255 break;
256 case 0x00011039:
257 s = "SiS 5591 host to AGP bridge";
258 break;
259
260 /* VLSI -- vendor 0x1004 */
261 case 0x00051004:
262 s = "VLSI 82C592 Host to PCI bridge";
263 break;
264
265 /* XXX Here is MVP3, I got the datasheet but NO M/B to test it */
266 /* totally. Please let me know if anything wrong. -F */
267 /* XXX need info on the MVP3 -- any takers? */
268 case 0x05981106:
269 s = "VIA 82C598MVP (Apollo MVP3) host bridge";
270 break;
271
272 /* AcerLabs -- vendor 0x10b9 */
273 /* Funny : The datasheet told me vendor id is "10b8",sub-vendor */
274 /* id is '10b9" but the register always shows "10b9". -Foxfair */
275 case 0x154110b9:
276 s = "AcerLabs M1541 (Aladdin-V) PCI host bridge";
277 break;
278
279 /* OPTi -- vendor 0x1045 */
280 case 0xc7011045:
281 s = "OPTi 82C700 host to PCI bridge";
282 break;
283 case 0xc8221045:
284 s = "OPTi 82C822 host to PCI Bridge";
285 break;
286
287 /* ServerWorks -- vendor 0x1166 */
288 case 0x00051166:
289 s = "ServerWorks NB6536 2.0HE host to PCI bridge";
290 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
291 break;
292
293 case 0x00061166:
294 /* FALLTHROUGH */
295 case 0x00081166:
296 /* FALLTHROUGH */
297 case 0x02011166:
298 /* FALLTHROUGH */
299 case 0x010f1014: /* IBM re-badged ServerWorks chipset */
300 s = "ServerWorks host to PCI bridge";
301 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
302 break;
303
304 case 0x00091166:
305 s = "ServerWorks NB6635 3.0LE host to PCI bridge";
306 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
307 break;
308
309 case 0x00101166:
310 s = "ServerWorks CIOB30 host to PCI bridge";
311 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
312 break;
313
314 case 0x00111166:
315 /* FALLTHROUGH */
316 case 0x03021014: /* IBM re-badged ServerWorks chipset */
317 s = "ServerWorks CMIC-HE host to PCI-X bridge";
318 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
319 break;
320
321 /* XXX unknown chipset, but working */
322 case 0x00171166:
323 /* FALLTHROUGH */
324 case 0x01011166:
325 case 0x01101166:
326 case 0x02251166:
327 s = "ServerWorks host to PCI bridge(unknown chipset)";
328 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
329 break;
330
331 /* Compaq/HP -- vendor 0x0e11 */
332 case 0x60100e11:
333 s = "Compaq/HP Model 6010 HotPlug PCI Bridge";
334 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0xc8, 1);
335 break;
336
337 /* Integrated Micro Solutions -- vendor 0x10e0 */
338 case 0x884910e0:
339 s = "Integrated Micro Solutions VL Bridge";
340 break;
341
342 default:
343 if (class == PCIC_BRIDGE && subclass == PCIS_BRIDGE_HOST)
344 s = "Host to PCI bridge";
345 break;
346 }
347
348 return s;
349 }
350
351 /*
352 * Scan the first pci bus for host-pci bridges and add pcib instances
353 * to the nexus for each bridge.
354 */
355 static void
356 legacy_pcib_identify(driver_t *driver, device_t parent)
357 {
358 int bus, slot, func;
359 u_int8_t hdrtype;
360 int found = 0;
361 int pcifunchigh;
362 int found824xx = 0;
363 int found_orion = 0;
364 device_t child;
365 devclass_t pci_devclass;
366
367 if (pci_cfgregopen() == 0)
368 return;
369 /*
370 * Check to see if we haven't already had a PCI bus added
371 * via some other means. If we have, bail since otherwise
372 * we're going to end up duplicating it.
373 */
374 if ((pci_devclass = devclass_find("pci")) &&
375 devclass_get_device(pci_devclass, 0))
376 return;
377
378
379 bus = 0;
380 retry:
381 for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
382 func = 0;
383 hdrtype = legacy_pcib_read_config(0, bus, slot, func,
384 PCIR_HDRTYPE, 1);
385 /*
386 * When enumerating bus devices, the standard says that
387 * one should check the header type and ignore the slots whose
388 * header types that the software doesn't know about. We use
389 * this to filter out devices.
390 */
391 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
392 continue;
393 if ((hdrtype & PCIM_MFDEV) &&
394 (!found_orion || hdrtype != 0xff))
395 pcifunchigh = PCI_FUNCMAX;
396 else
397 pcifunchigh = 0;
398 for (func = 0; func <= pcifunchigh; func++) {
399 /*
400 * Read the IDs and class from the device.
401 */
402 u_int32_t id;
403 u_int8_t class, subclass, busnum;
404 const char *s;
405 device_t *devs;
406 int ndevs, i;
407
408 id = legacy_pcib_read_config(0, bus, slot, func,
409 PCIR_DEVVENDOR, 4);
410 if (id == -1)
411 continue;
412 class = legacy_pcib_read_config(0, bus, slot, func,
413 PCIR_CLASS, 1);
414 subclass = legacy_pcib_read_config(0, bus, slot, func,
415 PCIR_SUBCLASS, 1);
416
417 s = legacy_pcib_is_host_bridge(bus, slot, func,
418 id, class, subclass,
419 &busnum);
420 if (s == NULL)
421 continue;
422
423 /*
424 * Check to see if the physical bus has already
425 * been seen. Eg: hybrid 32 and 64 bit host
426 * bridges to the same logical bus.
427 */
428 if (device_get_children(parent, &devs, &ndevs) == 0) {
429 for (i = 0; s != NULL && i < ndevs; i++) {
430 if (strcmp(device_get_name(devs[i]),
431 "pcib") != 0)
432 continue;
433 if (legacy_get_pcibus(devs[i]) == busnum)
434 s = NULL;
435 }
436 free(devs, M_TEMP);
437 }
438
439 if (s == NULL)
440 continue;
441 /*
442 * Add at priority 100 to make sure we
443 * go after any motherboard resources
444 */
445 child = BUS_ADD_CHILD(parent, 100,
446 "pcib", busnum);
447 device_set_desc(child, s);
448 legacy_set_pcibus(child, busnum);
449 legacy_set_pcislot(child, slot);
450 legacy_set_pcifunc(child, func);
451
452 found = 1;
453 if (id == 0x12258086)
454 found824xx = 1;
455 if (id == 0x84c48086)
456 found_orion = 1;
457 }
458 }
459 if (found824xx && bus == 0) {
460 bus++;
461 goto retry;
462 }
463
464 /*
465 * Make sure we add at least one bridge since some old
466 * hardware doesn't actually have a host-pci bridge device.
467 * Note that pci_cfgregopen() thinks we have PCI devices..
468 */
469 if (!found) {
470 if (bootverbose)
471 printf(
472 "legacy_pcib_identify: no bridge found, adding pcib0 anyway\n");
473 child = BUS_ADD_CHILD(parent, 100, "pcib", 0);
474 legacy_set_pcibus(child, 0);
475 }
476 }
477
478 static int
479 legacy_pcib_probe(device_t dev)
480 {
481
482 if (pci_cfgregopen() == 0)
483 return ENXIO;
484 return -100;
485 }
486
487 static int
488 legacy_pcib_attach(device_t dev)
489 {
490 device_t pir;
491 int bus;
492
493 /*
494 * Look for a PCI BIOS interrupt routing table as that will be
495 * our method of routing interrupts if we have one.
496 */
497 bus = pcib_get_bus(dev);
498 if (pci_pir_probe(bus, 0)) {
499 pir = BUS_ADD_CHILD(device_get_parent(dev), 0, "pir", 0);
500 if (pir != NULL)
501 device_probe_and_attach(pir);
502 }
503 device_add_child(dev, "pci", bus);
504 return bus_generic_attach(dev);
505 }
506
507 int
508 legacy_pcib_read_ivar(device_t dev, device_t child, int which,
509 uintptr_t *result)
510 {
511
512 switch (which) {
513 case PCIB_IVAR_DOMAIN:
514 *result = 0;
515 return 0;
516 case PCIB_IVAR_BUS:
517 *result = legacy_get_pcibus(dev);
518 return 0;
519 }
520 return ENOENT;
521 }
522
523 int
524 legacy_pcib_write_ivar(device_t dev, device_t child, int which,
525 uintptr_t value)
526 {
527
528 switch (which) {
529 case PCIB_IVAR_DOMAIN:
530 return EINVAL;
531 case PCIB_IVAR_BUS:
532 legacy_set_pcibus(dev, value);
533 return 0;
534 }
535 return ENOENT;
536 }
537
538 SYSCTL_DECL(_hw_pci);
539
540 static unsigned long legacy_host_mem_start = 0x80000000;
541 TUNABLE_ULONG("hw.pci.host_mem_start", &legacy_host_mem_start);
542 SYSCTL_ULONG(_hw_pci, OID_AUTO, host_mem_start, CTLFLAG_RDTUN,
543 &legacy_host_mem_start, 0x80000000,
544 "Limit the host bridge memory to being above this address. Must be\n\
545 set at boot via a tunable.");
546
547 struct resource *
548 legacy_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
549 u_long start, u_long end, u_long count, u_int flags)
550 {
551 /*
552 * If no memory preference is given, use upper 32MB slot most
553 * bioses use for their memory window. Typically other bridges
554 * before us get in the way to assert their preferences on memory.
555 * Hardcoding like this sucks, so a more MD/MI way needs to be
556 * found to do it. This is typically only used on older laptops
557 * that don't have pci busses behind pci bridge, so assuming > 32MB
558 * is liekly OK.
559 *
560 * However, this can cause problems for other chipsets, so we make
561 * this tunable by hw.pci.host_mem_start.
562 */
563 if (type == SYS_RES_MEMORY && start == 0UL && end == ~0UL)
564 start = legacy_host_mem_start;
565 if (type == SYS_RES_IOPORT && start == 0UL && end == ~0UL)
566 start = 0x1000;
567 return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
568 count, flags));
569 }
570
571 static device_method_t legacy_pcib_methods[] = {
572 /* Device interface */
573 DEVMETHOD(device_identify, legacy_pcib_identify),
574 DEVMETHOD(device_probe, legacy_pcib_probe),
575 DEVMETHOD(device_attach, legacy_pcib_attach),
576 DEVMETHOD(device_shutdown, bus_generic_shutdown),
577 DEVMETHOD(device_suspend, bus_generic_suspend),
578 DEVMETHOD(device_resume, bus_generic_resume),
579
580 /* Bus interface */
581 DEVMETHOD(bus_read_ivar, legacy_pcib_read_ivar),
582 DEVMETHOD(bus_write_ivar, legacy_pcib_write_ivar),
583 DEVMETHOD(bus_alloc_resource, legacy_pcib_alloc_resource),
584 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
585 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
586 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
587 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
588 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
589 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
590
591 /* pcib interface */
592 DEVMETHOD(pcib_maxslots, legacy_pcib_maxslots),
593 DEVMETHOD(pcib_read_config, legacy_pcib_read_config),
594 DEVMETHOD(pcib_write_config, legacy_pcib_write_config),
595 DEVMETHOD(pcib_route_interrupt, pcibios_pcib_route_interrupt),
596 DEVMETHOD(pcib_alloc_msi, legacy_pcib_alloc_msi),
597 DEVMETHOD(pcib_release_msi, pcib_release_msi),
598 DEVMETHOD(pcib_alloc_msix, legacy_pcib_alloc_msix),
599 DEVMETHOD(pcib_release_msix, pcib_release_msix),
600 DEVMETHOD(pcib_map_msi, legacy_pcib_map_msi),
601
602 DEVMETHOD_END
603 };
604
605 static devclass_t hostb_devclass;
606
607 DEFINE_CLASS_0(pcib, legacy_pcib_driver, legacy_pcib_methods, 1);
608 DRIVER_MODULE(pcib, legacy, legacy_pcib_driver, hostb_devclass, 0, 0);
609
610
611 /*
612 * Install placeholder to claim the resources owned by the
613 * PCI bus interface. This could be used to extract the
614 * config space registers in the extreme case where the PnP
615 * ID is available and the PCI BIOS isn't, but for now we just
616 * eat the PnP ID and do nothing else.
617 *
618 * XXX we should silence this probe, as it will generally confuse
619 * people.
620 */
621 static struct isa_pnp_id pcibus_pnp_ids[] = {
622 { 0x030ad041 /* PNP0A03 */, "PCI Bus" },
623 { 0x080ad041 /* PNP0A08 */, "PCIe Bus" },
624 { 0 }
625 };
626
627 static int
628 pcibus_pnp_probe(device_t dev)
629 {
630 int result;
631
632 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, pcibus_pnp_ids)) <= 0)
633 device_quiet(dev);
634 return(result);
635 }
636
637 static int
638 pcibus_pnp_attach(device_t dev)
639 {
640 return(0);
641 }
642
643 static device_method_t pcibus_pnp_methods[] = {
644 /* Device interface */
645 DEVMETHOD(device_probe, pcibus_pnp_probe),
646 DEVMETHOD(device_attach, pcibus_pnp_attach),
647 DEVMETHOD(device_detach, bus_generic_detach),
648 DEVMETHOD(device_shutdown, bus_generic_shutdown),
649 DEVMETHOD(device_suspend, bus_generic_suspend),
650 DEVMETHOD(device_resume, bus_generic_resume),
651 { 0, 0 }
652 };
653
654 static devclass_t pcibus_pnp_devclass;
655
656 DEFINE_CLASS_0(pcibus_pnp, pcibus_pnp_driver, pcibus_pnp_methods, 1);
657 DRIVER_MODULE(pcibus_pnp, isa, pcibus_pnp_driver, pcibus_pnp_devclass, 0, 0);
658
659
660 /*
661 * Provide a PCI-PCI bridge driver for PCI busses behind PCI-PCI bridges
662 * that appear in the PCIBIOS Interrupt Routing Table to use the routing
663 * table for interrupt routing when possible.
664 */
665 static int pcibios_pcib_probe(device_t bus);
666
667 static device_method_t pcibios_pcib_pci_methods[] = {
668 /* Device interface */
669 DEVMETHOD(device_probe, pcibios_pcib_probe),
670 DEVMETHOD(device_attach, pcib_attach),
671 DEVMETHOD(device_shutdown, bus_generic_shutdown),
672 DEVMETHOD(device_suspend, bus_generic_suspend),
673 DEVMETHOD(device_resume, bus_generic_resume),
674
675 /* Bus interface */
676 DEVMETHOD(bus_read_ivar, pcib_read_ivar),
677 DEVMETHOD(bus_write_ivar, pcib_write_ivar),
678 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource),
679 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
680 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
681 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
682 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
683 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
684
685 /* pcib interface */
686 DEVMETHOD(pcib_maxslots, pcib_maxslots),
687 DEVMETHOD(pcib_read_config, pcib_read_config),
688 DEVMETHOD(pcib_write_config, pcib_write_config),
689 DEVMETHOD(pcib_route_interrupt, pcibios_pcib_route_interrupt),
690 DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi),
691 DEVMETHOD(pcib_release_msi, pcib_release_msi),
692 DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix),
693 DEVMETHOD(pcib_release_msix, pcib_release_msix),
694 DEVMETHOD(pcib_map_msi, pcib_map_msi),
695
696 DEVMETHOD_END
697 };
698
699 static devclass_t pcib_devclass;
700
701 DEFINE_CLASS_0(pcib, pcibios_pcib_driver, pcibios_pcib_pci_methods,
702 sizeof(struct pcib_softc));
703 DRIVER_MODULE(pcibios_pcib, pci, pcibios_pcib_driver, pcib_devclass, 0, 0);
704
705 static int
706 pcibios_pcib_probe(device_t dev)
707 {
708 int bus;
709
710 if ((pci_get_class(dev) != PCIC_BRIDGE) ||
711 (pci_get_subclass(dev) != PCIS_BRIDGE_PCI))
712 return (ENXIO);
713 bus = pci_read_config(dev, PCIR_SECBUS_1, 1);
714 if (bus == 0)
715 return (ENXIO);
716 if (!pci_pir_probe(bus, 1))
717 return (ENXIO);
718 device_set_desc(dev, "PCIBIOS PCI-PCI bridge");
719 return (-2000);
720 }
721
722 static int
723 pcibios_pcib_route_interrupt(device_t pcib, device_t dev, int pin)
724 {
725 return (pci_pir_route_interrupt(pci_get_bus(dev), pci_get_slot(dev),
726 pci_get_function(dev), pin));
727 }
Cache object: b7a2e3b292d7163f88da251c55214002
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