1 /*
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000, BSDi
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
12 * disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * $FreeBSD: releng/5.0/sys/i386/pci/pci_cfgreg.c 106901 2002-11-14 05:22:37Z imp $
29 *
30 */
31
32 #include <sys/param.h> /* XXX trim includes */
33 #include <sys/systm.h>
34 #include <sys/bus.h>
35 #include <sys/kernel.h>
36 #include <sys/module.h>
37 #include <sys/malloc.h>
38 #include <vm/vm.h>
39 #include <vm/pmap.h>
40 #include <machine/md_var.h>
41 #include <dev/pci/pcivar.h>
42 #include <dev/pci/pcireg.h>
43 #include <isa/isavar.h>
44 #include <machine/pci_cfgreg.h>
45 #include <machine/segments.h>
46 #include <machine/pc/bios.h>
47
48 #ifdef APIC_IO
49 #include <machine/smp.h>
50 #endif /* APIC_IO */
51
52 #include "pcib_if.h"
53
54 #define PRVERB(a) do { \
55 if (bootverbose) \
56 printf a ; \
57 } while(0)
58
59 static int cfgmech;
60 static int devmax;
61 static int usebios;
62 static int enable_pcibios = 0;
63
64 TUNABLE_INT("hw.pci.enable_pcibios", &enable_pcibios);
65
66 static int pci_cfgintr_valid(struct PIR_entry *pe, int pin, int irq);
67 static int pci_cfgintr_unique(struct PIR_entry *pe, int pin);
68 static int pci_cfgintr_linked(struct PIR_entry *pe, int pin);
69 static int pci_cfgintr_search(struct PIR_entry *pe, int bus, int device, int matchpin, int pin);
70 static int pci_cfgintr_virgin(struct PIR_entry *pe, int pin);
71
72 static void pci_print_irqmask(u_int16_t irqs);
73 static void pci_print_route_table(struct PIR_table *prt, int size);
74 #ifdef USE_PCI_BIOS_FOR_READ_WRITE
75 static int pcibios_cfgread(int bus, int slot, int func, int reg, int bytes);
76 static void pcibios_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
77 #endif
78 static int pcibios_cfgopen(void);
79 static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);
80 static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
81 static int pcireg_cfgopen(void);
82
83 static struct PIR_table *pci_route_table;
84 static int pci_route_count;
85
86 /*
87 * Some BIOS writers seem to want to ignore the spec and put
88 * 0 in the intline rather than 255 to indicate none. Some use
89 * numbers in the range 128-254 to indicate something strange and
90 * apparently undocumented anywhere. Assume these are completely bogus
91 * and map them to 255, which means "none".
92 */
93 static __inline__ int
94 pci_i386_map_intline(int line)
95 {
96 if (line == 0 || line >= 128)
97 return (PCI_INVALID_IRQ);
98 return (line);
99 }
100
101 int
102 pci_pcibios_active(void)
103 {
104 return (usebios);
105 }
106
107 int
108 pci_kill_pcibios(void)
109 {
110 usebios = 0;
111 return (pcireg_cfgopen() != 0);
112 }
113
114 static u_int16_t
115 pcibios_get_version(void)
116 {
117 struct bios_regs args;
118
119 if (PCIbios.ventry == 0) {
120 PRVERB(("pcibios: No call entry point\n"));
121 return (0);
122 }
123 args.eax = PCIBIOS_BIOS_PRESENT;
124 if (bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL))) {
125 PRVERB(("pcibios: BIOS_PRESENT call failed\n"));
126 return (0);
127 }
128 if (args.edx != 0x20494350) {
129 PRVERB(("pcibios: BIOS_PRESENT didn't return 'PCI ' in edx\n"));
130 return (0);
131 }
132 return (args.ebx & 0xffff);
133 }
134
135 /*
136 * Initialise access to PCI configuration space
137 */
138 int
139 pci_cfgregopen(void)
140 {
141 static int opened = 0;
142 u_long sigaddr;
143 static struct PIR_table *pt;
144 u_int8_t ck, *cv;
145 int i;
146
147 if (opened)
148 return(1);
149
150 if (pcibios_cfgopen() != 0)
151 usebios = 1;
152 else if (pcireg_cfgopen() != 0)
153 usebios = 0;
154 else
155 return(0);
156
157 /*
158 * Look for the interrupt routing table.
159 *
160 * We use PCI BIOS's PIR table if it's available $PIR is the
161 * standard way to do this. Sadly, some machines are not
162 * standards conforming and have _PIR instead. We shrug and cope
163 * by looking for both.
164 */
165 if (pcibios_get_version() >= 0x0210 && pt == NULL) {
166 sigaddr = bios_sigsearch(0, "$PIR", 4, 16, 0);
167 if (sigaddr == 0)
168 sigaddr = bios_sigsearch(0, "_PIR", 4, 16, 0);
169 if (sigaddr != 0) {
170 pt = (struct PIR_table *)(uintptr_t)
171 BIOS_PADDRTOVADDR(sigaddr);
172 for (cv = (u_int8_t *)pt, ck = 0, i = 0;
173 i < (pt->pt_header.ph_length); i++) {
174 ck += cv[i];
175 }
176 if (ck == 0 && pt->pt_header.ph_length >
177 sizeof(struct PIR_header)) {
178 pci_route_table = pt;
179 pci_route_count = (pt->pt_header.ph_length -
180 sizeof(struct PIR_header)) /
181 sizeof(struct PIR_entry);
182 printf("Using $PIR table, %d entries at %p\n",
183 pci_route_count, pci_route_table);
184 if (bootverbose)
185 pci_print_route_table(pci_route_table,
186 pci_route_count);
187 }
188 }
189 }
190 opened = 1;
191 return(1);
192 }
193
194 /*
195 * Read configuration space register
196 */
197 static u_int32_t
198 pci_do_cfgregread(int bus, int slot, int func, int reg, int bytes)
199 {
200 #ifdef USE_PCI_BIOS_FOR_READ_WRITE
201 return(usebios ?
202 pcibios_cfgread(bus, slot, func, reg, bytes) :
203 pcireg_cfgread(bus, slot, func, reg, bytes));
204 #else
205 return (pcireg_cfgread(bus, slot, func, reg, bytes));
206 #endif
207 }
208
209 u_int32_t
210 pci_cfgregread(int bus, int slot, int func, int reg, int bytes)
211 {
212 uint32_t line;
213 #ifdef APIC_IO
214 uint32_t pin;
215
216 /*
217 * If we are using the APIC, the contents of the intline
218 * register will probably be wrong (since they are set up for
219 * use with the PIC. Rather than rewrite these registers
220 * (maybe that would be smarter) we trap attempts to read them
221 * and translate to our private vector numbers.
222 */
223 if ((reg == PCIR_INTLINE) && (bytes == 1)) {
224
225 pin = pci_do_cfgregread(bus, slot, func, PCIR_INTPIN, 1);
226 line = pci_do_cfgregread(bus, slot, func, PCIR_INTLINE, 1);
227
228 if (pin != 0) {
229 int airq;
230
231 airq = pci_apic_irq(bus, slot, pin);
232 if (airq >= 0) {
233 /* PCI specific entry found in MP table */
234 if (airq != line)
235 undirect_pci_irq(line);
236 return(airq);
237 } else {
238 /*
239 * PCI interrupts might be redirected
240 * to the ISA bus according to some MP
241 * tables. Use the same methods as
242 * used by the ISA devices devices to
243 * find the proper IOAPIC int pin.
244 */
245 airq = isa_apic_irq(line);
246 if ((airq >= 0) && (airq != line)) {
247 /* XXX: undirect_pci_irq() ? */
248 undirect_isa_irq(line);
249 return(airq);
250 }
251 }
252 }
253 return(line);
254 }
255 #else
256 /*
257 * Some BIOS writers seem to want to ignore the spec and put
258 * 0 in the intline rather than 255 to indicate none. The rest of
259 * the code uses 255 as an invalid IRQ.
260 */
261 if (reg == PCIR_INTLINE && bytes == 1) {
262 line = pci_do_cfgregread(bus, slot, func, PCIR_INTLINE, 1);
263 return pci_i386_map_intline(line);
264 }
265 #endif /* APIC_IO */
266 return(pci_do_cfgregread(bus, slot, func, reg, bytes));
267 }
268
269 /*
270 * Write configuration space register
271 */
272 void
273 pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes)
274 {
275 #ifdef USE_PCI_BIOS_FOR_READ_WRITE
276 if (usebios)
277 pcibios_cfgwrite(bus, slot, func, reg, data, bytes);
278 else
279 pcireg_cfgwrite(bus, slot, func, reg, data, bytes);
280 #else
281 pcireg_cfgwrite(bus, slot, func, reg, data, bytes);
282 #endif
283 }
284
285 /*
286 * Route a PCI interrupt
287 */
288 int
289 pci_cfgintr(int bus, int device, int pin, int oldirq)
290 {
291 struct PIR_entry *pe;
292 int i, irq;
293 struct bios_regs args;
294 u_int16_t v;
295 int already = 0;
296 int errok = 0;
297
298 v = pcibios_get_version();
299 if (v < 0x0210) {
300 PRVERB((
301 "pci_cfgintr: BIOS %x.%02x doesn't support interrupt routing\n",
302 (v & 0xff00) >> 8, v & 0xff));
303 return (PCI_INVALID_IRQ);
304 }
305 if ((bus < 0) || (bus > 255) || (device < 0) || (device > 255) ||
306 (pin < 1) || (pin > 4))
307 return(PCI_INVALID_IRQ);
308
309 /*
310 * Scan the entry table for a contender
311 */
312 for (i = 0, pe = &pci_route_table->pt_entry[0]; i < pci_route_count;
313 i++, pe++) {
314 if ((bus != pe->pe_bus) || (device != pe->pe_device))
315 continue;
316 /*
317 * A link of 0 means that this intpin is not connected to
318 * any other device's interrupt pins and is not connected to
319 * any of the Interrupt Router's interrupt pins, so we can't
320 * route it.
321 */
322 if (pe->pe_intpin[pin - 1].link == 0)
323 continue;
324
325 if (pci_cfgintr_valid(pe, pin, oldirq)) {
326 printf("pci_cfgintr: %d:%d INT%c BIOS irq %d\n", bus,
327 device, 'A' + pin - 1, oldirq);
328 return (oldirq);
329 }
330
331 /*
332 * We try to find a linked interrupt, then we look to see
333 * if the interrupt is uniquely routed, then we look for
334 * a virgin interrupt. The virgin interrupt should return
335 * an interrupt we can route, but if that fails, maybe we
336 * should try harder to route a different interrupt.
337 * However, experience has shown that that's rarely the
338 * failure mode we see.
339 */
340 irq = pci_cfgintr_linked(pe, pin);
341 if (irq != PCI_INVALID_IRQ)
342 already = 1;
343 if (irq == PCI_INVALID_IRQ) {
344 irq = pci_cfgintr_unique(pe, pin);
345 if (irq != PCI_INVALID_IRQ)
346 errok = 1;
347 }
348 if (irq == PCI_INVALID_IRQ)
349 irq = pci_cfgintr_virgin(pe, pin);
350 if (irq == PCI_INVALID_IRQ)
351 break;
352
353 /*
354 * Ask the BIOS to route the interrupt. If we picked an
355 * interrupt that failed, we should really try other
356 * choices that the BIOS offers us.
357 *
358 * For uniquely routed interrupts, we need to try
359 * to route them on some machines. Yet other machines
360 * fail to route, so we have to pretend that in that
361 * case it worked. Isn't pc hardware fun?
362 *
363 * NOTE: if we want to whack hardware to do this, then
364 * I think the right way to do that would be to have
365 * bridge drivers that do this. I'm not sure that the
366 * $PIR table would be valid for those interrupt
367 * routers.
368 */
369 args.eax = PCIBIOS_ROUTE_INTERRUPT;
370 args.ebx = (bus << 8) | (device << 3);
371 /* pin value is 0xa - 0xd */
372 args.ecx = (irq << 8) | (0xa + pin - 1);
373 if (!already &&
374 bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL)) &&
375 !errok) {
376 PRVERB(("pci_cfgintr: ROUTE_INTERRUPT failed.\n"));
377 return(PCI_INVALID_IRQ);
378 }
379 printf("pci_cfgintr: %d:%d INT%c routed to irq %d\n", bus,
380 device, 'A' + pin - 1, irq);
381 return(irq);
382 }
383
384 PRVERB(("pci_cfgintr: can't route an interrupt to %d:%d INT%c\n", bus,
385 device, 'A' + pin - 1));
386 return(PCI_INVALID_IRQ);
387 }
388
389 /*
390 * Check to see if an existing IRQ setting is valid.
391 */
392 static int
393 pci_cfgintr_valid(struct PIR_entry *pe, int pin, int irq)
394 {
395 uint32_t irqmask;
396
397 if (!PCI_INTERRUPT_VALID(irq))
398 return (0);
399 irqmask = pe->pe_intpin[pin - 1].irqs;
400 if (irqmask & (1 << irq)) {
401 PRVERB(("pci_cfgintr_valid: BIOS irq %d is valid\n", irq));
402 return (1);
403 }
404 return (0);
405 }
406
407 /*
408 * Look to see if the routing table claims this pin is uniquely routed.
409 */
410 static int
411 pci_cfgintr_unique(struct PIR_entry *pe, int pin)
412 {
413 int irq;
414 uint32_t irqmask;
415
416 irqmask = pe->pe_intpin[pin - 1].irqs;
417 if (irqmask != 0 && powerof2(irqmask)) {
418 irq = ffs(irqmask) - 1;
419 PRVERB(("pci_cfgintr_unique: hard-routed to irq %d\n", irq));
420 return(irq);
421 }
422 return(PCI_INVALID_IRQ);
423 }
424
425 /*
426 * Look for another device which shares the same link byte and
427 * already has a unique IRQ, or which has had one routed already.
428 */
429 static int
430 pci_cfgintr_linked(struct PIR_entry *pe, int pin)
431 {
432 struct PIR_entry *oe;
433 struct PIR_intpin *pi;
434 int i, j, irq;
435
436 /*
437 * Scan table slots.
438 */
439 for (i = 0, oe = &pci_route_table->pt_entry[0]; i < pci_route_count;
440 i++, oe++) {
441 /* scan interrupt pins */
442 for (j = 0, pi = &oe->pe_intpin[0]; j < 4; j++, pi++) {
443
444 /* don't look at the entry we're trying to match */
445 if ((pe == oe) && (i == (pin - 1)))
446 continue;
447 /* compare link bytes */
448 if (pi->link != pe->pe_intpin[pin - 1].link)
449 continue;
450 /* link destination mapped to a unique interrupt? */
451 if (pi->irqs != 0 && powerof2(pi->irqs)) {
452 irq = ffs(pi->irqs) - 1;
453 PRVERB(("pci_cfgintr_linked: linked (%x) to hard-routed irq %d\n",
454 pi->link, irq));
455 return(irq);
456 }
457
458 /*
459 * look for the real PCI device that matches this
460 * table entry
461 */
462 irq = pci_cfgintr_search(pe, oe->pe_bus, oe->pe_device,
463 j, pin);
464 if (irq != PCI_INVALID_IRQ)
465 return(irq);
466 }
467 }
468 return(PCI_INVALID_IRQ);
469 }
470
471 /*
472 * Scan for the real PCI device at (bus)/(device) using intpin (matchpin) and
473 * see if it has already been assigned an interrupt.
474 */
475 static int
476 pci_cfgintr_search(struct PIR_entry *pe, int bus, int device, int matchpin, int pin)
477 {
478 devclass_t pci_devclass;
479 device_t *pci_devices;
480 int pci_count;
481 device_t *pci_children;
482 int pci_childcount;
483 device_t *busp, *childp;
484 int i, j, irq;
485
486 /*
487 * Find all the PCI busses.
488 */
489 pci_count = 0;
490 if ((pci_devclass = devclass_find("pci")) != NULL)
491 devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
492
493 /*
494 * Scan all the PCI busses/devices looking for this one.
495 */
496 irq = PCI_INVALID_IRQ;
497 for (i = 0, busp = pci_devices; (i < pci_count) && (irq == PCI_INVALID_IRQ);
498 i++, busp++) {
499 pci_childcount = 0;
500 device_get_children(*busp, &pci_children, &pci_childcount);
501
502 for (j = 0, childp = pci_children; j < pci_childcount; j++,
503 childp++) {
504 if ((pci_get_bus(*childp) == bus) &&
505 (pci_get_slot(*childp) == device) &&
506 (pci_get_intpin(*childp) == matchpin)) {
507 irq = pci_i386_map_intline(pci_get_irq(*childp));
508 if (irq != PCI_INVALID_IRQ)
509 PRVERB(("pci_cfgintr_search: linked (%x) to configured irq %d at %d:%d:%d\n",
510 pe->pe_intpin[pin - 1].link, irq,
511 pci_get_bus(*childp),
512 pci_get_slot(*childp),
513 pci_get_function(*childp)));
514 break;
515 }
516 }
517 if (pci_children != NULL)
518 free(pci_children, M_TEMP);
519 }
520 if (pci_devices != NULL)
521 free(pci_devices, M_TEMP);
522 return(irq);
523 }
524
525 /*
526 * Pick a suitable IRQ from those listed as routable to this device.
527 */
528 static int
529 pci_cfgintr_virgin(struct PIR_entry *pe, int pin)
530 {
531 int irq, ibit;
532
533 /*
534 * first scan the set of PCI-only interrupts and see if any of these
535 * are routable
536 */
537 for (irq = 0; irq < 16; irq++) {
538 ibit = (1 << irq);
539
540 /* can we use this interrupt? */
541 if ((pci_route_table->pt_header.ph_pci_irqs & ibit) &&
542 (pe->pe_intpin[pin - 1].irqs & ibit)) {
543 PRVERB(("pci_cfgintr_virgin: using routable PCI-only interrupt %d\n", irq));
544 return(irq);
545 }
546 }
547
548 /* life is tough, so just pick an interrupt */
549 for (irq = 0; irq < 16; irq++) {
550 ibit = (1 << irq);
551 if (pe->pe_intpin[pin - 1].irqs & ibit) {
552 PRVERB(("pci_cfgintr_virgin: using routable interrupt %d\n", irq));
553 return(irq);
554 }
555 }
556 return(PCI_INVALID_IRQ);
557 }
558
559 static void
560 pci_print_irqmask(u_int16_t irqs)
561 {
562 int i, first;
563
564 if (irqs == 0) {
565 printf("none");
566 return;
567 }
568 first = 1;
569 for (i = 0; i < 16; i++, irqs >>= 1)
570 if (irqs & 1) {
571 if (!first)
572 printf(" ");
573 else
574 first = 0;
575 printf("%d", i);
576 }
577 }
578
579 /*
580 * Dump the contents of a PCI BIOS Interrupt Routing Table to the console.
581 */
582 static void
583 pci_print_route_table(struct PIR_table *prt, int size)
584 {
585 struct PIR_entry *entry;
586 struct PIR_intpin *intpin;
587 int i, pin;
588
589 printf("PCI-Only Interrupts: ");
590 pci_print_irqmask(prt->pt_header.ph_pci_irqs);
591 printf("\nLocation Bus Device Pin Link IRQs\n");
592 entry = &prt->pt_entry[0];
593 for (i = 0; i < size; i++, entry++) {
594 intpin = &entry->pe_intpin[0];
595 for (pin = 0; pin < 4; pin++, intpin++)
596 if (intpin->link != 0) {
597 if (entry->pe_slot == 0)
598 printf("embedded ");
599 else
600 printf("slot %-3d ", entry->pe_slot);
601 printf(" %3d %3d %c 0x%02x ",
602 entry->pe_bus, entry->pe_device,
603 'A' + pin, intpin->link);
604 pci_print_irqmask(intpin->irqs);
605 printf("\n");
606 }
607 }
608 }
609
610 /*
611 * See if any interrupts for a given PCI bus are routed in the PIR. Don't
612 * even bother looking if the BIOS doesn't support routing anyways.
613 */
614 int
615 pci_probe_route_table(int bus)
616 {
617 int i;
618 u_int16_t v;
619
620 v = pcibios_get_version();
621 if (v < 0x0210)
622 return (0);
623 for (i = 0; i < pci_route_count; i++)
624 if (pci_route_table->pt_entry[i].pe_bus == bus)
625 return (1);
626 return (0);
627 }
628
629 #ifdef USE_PCI_BIOS_FOR_READ_WRITE
630 /*
631 * Config space access using BIOS functions
632 */
633 static int
634 pcibios_cfgread(int bus, int slot, int func, int reg, int bytes)
635 {
636 struct bios_regs args;
637 u_int mask;
638
639 switch(bytes) {
640 case 1:
641 args.eax = PCIBIOS_READ_CONFIG_BYTE;
642 mask = 0xff;
643 break;
644 case 2:
645 args.eax = PCIBIOS_READ_CONFIG_WORD;
646 mask = 0xffff;
647 break;
648 case 4:
649 args.eax = PCIBIOS_READ_CONFIG_DWORD;
650 mask = 0xffffffff;
651 break;
652 default:
653 return(-1);
654 }
655 args.ebx = (bus << 8) | (slot << 3) | func;
656 args.edi = reg;
657 bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL));
658 /* check call results? */
659 return(args.ecx & mask);
660 }
661
662 static void
663 pcibios_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
664 {
665 struct bios_regs args;
666
667 switch(bytes) {
668 case 1:
669 args.eax = PCIBIOS_WRITE_CONFIG_BYTE;
670 break;
671 case 2:
672 args.eax = PCIBIOS_WRITE_CONFIG_WORD;
673 break;
674 case 4:
675 args.eax = PCIBIOS_WRITE_CONFIG_DWORD;
676 break;
677 default:
678 return;
679 }
680 args.ebx = (bus << 8) | (slot << 3) | func;
681 args.ecx = data;
682 args.edi = reg;
683 bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL));
684 }
685 #endif
686
687 /*
688 * Determine whether there is a PCI BIOS present
689 */
690 static int
691 pcibios_cfgopen(void)
692 {
693 u_int16_t v = 0;
694
695 if (PCIbios.ventry != 0 && enable_pcibios) {
696 v = pcibios_get_version();
697 if (v > 0)
698 printf("pcibios: BIOS version %x.%02x\n",
699 (v & 0xff00) >> 8, v & 0xff);
700 }
701 return (v > 0);
702 }
703
704 /*
705 * Configuration space access using direct register operations
706 */
707
708 /* enable configuration space accesses and return data port address */
709 static int
710 pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
711 {
712 int dataport = 0;
713
714 if (bus <= PCI_BUSMAX
715 && slot < devmax
716 && func <= PCI_FUNCMAX
717 && reg <= PCI_REGMAX
718 && bytes != 3
719 && (unsigned) bytes <= 4
720 && (reg & (bytes - 1)) == 0) {
721 switch (cfgmech) {
722 case 1:
723 outl(CONF1_ADDR_PORT, (1 << 31)
724 | (bus << 16) | (slot << 11)
725 | (func << 8) | (reg & ~0x03));
726 dataport = CONF1_DATA_PORT + (reg & 0x03);
727 break;
728 case 2:
729 outb(CONF2_ENABLE_PORT, 0xf0 | (func << 1));
730 outb(CONF2_FORWARD_PORT, bus);
731 dataport = 0xc000 | (slot << 8) | reg;
732 break;
733 }
734 }
735 return (dataport);
736 }
737
738 /* disable configuration space accesses */
739 static void
740 pci_cfgdisable(void)
741 {
742 switch (cfgmech) {
743 case 1:
744 outl(CONF1_ADDR_PORT, 0);
745 break;
746 case 2:
747 outb(CONF2_ENABLE_PORT, 0);
748 outb(CONF2_FORWARD_PORT, 0);
749 break;
750 }
751 }
752
753 static int
754 pcireg_cfgread(int bus, int slot, int func, int reg, int bytes)
755 {
756 int data = -1;
757 int port;
758
759 port = pci_cfgenable(bus, slot, func, reg, bytes);
760
761 if (port != 0) {
762 switch (bytes) {
763 case 1:
764 data = inb(port);
765 break;
766 case 2:
767 data = inw(port);
768 break;
769 case 4:
770 data = inl(port);
771 break;
772 }
773 pci_cfgdisable();
774 }
775 return (data);
776 }
777
778 static void
779 pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
780 {
781 int port;
782
783 port = pci_cfgenable(bus, slot, func, reg, bytes);
784 if (port != 0) {
785 switch (bytes) {
786 case 1:
787 outb(port, data);
788 break;
789 case 2:
790 outw(port, data);
791 break;
792 case 4:
793 outl(port, data);
794 break;
795 }
796 pci_cfgdisable();
797 }
798 }
799
800 /* check whether the configuration mechanism has been correctly identified */
801 static int
802 pci_cfgcheck(int maxdev)
803 {
804 uint32_t id, class;
805 uint8_t header;
806 uint8_t device;
807
808 if (bootverbose)
809 printf("pci_cfgcheck:\tdevice ");
810
811 for (device = 0; device < maxdev; device++) {
812 if (bootverbose)
813 printf("%d ", device);
814
815 id = inl(pci_cfgenable(0, device, 0, 0, 4));
816 if (id == 0 || id == 0xffffffff)
817 continue;
818
819 class = inl(pci_cfgenable(0, device, 0, 8, 4)) >> 8;
820 if (bootverbose)
821 printf("[class=%06x] ", class);
822 if (class == 0 || (class & 0xf870ff) != 0)
823 continue;
824
825 header = inb(pci_cfgenable(0, device, 0, 14, 1));
826 if (bootverbose)
827 printf("[hdr=%02x] ", header);
828 if ((header & 0x7e) != 0)
829 continue;
830
831 if (bootverbose)
832 printf("is there (id=%08x)\n", id);
833
834 pci_cfgdisable();
835 return (1);
836 }
837 if (bootverbose)
838 printf("-- nothing found\n");
839
840 pci_cfgdisable();
841 return (0);
842 }
843
844 static int
845 pcireg_cfgopen(void)
846 {
847 uint32_t mode1res, oldval1;
848 uint8_t mode2res, oldval2;
849
850 oldval1 = inl(CONF1_ADDR_PORT);
851
852 if (bootverbose) {
853 printf("pci_open(1):\tmode 1 addr port (0x0cf8) is 0x%08x\n",
854 oldval1);
855 }
856
857 if ((oldval1 & CONF1_ENABLE_MSK) == 0) {
858
859 cfgmech = 1;
860 devmax = 32;
861
862 outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK);
863 outb(CONF1_ADDR_PORT + 3, 0);
864 mode1res = inl(CONF1_ADDR_PORT);
865 outl(CONF1_ADDR_PORT, oldval1);
866
867 if (bootverbose)
868 printf("pci_open(1a):\tmode1res=0x%08x (0x%08lx)\n",
869 mode1res, CONF1_ENABLE_CHK);
870
871 if (mode1res) {
872 if (pci_cfgcheck(32))
873 return (cfgmech);
874 }
875
876 outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK1);
877 mode1res = inl(CONF1_ADDR_PORT);
878 outl(CONF1_ADDR_PORT, oldval1);
879
880 if (bootverbose)
881 printf("pci_open(1b):\tmode1res=0x%08x (0x%08lx)\n",
882 mode1res, CONF1_ENABLE_CHK1);
883
884 if ((mode1res & CONF1_ENABLE_MSK1) == CONF1_ENABLE_RES1) {
885 if (pci_cfgcheck(32))
886 return (cfgmech);
887 }
888 }
889
890 oldval2 = inb(CONF2_ENABLE_PORT);
891
892 if (bootverbose) {
893 printf("pci_open(2):\tmode 2 enable port (0x0cf8) is 0x%02x\n",
894 oldval2);
895 }
896
897 if ((oldval2 & 0xf0) == 0) {
898
899 cfgmech = 2;
900 devmax = 16;
901
902 outb(CONF2_ENABLE_PORT, CONF2_ENABLE_CHK);
903 mode2res = inb(CONF2_ENABLE_PORT);
904 outb(CONF2_ENABLE_PORT, oldval2);
905
906 if (bootverbose)
907 printf("pci_open(2a):\tmode2res=0x%02x (0x%02x)\n",
908 mode2res, CONF2_ENABLE_CHK);
909
910 if (mode2res == CONF2_ENABLE_RES) {
911 if (bootverbose)
912 printf("pci_open(2a):\tnow trying mechanism 2\n");
913
914 if (pci_cfgcheck(16))
915 return (cfgmech);
916 }
917 }
918
919 cfgmech = 0;
920 devmax = 0;
921 return (cfgmech);
922 }
923
Cache object: 8a86dd0a58ceb59ee784c8a8efaa5a9d
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