1 /*
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000, BSDi
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
12 * disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * $FreeBSD: releng/5.1/sys/i386/pci/pci_cfgreg.c 111068 2003-02-18 03:36:49Z peter $
29 *
30 */
31
32 #include <sys/param.h> /* XXX trim includes */
33 #include <sys/systm.h>
34 #include <sys/bus.h>
35 #include <sys/kernel.h>
36 #include <sys/module.h>
37 #include <sys/malloc.h>
38 #include <sys/lock.h>
39 #include <sys/mutex.h>
40 #include <vm/vm.h>
41 #include <vm/pmap.h>
42 #include <machine/md_var.h>
43 #include <dev/pci/pcivar.h>
44 #include <dev/pci/pcireg.h>
45 #include <isa/isavar.h>
46 #include <machine/pci_cfgreg.h>
47 #include <machine/segments.h>
48 #include <machine/pc/bios.h>
49
50 #ifdef APIC_IO
51 #include <machine/smp.h>
52 #endif /* APIC_IO */
53
54 #include "pcib_if.h"
55
56 #define PRVERB(a) do { \
57 if (bootverbose) \
58 printf a ; \
59 } while(0)
60
61 static int cfgmech;
62 static int devmax;
63
64 static int pci_cfgintr_valid(struct PIR_entry *pe, int pin, int irq);
65 static int pci_cfgintr_unique(struct PIR_entry *pe, int pin);
66 static int pci_cfgintr_linked(struct PIR_entry *pe, int pin);
67 static int pci_cfgintr_search(struct PIR_entry *pe, int bus, int device, int matchpin, int pin);
68 static int pci_cfgintr_virgin(struct PIR_entry *pe, int pin);
69
70 static void pci_print_irqmask(u_int16_t irqs);
71 static void pci_print_route_table(struct PIR_table *prt, int size);
72 static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);
73 static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
74 static int pcireg_cfgopen(void);
75
76 static struct PIR_table *pci_route_table;
77 static int pci_route_count;
78
79 static struct mtx pcicfg_mtx;
80
81 /*
82 * Some BIOS writers seem to want to ignore the spec and put
83 * 0 in the intline rather than 255 to indicate none. Some use
84 * numbers in the range 128-254 to indicate something strange and
85 * apparently undocumented anywhere. Assume these are completely bogus
86 * and map them to 255, which means "none".
87 */
88 static __inline__ int
89 pci_i386_map_intline(int line)
90 {
91 if (line == 0 || line >= 128)
92 return (PCI_INVALID_IRQ);
93 return (line);
94 }
95
96 static u_int16_t
97 pcibios_get_version(void)
98 {
99 struct bios_regs args;
100
101 if (PCIbios.ventry == 0) {
102 PRVERB(("pcibios: No call entry point\n"));
103 return (0);
104 }
105 args.eax = PCIBIOS_BIOS_PRESENT;
106 if (bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL))) {
107 PRVERB(("pcibios: BIOS_PRESENT call failed\n"));
108 return (0);
109 }
110 if (args.edx != 0x20494350) {
111 PRVERB(("pcibios: BIOS_PRESENT didn't return 'PCI ' in edx\n"));
112 return (0);
113 }
114 return (args.ebx & 0xffff);
115 }
116
117 /*
118 * Initialise access to PCI configuration space
119 */
120 int
121 pci_cfgregopen(void)
122 {
123 static int opened = 0;
124 u_long sigaddr;
125 static struct PIR_table *pt;
126 u_int16_t v;
127 u_int8_t ck, *cv;
128 int i;
129
130 if (opened)
131 return(1);
132
133 if (pcireg_cfgopen() == 0)
134 return(0);
135
136 v = pcibios_get_version();
137 if (v > 0)
138 printf("pcibios: BIOS version %x.%02x\n", (v & 0xff00) >> 8,
139 v & 0xff);
140
141 /*
142 * Look for the interrupt routing table.
143 *
144 * We use PCI BIOS's PIR table if it's available $PIR is the
145 * standard way to do this. Sadly, some machines are not
146 * standards conforming and have _PIR instead. We shrug and cope
147 * by looking for both.
148 */
149 if (pcibios_get_version() >= 0x0210 && pt == NULL) {
150 sigaddr = bios_sigsearch(0, "$PIR", 4, 16, 0);
151 if (sigaddr == 0)
152 sigaddr = bios_sigsearch(0, "_PIR", 4, 16, 0);
153 if (sigaddr != 0) {
154 pt = (struct PIR_table *)(uintptr_t)
155 BIOS_PADDRTOVADDR(sigaddr);
156 for (cv = (u_int8_t *)pt, ck = 0, i = 0;
157 i < (pt->pt_header.ph_length); i++) {
158 ck += cv[i];
159 }
160 if (ck == 0 && pt->pt_header.ph_length >
161 sizeof(struct PIR_header)) {
162 pci_route_table = pt;
163 pci_route_count = (pt->pt_header.ph_length -
164 sizeof(struct PIR_header)) /
165 sizeof(struct PIR_entry);
166 printf("Using $PIR table, %d entries at %p\n",
167 pci_route_count, pci_route_table);
168 if (bootverbose)
169 pci_print_route_table(pci_route_table,
170 pci_route_count);
171 }
172 }
173 }
174 mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN);
175 opened = 1;
176 return(1);
177 }
178
179 /*
180 * Read configuration space register
181 */
182 u_int32_t
183 pci_cfgregread(int bus, int slot, int func, int reg, int bytes)
184 {
185 uint32_t line;
186 #ifdef APIC_IO
187 uint32_t pin;
188
189 /*
190 * If we are using the APIC, the contents of the intline
191 * register will probably be wrong (since they are set up for
192 * use with the PIC. Rather than rewrite these registers
193 * (maybe that would be smarter) we trap attempts to read them
194 * and translate to our private vector numbers.
195 */
196 if ((reg == PCIR_INTLINE) && (bytes == 1)) {
197
198 pin = pcireg_cfgread(bus, slot, func, PCIR_INTPIN, 1);
199 line = pcireg_cfgread(bus, slot, func, PCIR_INTLINE, 1);
200
201 if (pin != 0) {
202 int airq;
203
204 airq = pci_apic_irq(bus, slot, pin);
205 if (airq >= 0) {
206 /* PCI specific entry found in MP table */
207 if (airq != line)
208 undirect_pci_irq(line);
209 return(airq);
210 } else {
211 /*
212 * PCI interrupts might be redirected
213 * to the ISA bus according to some MP
214 * tables. Use the same methods as
215 * used by the ISA devices devices to
216 * find the proper IOAPIC int pin.
217 */
218 airq = isa_apic_irq(line);
219 if ((airq >= 0) && (airq != line)) {
220 /* XXX: undirect_pci_irq() ? */
221 undirect_isa_irq(line);
222 return(airq);
223 }
224 }
225 }
226 return(line);
227 }
228 #else
229 /*
230 * Some BIOS writers seem to want to ignore the spec and put
231 * 0 in the intline rather than 255 to indicate none. The rest of
232 * the code uses 255 as an invalid IRQ.
233 */
234 if (reg == PCIR_INTLINE && bytes == 1) {
235 line = pcireg_cfgread(bus, slot, func, PCIR_INTLINE, 1);
236 return pci_i386_map_intline(line);
237 }
238 #endif /* APIC_IO */
239 return(pcireg_cfgread(bus, slot, func, reg, bytes));
240 }
241
242 /*
243 * Write configuration space register
244 */
245 void
246 pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes)
247 {
248
249 pcireg_cfgwrite(bus, slot, func, reg, data, bytes);
250 }
251
252 /*
253 * Route a PCI interrupt
254 */
255 int
256 pci_cfgintr(int bus, int device, int pin, int oldirq)
257 {
258 struct PIR_entry *pe;
259 int i, irq;
260 struct bios_regs args;
261 u_int16_t v;
262 int already = 0;
263 int errok = 0;
264
265 v = pcibios_get_version();
266 if (v < 0x0210) {
267 PRVERB((
268 "pci_cfgintr: BIOS %x.%02x doesn't support interrupt routing\n",
269 (v & 0xff00) >> 8, v & 0xff));
270 return (PCI_INVALID_IRQ);
271 }
272 if ((bus < 0) || (bus > 255) || (device < 0) || (device > 255) ||
273 (pin < 1) || (pin > 4))
274 return(PCI_INVALID_IRQ);
275
276 /*
277 * Scan the entry table for a contender
278 */
279 for (i = 0, pe = &pci_route_table->pt_entry[0]; i < pci_route_count;
280 i++, pe++) {
281 if ((bus != pe->pe_bus) || (device != pe->pe_device))
282 continue;
283 /*
284 * A link of 0 means that this intpin is not connected to
285 * any other device's interrupt pins and is not connected to
286 * any of the Interrupt Router's interrupt pins, so we can't
287 * route it.
288 */
289 if (pe->pe_intpin[pin - 1].link == 0)
290 continue;
291
292 if (pci_cfgintr_valid(pe, pin, oldirq)) {
293 printf("pci_cfgintr: %d:%d INT%c BIOS irq %d\n", bus,
294 device, 'A' + pin - 1, oldirq);
295 return (oldirq);
296 }
297
298 /*
299 * We try to find a linked interrupt, then we look to see
300 * if the interrupt is uniquely routed, then we look for
301 * a virgin interrupt. The virgin interrupt should return
302 * an interrupt we can route, but if that fails, maybe we
303 * should try harder to route a different interrupt.
304 * However, experience has shown that that's rarely the
305 * failure mode we see.
306 */
307 irq = pci_cfgintr_linked(pe, pin);
308 if (irq != PCI_INVALID_IRQ)
309 already = 1;
310 if (irq == PCI_INVALID_IRQ) {
311 irq = pci_cfgintr_unique(pe, pin);
312 if (irq != PCI_INVALID_IRQ)
313 errok = 1;
314 }
315 if (irq == PCI_INVALID_IRQ)
316 irq = pci_cfgintr_virgin(pe, pin);
317 if (irq == PCI_INVALID_IRQ)
318 break;
319
320 /*
321 * Ask the BIOS to route the interrupt. If we picked an
322 * interrupt that failed, we should really try other
323 * choices that the BIOS offers us.
324 *
325 * For uniquely routed interrupts, we need to try
326 * to route them on some machines. Yet other machines
327 * fail to route, so we have to pretend that in that
328 * case it worked. Isn't pc hardware fun?
329 *
330 * NOTE: if we want to whack hardware to do this, then
331 * I think the right way to do that would be to have
332 * bridge drivers that do this. I'm not sure that the
333 * $PIR table would be valid for those interrupt
334 * routers.
335 */
336 args.eax = PCIBIOS_ROUTE_INTERRUPT;
337 args.ebx = (bus << 8) | (device << 3);
338 /* pin value is 0xa - 0xd */
339 args.ecx = (irq << 8) | (0xa + pin - 1);
340 if (!already &&
341 bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL)) &&
342 !errok) {
343 PRVERB(("pci_cfgintr: ROUTE_INTERRUPT failed.\n"));
344 return(PCI_INVALID_IRQ);
345 }
346 printf("pci_cfgintr: %d:%d INT%c routed to irq %d\n", bus,
347 device, 'A' + pin - 1, irq);
348 return(irq);
349 }
350
351 PRVERB(("pci_cfgintr: can't route an interrupt to %d:%d INT%c\n", bus,
352 device, 'A' + pin - 1));
353 return(PCI_INVALID_IRQ);
354 }
355
356 /*
357 * Check to see if an existing IRQ setting is valid.
358 */
359 static int
360 pci_cfgintr_valid(struct PIR_entry *pe, int pin, int irq)
361 {
362 uint32_t irqmask;
363
364 if (!PCI_INTERRUPT_VALID(irq))
365 return (0);
366 irqmask = pe->pe_intpin[pin - 1].irqs;
367 if (irqmask & (1 << irq)) {
368 PRVERB(("pci_cfgintr_valid: BIOS irq %d is valid\n", irq));
369 return (1);
370 }
371 return (0);
372 }
373
374 /*
375 * Look to see if the routing table claims this pin is uniquely routed.
376 */
377 static int
378 pci_cfgintr_unique(struct PIR_entry *pe, int pin)
379 {
380 int irq;
381 uint32_t irqmask;
382
383 irqmask = pe->pe_intpin[pin - 1].irqs;
384 if (irqmask != 0 && powerof2(irqmask)) {
385 irq = ffs(irqmask) - 1;
386 PRVERB(("pci_cfgintr_unique: hard-routed to irq %d\n", irq));
387 return(irq);
388 }
389 return(PCI_INVALID_IRQ);
390 }
391
392 /*
393 * Look for another device which shares the same link byte and
394 * already has a unique IRQ, or which has had one routed already.
395 */
396 static int
397 pci_cfgintr_linked(struct PIR_entry *pe, int pin)
398 {
399 struct PIR_entry *oe;
400 struct PIR_intpin *pi;
401 int i, j, irq;
402
403 /*
404 * Scan table slots.
405 */
406 for (i = 0, oe = &pci_route_table->pt_entry[0]; i < pci_route_count;
407 i++, oe++) {
408 /* scan interrupt pins */
409 for (j = 0, pi = &oe->pe_intpin[0]; j < 4; j++, pi++) {
410
411 /* don't look at the entry we're trying to match */
412 if ((pe == oe) && (i == (pin - 1)))
413 continue;
414 /* compare link bytes */
415 if (pi->link != pe->pe_intpin[pin - 1].link)
416 continue;
417 /* link destination mapped to a unique interrupt? */
418 if (pi->irqs != 0 && powerof2(pi->irqs)) {
419 irq = ffs(pi->irqs) - 1;
420 PRVERB(("pci_cfgintr_linked: linked (%x) to hard-routed irq %d\n",
421 pi->link, irq));
422 return(irq);
423 }
424
425 /*
426 * look for the real PCI device that matches this
427 * table entry
428 */
429 irq = pci_cfgintr_search(pe, oe->pe_bus, oe->pe_device,
430 j, pin);
431 if (irq != PCI_INVALID_IRQ)
432 return(irq);
433 }
434 }
435 return(PCI_INVALID_IRQ);
436 }
437
438 /*
439 * Scan for the real PCI device at (bus)/(device) using intpin (matchpin) and
440 * see if it has already been assigned an interrupt.
441 */
442 static int
443 pci_cfgintr_search(struct PIR_entry *pe, int bus, int device, int matchpin, int pin)
444 {
445 devclass_t pci_devclass;
446 device_t *pci_devices;
447 int pci_count;
448 device_t *pci_children;
449 int pci_childcount;
450 device_t *busp, *childp;
451 int i, j, irq;
452
453 /*
454 * Find all the PCI busses.
455 */
456 pci_count = 0;
457 if ((pci_devclass = devclass_find("pci")) != NULL)
458 devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
459
460 /*
461 * Scan all the PCI busses/devices looking for this one.
462 */
463 irq = PCI_INVALID_IRQ;
464 for (i = 0, busp = pci_devices; (i < pci_count) && (irq == PCI_INVALID_IRQ);
465 i++, busp++) {
466 pci_childcount = 0;
467 device_get_children(*busp, &pci_children, &pci_childcount);
468
469 for (j = 0, childp = pci_children; j < pci_childcount; j++,
470 childp++) {
471 if ((pci_get_bus(*childp) == bus) &&
472 (pci_get_slot(*childp) == device) &&
473 (pci_get_intpin(*childp) == matchpin)) {
474 irq = pci_i386_map_intline(pci_get_irq(*childp));
475 if (irq != PCI_INVALID_IRQ)
476 PRVERB(("pci_cfgintr_search: linked (%x) to configured irq %d at %d:%d:%d\n",
477 pe->pe_intpin[pin - 1].link, irq,
478 pci_get_bus(*childp),
479 pci_get_slot(*childp),
480 pci_get_function(*childp)));
481 break;
482 }
483 }
484 if (pci_children != NULL)
485 free(pci_children, M_TEMP);
486 }
487 if (pci_devices != NULL)
488 free(pci_devices, M_TEMP);
489 return(irq);
490 }
491
492 /*
493 * Pick a suitable IRQ from those listed as routable to this device.
494 */
495 static int
496 pci_cfgintr_virgin(struct PIR_entry *pe, int pin)
497 {
498 int irq, ibit;
499
500 /*
501 * first scan the set of PCI-only interrupts and see if any of these
502 * are routable
503 */
504 for (irq = 0; irq < 16; irq++) {
505 ibit = (1 << irq);
506
507 /* can we use this interrupt? */
508 if ((pci_route_table->pt_header.ph_pci_irqs & ibit) &&
509 (pe->pe_intpin[pin - 1].irqs & ibit)) {
510 PRVERB(("pci_cfgintr_virgin: using routable PCI-only interrupt %d\n", irq));
511 return(irq);
512 }
513 }
514
515 /* life is tough, so just pick an interrupt */
516 for (irq = 0; irq < 16; irq++) {
517 ibit = (1 << irq);
518 if (pe->pe_intpin[pin - 1].irqs & ibit) {
519 PRVERB(("pci_cfgintr_virgin: using routable interrupt %d\n", irq));
520 return(irq);
521 }
522 }
523 return(PCI_INVALID_IRQ);
524 }
525
526 static void
527 pci_print_irqmask(u_int16_t irqs)
528 {
529 int i, first;
530
531 if (irqs == 0) {
532 printf("none");
533 return;
534 }
535 first = 1;
536 for (i = 0; i < 16; i++, irqs >>= 1)
537 if (irqs & 1) {
538 if (!first)
539 printf(" ");
540 else
541 first = 0;
542 printf("%d", i);
543 }
544 }
545
546 /*
547 * Dump the contents of a PCI BIOS Interrupt Routing Table to the console.
548 */
549 static void
550 pci_print_route_table(struct PIR_table *prt, int size)
551 {
552 struct PIR_entry *entry;
553 struct PIR_intpin *intpin;
554 int i, pin;
555
556 printf("PCI-Only Interrupts: ");
557 pci_print_irqmask(prt->pt_header.ph_pci_irqs);
558 printf("\nLocation Bus Device Pin Link IRQs\n");
559 entry = &prt->pt_entry[0];
560 for (i = 0; i < size; i++, entry++) {
561 intpin = &entry->pe_intpin[0];
562 for (pin = 0; pin < 4; pin++, intpin++)
563 if (intpin->link != 0) {
564 if (entry->pe_slot == 0)
565 printf("embedded ");
566 else
567 printf("slot %-3d ", entry->pe_slot);
568 printf(" %3d %3d %c 0x%02x ",
569 entry->pe_bus, entry->pe_device,
570 'A' + pin, intpin->link);
571 pci_print_irqmask(intpin->irqs);
572 printf("\n");
573 }
574 }
575 }
576
577 /*
578 * See if any interrupts for a given PCI bus are routed in the PIR. Don't
579 * even bother looking if the BIOS doesn't support routing anyways.
580 */
581 int
582 pci_probe_route_table(int bus)
583 {
584 int i;
585 u_int16_t v;
586
587 v = pcibios_get_version();
588 if (v < 0x0210)
589 return (0);
590 for (i = 0; i < pci_route_count; i++)
591 if (pci_route_table->pt_entry[i].pe_bus == bus)
592 return (1);
593 return (0);
594 }
595
596 /*
597 * Configuration space access using direct register operations
598 */
599
600 /* enable configuration space accesses and return data port address */
601 static int
602 pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
603 {
604 int dataport = 0;
605
606 if (bus <= PCI_BUSMAX
607 && slot < devmax
608 && func <= PCI_FUNCMAX
609 && reg <= PCI_REGMAX
610 && bytes != 3
611 && (unsigned) bytes <= 4
612 && (reg & (bytes - 1)) == 0) {
613 switch (cfgmech) {
614 case 1:
615 outl(CONF1_ADDR_PORT, (1 << 31)
616 | (bus << 16) | (slot << 11)
617 | (func << 8) | (reg & ~0x03));
618 dataport = CONF1_DATA_PORT + (reg & 0x03);
619 break;
620 case 2:
621 outb(CONF2_ENABLE_PORT, 0xf0 | (func << 1));
622 outb(CONF2_FORWARD_PORT, bus);
623 dataport = 0xc000 | (slot << 8) | reg;
624 break;
625 }
626 }
627 return (dataport);
628 }
629
630 /* disable configuration space accesses */
631 static void
632 pci_cfgdisable(void)
633 {
634 switch (cfgmech) {
635 case 1:
636 outl(CONF1_ADDR_PORT, 0);
637 break;
638 case 2:
639 outb(CONF2_ENABLE_PORT, 0);
640 outb(CONF2_FORWARD_PORT, 0);
641 break;
642 }
643 }
644
645 static int
646 pcireg_cfgread(int bus, int slot, int func, int reg, int bytes)
647 {
648 int data = -1;
649 int port;
650
651 mtx_lock_spin(&pcicfg_mtx);
652 port = pci_cfgenable(bus, slot, func, reg, bytes);
653 if (port != 0) {
654 switch (bytes) {
655 case 1:
656 data = inb(port);
657 break;
658 case 2:
659 data = inw(port);
660 break;
661 case 4:
662 data = inl(port);
663 break;
664 }
665 pci_cfgdisable();
666 }
667 mtx_unlock_spin(&pcicfg_mtx);
668 return (data);
669 }
670
671 static void
672 pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
673 {
674 int port;
675
676 mtx_lock_spin(&pcicfg_mtx);
677 port = pci_cfgenable(bus, slot, func, reg, bytes);
678 if (port != 0) {
679 switch (bytes) {
680 case 1:
681 outb(port, data);
682 break;
683 case 2:
684 outw(port, data);
685 break;
686 case 4:
687 outl(port, data);
688 break;
689 }
690 pci_cfgdisable();
691 }
692 mtx_unlock_spin(&pcicfg_mtx);
693 }
694
695 /* check whether the configuration mechanism has been correctly identified */
696 static int
697 pci_cfgcheck(int maxdev)
698 {
699 uint32_t id, class;
700 uint8_t header;
701 uint8_t device;
702 int port;
703
704 if (bootverbose)
705 printf("pci_cfgcheck:\tdevice ");
706
707 for (device = 0; device < maxdev; device++) {
708 if (bootverbose)
709 printf("%d ", device);
710
711 port = pci_cfgenable(0, device, 0, 0, 4);
712 id = inl(port);
713 if (id == 0 || id == 0xffffffff)
714 continue;
715
716 port = pci_cfgenable(0, device, 0, 8, 4);
717 class = inl(port) >> 8;
718 if (bootverbose)
719 printf("[class=%06x] ", class);
720 if (class == 0 || (class & 0xf870ff) != 0)
721 continue;
722
723 port = pci_cfgenable(0, device, 0, 14, 1);
724 header = inb(port);
725 if (bootverbose)
726 printf("[hdr=%02x] ", header);
727 if ((header & 0x7e) != 0)
728 continue;
729
730 if (bootverbose)
731 printf("is there (id=%08x)\n", id);
732
733 pci_cfgdisable();
734 return (1);
735 }
736 if (bootverbose)
737 printf("-- nothing found\n");
738
739 pci_cfgdisable();
740 return (0);
741 }
742
743 static int
744 pcireg_cfgopen(void)
745 {
746 uint32_t mode1res, oldval1;
747 uint8_t mode2res, oldval2;
748
749 oldval1 = inl(CONF1_ADDR_PORT);
750
751 if (bootverbose) {
752 printf("pci_open(1):\tmode 1 addr port (0x0cf8) is 0x%08x\n",
753 oldval1);
754 }
755
756 if ((oldval1 & CONF1_ENABLE_MSK) == 0) {
757
758 cfgmech = 1;
759 devmax = 32;
760
761 outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK);
762 outb(CONF1_ADDR_PORT + 3, 0);
763 mode1res = inl(CONF1_ADDR_PORT);
764 outl(CONF1_ADDR_PORT, oldval1);
765
766 if (bootverbose)
767 printf("pci_open(1a):\tmode1res=0x%08x (0x%08lx)\n",
768 mode1res, CONF1_ENABLE_CHK);
769
770 if (mode1res) {
771 if (pci_cfgcheck(32))
772 return (cfgmech);
773 }
774
775 outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK1);
776 mode1res = inl(CONF1_ADDR_PORT);
777 outl(CONF1_ADDR_PORT, oldval1);
778
779 if (bootverbose)
780 printf("pci_open(1b):\tmode1res=0x%08x (0x%08lx)\n",
781 mode1res, CONF1_ENABLE_CHK1);
782
783 if ((mode1res & CONF1_ENABLE_MSK1) == CONF1_ENABLE_RES1) {
784 if (pci_cfgcheck(32))
785 return (cfgmech);
786 }
787 }
788
789 oldval2 = inb(CONF2_ENABLE_PORT);
790
791 if (bootverbose) {
792 printf("pci_open(2):\tmode 2 enable port (0x0cf8) is 0x%02x\n",
793 oldval2);
794 }
795
796 if ((oldval2 & 0xf0) == 0) {
797
798 cfgmech = 2;
799 devmax = 16;
800
801 outb(CONF2_ENABLE_PORT, CONF2_ENABLE_CHK);
802 mode2res = inb(CONF2_ENABLE_PORT);
803 outb(CONF2_ENABLE_PORT, oldval2);
804
805 if (bootverbose)
806 printf("pci_open(2a):\tmode2res=0x%02x (0x%02x)\n",
807 mode2res, CONF2_ENABLE_CHK);
808
809 if (mode2res == CONF2_ENABLE_RES) {
810 if (bootverbose)
811 printf("pci_open(2a):\tnow trying mechanism 2\n");
812
813 if (pci_cfgcheck(16))
814 return (cfgmech);
815 }
816 }
817
818 cfgmech = 0;
819 devmax = 0;
820 return (cfgmech);
821 }
822
Cache object: a7be4858d6e766b28bef9b995b886640
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