FreeBSD/Linux Kernel Cross Reference
sys/i386/xen/pmap.c
1 /*-
2 * Copyright (c) 1991 Regents of the University of California.
3 * All rights reserved.
4 * Copyright (c) 1994 John S. Dyson
5 * All rights reserved.
6 * Copyright (c) 1994 David Greenman
7 * All rights reserved.
8 * Copyright (c) 2005 Alan L. Cox <alc@cs.rice.edu>
9 * All rights reserved.
10 *
11 * This code is derived from software contributed to Berkeley by
12 * the Systems Programming Group of the University of Utah Computer
13 * Science Department and William Jolitz of UUNET Technologies Inc.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 * 3. All advertising materials mentioning features or use of this software
24 * must display the following acknowledgement:
25 * This product includes software developed by the University of
26 * California, Berkeley and its contributors.
27 * 4. Neither the name of the University nor the names of its contributors
28 * may be used to endorse or promote products derived from this software
29 * without specific prior written permission.
30 *
31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
41 * SUCH DAMAGE.
42 *
43 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
44 */
45 /*-
46 * Copyright (c) 2003 Networks Associates Technology, Inc.
47 * All rights reserved.
48 *
49 * This software was developed for the FreeBSD Project by Jake Burkholder,
50 * Safeport Network Services, and Network Associates Laboratories, the
51 * Security Research Division of Network Associates, Inc. under
52 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
53 * CHATS research program.
54 *
55 * Redistribution and use in source and binary forms, with or without
56 * modification, are permitted provided that the following conditions
57 * are met:
58 * 1. Redistributions of source code must retain the above copyright
59 * notice, this list of conditions and the following disclaimer.
60 * 2. Redistributions in binary form must reproduce the above copyright
61 * notice, this list of conditions and the following disclaimer in the
62 * documentation and/or other materials provided with the distribution.
63 *
64 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
67 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
74 * SUCH DAMAGE.
75 */
76
77 #include <sys/cdefs.h>
78 __FBSDID("$FreeBSD: releng/9.0/sys/i386/xen/pmap.c 225418 2011-09-06 10:30:11Z kib $");
79
80 /*
81 * Manages physical address maps.
82 *
83 * In addition to hardware address maps, this
84 * module is called upon to provide software-use-only
85 * maps which may or may not be stored in the same
86 * form as hardware maps. These pseudo-maps are
87 * used to store intermediate results from copy
88 * operations to and from address spaces.
89 *
90 * Since the information managed by this module is
91 * also stored by the logical address mapping module,
92 * this module may throw away valid virtual-to-physical
93 * mappings at almost any time. However, invalidations
94 * of virtual-to-physical mappings must be done as
95 * requested.
96 *
97 * In order to cope with hardware architectures which
98 * make virtual-to-physical map invalidates expensive,
99 * this module may delay invalidate or reduced protection
100 * operations until such time as they are actually
101 * necessary. This module is given full information as
102 * to which processors are currently using which maps,
103 * and to when physical maps must be made correct.
104 */
105
106 #include "opt_cpu.h"
107 #include "opt_pmap.h"
108 #include "opt_smp.h"
109 #include "opt_xbox.h"
110
111 #include <sys/param.h>
112 #include <sys/systm.h>
113 #include <sys/kernel.h>
114 #include <sys/ktr.h>
115 #include <sys/lock.h>
116 #include <sys/malloc.h>
117 #include <sys/mman.h>
118 #include <sys/msgbuf.h>
119 #include <sys/mutex.h>
120 #include <sys/proc.h>
121 #include <sys/sf_buf.h>
122 #include <sys/sx.h>
123 #include <sys/vmmeter.h>
124 #include <sys/sched.h>
125 #include <sys/sysctl.h>
126 #ifdef SMP
127 #include <sys/smp.h>
128 #endif
129
130 #include <vm/vm.h>
131 #include <vm/vm_param.h>
132 #include <vm/vm_kern.h>
133 #include <vm/vm_page.h>
134 #include <vm/vm_map.h>
135 #include <vm/vm_object.h>
136 #include <vm/vm_extern.h>
137 #include <vm/vm_pageout.h>
138 #include <vm/vm_pager.h>
139 #include <vm/uma.h>
140
141 #include <machine/cpu.h>
142 #include <machine/cputypes.h>
143 #include <machine/md_var.h>
144 #include <machine/pcb.h>
145 #include <machine/specialreg.h>
146 #ifdef SMP
147 #include <machine/smp.h>
148 #endif
149
150 #ifdef XBOX
151 #include <machine/xbox.h>
152 #endif
153
154 #include <xen/interface/xen.h>
155 #include <xen/hypervisor.h>
156 #include <machine/xen/hypercall.h>
157 #include <machine/xen/xenvar.h>
158 #include <machine/xen/xenfunc.h>
159
160 #if !defined(CPU_DISABLE_SSE) && defined(I686_CPU)
161 #define CPU_ENABLE_SSE
162 #endif
163
164 #ifndef PMAP_SHPGPERPROC
165 #define PMAP_SHPGPERPROC 200
166 #endif
167
168 #define DIAGNOSTIC
169
170 #if !defined(DIAGNOSTIC)
171 #ifdef __GNUC_GNU_INLINE__
172 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
173 #else
174 #define PMAP_INLINE extern inline
175 #endif
176 #else
177 #define PMAP_INLINE
178 #endif
179
180 #define PV_STATS
181 #ifdef PV_STATS
182 #define PV_STAT(x) do { x ; } while (0)
183 #else
184 #define PV_STAT(x) do { } while (0)
185 #endif
186
187 #define pa_index(pa) ((pa) >> PDRSHIFT)
188 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
189
190 /*
191 * Get PDEs and PTEs for user/kernel address space
192 */
193 #define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT]))
194 #define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT])
195
196 #define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0)
197 #define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0)
198 #define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0)
199 #define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0)
200 #define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0)
201
202 #define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v)))
203
204 #define HAMFISTED_LOCKING
205 #ifdef HAMFISTED_LOCKING
206 static struct mtx createdelete_lock;
207 #endif
208
209 struct pmap kernel_pmap_store;
210 LIST_HEAD(pmaplist, pmap);
211 static struct pmaplist allpmaps;
212 static struct mtx allpmaps_lock;
213
214 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
215 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
216 int pgeflag = 0; /* PG_G or-in */
217 int pseflag = 0; /* PG_PS or-in */
218
219 int nkpt;
220 vm_offset_t kernel_vm_end;
221 extern u_int32_t KERNend;
222
223 #ifdef PAE
224 pt_entry_t pg_nx;
225 #endif
226
227 static int pat_works; /* Is page attribute table sane? */
228
229 /*
230 * Data for the pv entry allocation mechanism
231 */
232 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
233 static struct md_page *pv_table;
234 static int shpgperproc = PMAP_SHPGPERPROC;
235
236 struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
237 int pv_maxchunks; /* How many chunks we have KVA for */
238 vm_offset_t pv_vafree; /* freelist stored in the PTE */
239
240 /*
241 * All those kernel PT submaps that BSD is so fond of
242 */
243 struct sysmaps {
244 struct mtx lock;
245 pt_entry_t *CMAP1;
246 pt_entry_t *CMAP2;
247 caddr_t CADDR1;
248 caddr_t CADDR2;
249 };
250 static struct sysmaps sysmaps_pcpu[MAXCPU];
251 static pt_entry_t *CMAP3;
252 caddr_t ptvmmap = 0;
253 static caddr_t CADDR3;
254 struct msgbuf *msgbufp = 0;
255
256 /*
257 * Crashdump maps.
258 */
259 static caddr_t crashdumpmap;
260
261 static pt_entry_t *PMAP1 = 0, *PMAP2;
262 static pt_entry_t *PADDR1 = 0, *PADDR2;
263 #ifdef SMP
264 static int PMAP1cpu;
265 static int PMAP1changedcpu;
266 SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD,
267 &PMAP1changedcpu, 0,
268 "Number of times pmap_pte_quick changed CPU with same PMAP1");
269 #endif
270 static int PMAP1changed;
271 SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD,
272 &PMAP1changed, 0,
273 "Number of times pmap_pte_quick changed PMAP1");
274 static int PMAP1unchanged;
275 SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD,
276 &PMAP1unchanged, 0,
277 "Number of times pmap_pte_quick didn't change PMAP1");
278 static struct mtx PMAP2mutex;
279
280 SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
281 static int pg_ps_enabled;
282 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN, &pg_ps_enabled, 0,
283 "Are large page mappings enabled?");
284
285 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0,
286 "Max number of PV entries");
287 SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0,
288 "Page share factor per proc");
289 SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
290 "2/4MB page mapping counters");
291
292 static u_long pmap_pde_mappings;
293 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
294 &pmap_pde_mappings, 0, "2/4MB page mappings");
295
296 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
297 static pv_entry_t get_pv_entry(pmap_t locked_pmap, int try);
298 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
299 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
300 vm_offset_t va);
301
302 static vm_page_t pmap_enter_quick_locked(multicall_entry_t **mcl, int *count, pmap_t pmap, vm_offset_t va,
303 vm_page_t m, vm_prot_t prot, vm_page_t mpte);
304 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
305 vm_page_t *free);
306 static void pmap_remove_page(struct pmap *pmap, vm_offset_t va,
307 vm_page_t *free);
308 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m,
309 vm_offset_t va);
310 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
311 vm_page_t m);
312
313 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags);
314
315 static vm_page_t _pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags);
316 static int _pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free);
317 static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va);
318 static void pmap_pte_release(pt_entry_t *pte);
319 static int pmap_unuse_pt(pmap_t, vm_offset_t, vm_page_t *);
320 static vm_offset_t pmap_kmem_choose(vm_offset_t addr);
321 static boolean_t pmap_is_prefaultable_locked(pmap_t pmap, vm_offset_t addr);
322 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
323
324 static __inline void pagezero(void *page);
325
326 CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t));
327 CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t));
328
329 /*
330 * If you get an error here, then you set KVA_PAGES wrong! See the
331 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be
332 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE.
333 */
334 CTASSERT(KERNBASE % (1 << 24) == 0);
335
336
337
338 void
339 pd_set(struct pmap *pmap, int ptepindex, vm_paddr_t val, int type)
340 {
341 vm_paddr_t pdir_ma = vtomach(&pmap->pm_pdir[ptepindex]);
342
343 switch (type) {
344 case SH_PD_SET_VA:
345 #if 0
346 xen_queue_pt_update(shadow_pdir_ma,
347 xpmap_ptom(val & ~(PG_RW)));
348 #endif
349 xen_queue_pt_update(pdir_ma,
350 xpmap_ptom(val));
351 break;
352 case SH_PD_SET_VA_MA:
353 #if 0
354 xen_queue_pt_update(shadow_pdir_ma,
355 val & ~(PG_RW));
356 #endif
357 xen_queue_pt_update(pdir_ma, val);
358 break;
359 case SH_PD_SET_VA_CLEAR:
360 #if 0
361 xen_queue_pt_update(shadow_pdir_ma, 0);
362 #endif
363 xen_queue_pt_update(pdir_ma, 0);
364 break;
365 }
366 }
367
368 /*
369 * Move the kernel virtual free pointer to the next
370 * 4MB. This is used to help improve performance
371 * by using a large (4MB) page for much of the kernel
372 * (.text, .data, .bss)
373 */
374 static vm_offset_t
375 pmap_kmem_choose(vm_offset_t addr)
376 {
377 vm_offset_t newaddr = addr;
378
379 #ifndef DISABLE_PSE
380 if (cpu_feature & CPUID_PSE)
381 newaddr = (addr + PDRMASK) & ~PDRMASK;
382 #endif
383 return newaddr;
384 }
385
386 /*
387 * Bootstrap the system enough to run with virtual memory.
388 *
389 * On the i386 this is called after mapping has already been enabled
390 * and just syncs the pmap module with what has already been done.
391 * [We can't call it easily with mapping off since the kernel is not
392 * mapped with PA == VA, hence we would have to relocate every address
393 * from the linked base (virtual) address "KERNBASE" to the actual
394 * (physical) address starting relative to 0]
395 */
396 void
397 pmap_bootstrap(vm_paddr_t firstaddr)
398 {
399 vm_offset_t va;
400 pt_entry_t *pte, *unused;
401 struct sysmaps *sysmaps;
402 int i;
403
404 /*
405 * XXX The calculation of virtual_avail is wrong. It's NKPT*PAGE_SIZE too
406 * large. It should instead be correctly calculated in locore.s and
407 * not based on 'first' (which is a physical address, not a virtual
408 * address, for the start of unused physical memory). The kernel
409 * page tables are NOT double mapped and thus should not be included
410 * in this calculation.
411 */
412 virtual_avail = (vm_offset_t) KERNBASE + firstaddr;
413 virtual_avail = pmap_kmem_choose(virtual_avail);
414
415 virtual_end = VM_MAX_KERNEL_ADDRESS;
416
417 /*
418 * Initialize the kernel pmap (which is statically allocated).
419 */
420 PMAP_LOCK_INIT(kernel_pmap);
421 kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD);
422 #ifdef PAE
423 kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT);
424 #endif
425 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
426 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
427 LIST_INIT(&allpmaps);
428 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN);
429 mtx_lock_spin(&allpmaps_lock);
430 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list);
431 mtx_unlock_spin(&allpmaps_lock);
432 if (nkpt == 0)
433 nkpt = NKPT;
434
435 /*
436 * Reserve some special page table entries/VA space for temporary
437 * mapping of pages.
438 */
439 #define SYSMAP(c, p, v, n) \
440 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
441
442 va = virtual_avail;
443 pte = vtopte(va);
444
445 /*
446 * CMAP1/CMAP2 are used for zeroing and copying pages.
447 * CMAP3 is used for the idle process page zeroing.
448 */
449 for (i = 0; i < MAXCPU; i++) {
450 sysmaps = &sysmaps_pcpu[i];
451 mtx_init(&sysmaps->lock, "SYSMAPS", NULL, MTX_DEF);
452 SYSMAP(caddr_t, sysmaps->CMAP1, sysmaps->CADDR1, 1)
453 SYSMAP(caddr_t, sysmaps->CMAP2, sysmaps->CADDR2, 1)
454 PT_SET_MA(sysmaps->CADDR1, 0);
455 PT_SET_MA(sysmaps->CADDR2, 0);
456 }
457 SYSMAP(caddr_t, CMAP3, CADDR3, 1)
458 PT_SET_MA(CADDR3, 0);
459
460 /*
461 * Crashdump maps.
462 */
463 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS)
464
465 /*
466 * ptvmmap is used for reading arbitrary physical pages via /dev/mem.
467 */
468 SYSMAP(caddr_t, unused, ptvmmap, 1)
469
470 /*
471 * msgbufp is used to map the system message buffer.
472 */
473 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize)))
474
475 /*
476 * ptemap is used for pmap_pte_quick
477 */
478 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1);
479 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1);
480
481 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
482
483 virtual_avail = va;
484
485 /*
486 * Leave in place an identity mapping (virt == phys) for the low 1 MB
487 * physical memory region that is used by the ACPI wakeup code. This
488 * mapping must not have PG_G set.
489 */
490 #ifndef XEN
491 /*
492 * leave here deliberately to show that this is not supported
493 */
494 #ifdef XBOX
495 /* FIXME: This is gross, but needed for the XBOX. Since we are in such
496 * an early stadium, we cannot yet neatly map video memory ... :-(
497 * Better fixes are very welcome! */
498 if (!arch_i386_is_xbox)
499 #endif
500 for (i = 1; i < NKPT; i++)
501 PTD[i] = 0;
502
503 /* Initialize the PAT MSR if present. */
504 pmap_init_pat();
505
506 /* Turn on PG_G on kernel page(s) */
507 pmap_set_pg();
508 #endif
509
510 #ifdef HAMFISTED_LOCKING
511 mtx_init(&createdelete_lock, "pmap create/delete", NULL, MTX_DEF);
512 #endif
513 }
514
515 /*
516 * Setup the PAT MSR.
517 */
518 void
519 pmap_init_pat(void)
520 {
521 uint64_t pat_msr;
522
523 /* Bail if this CPU doesn't implement PAT. */
524 if (!(cpu_feature & CPUID_PAT))
525 return;
526
527 if (cpu_vendor_id != CPU_VENDOR_INTEL ||
528 (CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe)) {
529 /*
530 * Leave the indices 0-3 at the default of WB, WT, UC, and UC-.
531 * Program 4 and 5 as WP and WC.
532 * Leave 6 and 7 as UC and UC-.
533 */
534 pat_msr = rdmsr(MSR_PAT);
535 pat_msr &= ~(PAT_MASK(4) | PAT_MASK(5));
536 pat_msr |= PAT_VALUE(4, PAT_WRITE_PROTECTED) |
537 PAT_VALUE(5, PAT_WRITE_COMBINING);
538 pat_works = 1;
539 } else {
540 /*
541 * Due to some Intel errata, we can only safely use the lower 4
542 * PAT entries. Thus, just replace PAT Index 2 with WC instead
543 * of UC-.
544 *
545 * Intel Pentium III Processor Specification Update
546 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B
547 * or Mode C Paging)
548 *
549 * Intel Pentium IV Processor Specification Update
550 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly)
551 */
552 pat_msr = rdmsr(MSR_PAT);
553 pat_msr &= ~PAT_MASK(2);
554 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
555 pat_works = 0;
556 }
557 wrmsr(MSR_PAT, pat_msr);
558 }
559
560 /*
561 * Initialize a vm_page's machine-dependent fields.
562 */
563 void
564 pmap_page_init(vm_page_t m)
565 {
566
567 TAILQ_INIT(&m->md.pv_list);
568 m->md.pat_mode = PAT_WRITE_BACK;
569 }
570
571 /*
572 * ABuse the pte nodes for unmapped kva to thread a kva freelist through.
573 * Requirements:
574 * - Must deal with pages in order to ensure that none of the PG_* bits
575 * are ever set, PG_V in particular.
576 * - Assumes we can write to ptes without pte_store() atomic ops, even
577 * on PAE systems. This should be ok.
578 * - Assumes nothing will ever test these addresses for 0 to indicate
579 * no mapping instead of correctly checking PG_V.
580 * - Assumes a vm_offset_t will fit in a pte (true for i386).
581 * Because PG_V is never set, there can be no mappings to invalidate.
582 */
583 static int ptelist_count = 0;
584 static vm_offset_t
585 pmap_ptelist_alloc(vm_offset_t *head)
586 {
587 vm_offset_t va;
588 vm_offset_t *phead = (vm_offset_t *)*head;
589
590 if (ptelist_count == 0) {
591 printf("out of memory!!!!!!\n");
592 return (0); /* Out of memory */
593 }
594 ptelist_count--;
595 va = phead[ptelist_count];
596 return (va);
597 }
598
599 static void
600 pmap_ptelist_free(vm_offset_t *head, vm_offset_t va)
601 {
602 vm_offset_t *phead = (vm_offset_t *)*head;
603
604 phead[ptelist_count++] = va;
605 }
606
607 static void
608 pmap_ptelist_init(vm_offset_t *head, void *base, int npages)
609 {
610 int i, nstackpages;
611 vm_offset_t va;
612 vm_page_t m;
613
614 nstackpages = (npages + PAGE_SIZE/sizeof(vm_offset_t) - 1)/ (PAGE_SIZE/sizeof(vm_offset_t));
615 for (i = 0; i < nstackpages; i++) {
616 va = (vm_offset_t)base + i * PAGE_SIZE;
617 m = vm_page_alloc(NULL, i,
618 VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
619 VM_ALLOC_ZERO);
620 pmap_qenter(va, &m, 1);
621 }
622
623 *head = (vm_offset_t)base;
624 for (i = npages - 1; i >= nstackpages; i--) {
625 va = (vm_offset_t)base + i * PAGE_SIZE;
626 pmap_ptelist_free(head, va);
627 }
628 }
629
630
631 /*
632 * Initialize the pmap module.
633 * Called by vm_init, to initialize any structures that the pmap
634 * system needs to map virtual memory.
635 */
636 void
637 pmap_init(void)
638 {
639 vm_page_t mpte;
640 vm_size_t s;
641 int i, pv_npg;
642
643 /*
644 * Initialize the vm page array entries for the kernel pmap's
645 * page table pages.
646 */
647 for (i = 0; i < nkpt; i++) {
648 mpte = PHYS_TO_VM_PAGE(xpmap_mtop(PTD[i + KPTDI] & PG_FRAME));
649 KASSERT(mpte >= vm_page_array &&
650 mpte < &vm_page_array[vm_page_array_size],
651 ("pmap_init: page table page is out of range"));
652 mpte->pindex = i + KPTDI;
653 mpte->phys_addr = xpmap_mtop(PTD[i + KPTDI] & PG_FRAME);
654 }
655
656 /*
657 * Initialize the address space (zone) for the pv entries. Set a
658 * high water mark so that the system can recover from excessive
659 * numbers of pv entries.
660 */
661 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
662 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count;
663 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
664 pv_entry_max = roundup(pv_entry_max, _NPCPV);
665 pv_entry_high_water = 9 * (pv_entry_max / 10);
666
667 /*
668 * Are large page mappings enabled?
669 */
670 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
671
672 /*
673 * Calculate the size of the pv head table for superpages.
674 */
675 for (i = 0; phys_avail[i + 1]; i += 2);
676 pv_npg = round_4mpage(phys_avail[(i - 2) + 1]) / NBPDR;
677
678 /*
679 * Allocate memory for the pv head table for superpages.
680 */
681 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
682 s = round_page(s);
683 pv_table = (struct md_page *)kmem_alloc(kernel_map, s);
684 for (i = 0; i < pv_npg; i++)
685 TAILQ_INIT(&pv_table[i].pv_list);
686
687 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
688 pv_chunkbase = (struct pv_chunk *)kmem_alloc_nofault(kernel_map,
689 PAGE_SIZE * pv_maxchunks);
690 if (pv_chunkbase == NULL)
691 panic("pmap_init: not enough kvm for pv chunks");
692 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
693 }
694
695
696 /***************************************************
697 * Low level helper routines.....
698 ***************************************************/
699
700 /*
701 * Determine the appropriate bits to set in a PTE or PDE for a specified
702 * caching mode.
703 */
704 int
705 pmap_cache_bits(int mode, boolean_t is_pde)
706 {
707 int pat_flag, pat_index, cache_bits;
708
709 /* The PAT bit is different for PTE's and PDE's. */
710 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
711
712 /* If we don't support PAT, map extended modes to older ones. */
713 if (!(cpu_feature & CPUID_PAT)) {
714 switch (mode) {
715 case PAT_UNCACHEABLE:
716 case PAT_WRITE_THROUGH:
717 case PAT_WRITE_BACK:
718 break;
719 case PAT_UNCACHED:
720 case PAT_WRITE_COMBINING:
721 case PAT_WRITE_PROTECTED:
722 mode = PAT_UNCACHEABLE;
723 break;
724 }
725 }
726
727 /* Map the caching mode to a PAT index. */
728 if (pat_works) {
729 switch (mode) {
730 case PAT_UNCACHEABLE:
731 pat_index = 3;
732 break;
733 case PAT_WRITE_THROUGH:
734 pat_index = 1;
735 break;
736 case PAT_WRITE_BACK:
737 pat_index = 0;
738 break;
739 case PAT_UNCACHED:
740 pat_index = 2;
741 break;
742 case PAT_WRITE_COMBINING:
743 pat_index = 5;
744 break;
745 case PAT_WRITE_PROTECTED:
746 pat_index = 4;
747 break;
748 default:
749 panic("Unknown caching mode %d\n", mode);
750 }
751 } else {
752 switch (mode) {
753 case PAT_UNCACHED:
754 case PAT_UNCACHEABLE:
755 case PAT_WRITE_PROTECTED:
756 pat_index = 3;
757 break;
758 case PAT_WRITE_THROUGH:
759 pat_index = 1;
760 break;
761 case PAT_WRITE_BACK:
762 pat_index = 0;
763 break;
764 case PAT_WRITE_COMBINING:
765 pat_index = 2;
766 break;
767 default:
768 panic("Unknown caching mode %d\n", mode);
769 }
770 }
771
772 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
773 cache_bits = 0;
774 if (pat_index & 0x4)
775 cache_bits |= pat_flag;
776 if (pat_index & 0x2)
777 cache_bits |= PG_NC_PCD;
778 if (pat_index & 0x1)
779 cache_bits |= PG_NC_PWT;
780 return (cache_bits);
781 }
782 #ifdef SMP
783 /*
784 * For SMP, these functions have to use the IPI mechanism for coherence.
785 *
786 * N.B.: Before calling any of the following TLB invalidation functions,
787 * the calling processor must ensure that all stores updating a non-
788 * kernel page table are globally performed. Otherwise, another
789 * processor could cache an old, pre-update entry without being
790 * invalidated. This can happen one of two ways: (1) The pmap becomes
791 * active on another processor after its pm_active field is checked by
792 * one of the following functions but before a store updating the page
793 * table is globally performed. (2) The pmap becomes active on another
794 * processor before its pm_active field is checked but due to
795 * speculative loads one of the following functions stills reads the
796 * pmap as inactive on the other processor.
797 *
798 * The kernel page table is exempt because its pm_active field is
799 * immutable. The kernel page table is always active on every
800 * processor.
801 */
802 void
803 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
804 {
805 cpuset_t other_cpus;
806 u_int cpuid;
807
808 CTR2(KTR_PMAP, "pmap_invalidate_page: pmap=%p va=0x%x",
809 pmap, va);
810
811 sched_pin();
812 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
813 invlpg(va);
814 smp_invlpg(va);
815 } else {
816 cpuid = PCPU_GET(cpuid);
817 other_cpus = all_cpus;
818 CPU_CLR(cpuid, &other_cpus);
819 if (CPU_ISSET(cpuid, &pmap->pm_active))
820 invlpg(va);
821 CPU_AND(&other_cpus, &pmap->pm_active);
822 if (!CPU_EMPTY(&other_cpus))
823 smp_masked_invlpg(other_cpus, va);
824 }
825 sched_unpin();
826 PT_UPDATES_FLUSH();
827 }
828
829 void
830 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
831 {
832 cpuset_t other_cpus;
833 vm_offset_t addr;
834 u_int cpuid;
835
836 CTR3(KTR_PMAP, "pmap_invalidate_page: pmap=%p eva=0x%x sva=0x%x",
837 pmap, sva, eva);
838
839 sched_pin();
840 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
841 for (addr = sva; addr < eva; addr += PAGE_SIZE)
842 invlpg(addr);
843 smp_invlpg_range(sva, eva);
844 } else {
845 cpuid = PCPU_GET(cpuid);
846 other_cpus = all_cpus;
847 CPU_CLR(cpuid, &other_cpus);
848 if (CPU_ISSET(cpuid, &pmap->pm_active))
849 for (addr = sva; addr < eva; addr += PAGE_SIZE)
850 invlpg(addr);
851 CPU_AND(&other_cpus, &pmap->pm_active);
852 if (!CPU_EMPTY(&other_cpus))
853 smp_masked_invlpg_range(other_cpus, sva, eva);
854 }
855 sched_unpin();
856 PT_UPDATES_FLUSH();
857 }
858
859 void
860 pmap_invalidate_all(pmap_t pmap)
861 {
862 cpuset_t other_cpus;
863 u_int cpuid;
864
865 CTR1(KTR_PMAP, "pmap_invalidate_page: pmap=%p", pmap);
866
867 sched_pin();
868 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
869 invltlb();
870 smp_invltlb();
871 } else {
872 cpuid = PCPU_GET(cpuid);
873 other_cpus = all_cpus;
874 CPU_CLR(cpuid, &other_cpus);
875 if (CPU_ISSET(cpuid, &pmap->pm_active))
876 invltlb();
877 CPU_AND(&other_cpus, &pmap->pm_active);
878 if (!CPU_EMPTY(&other_cpus))
879 smp_masked_invltlb(other_cpus);
880 }
881 sched_unpin();
882 }
883
884 void
885 pmap_invalidate_cache(void)
886 {
887
888 sched_pin();
889 wbinvd();
890 smp_cache_flush();
891 sched_unpin();
892 }
893 #else /* !SMP */
894 /*
895 * Normal, non-SMP, 486+ invalidation functions.
896 * We inline these within pmap.c for speed.
897 */
898 PMAP_INLINE void
899 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
900 {
901 CTR2(KTR_PMAP, "pmap_invalidate_page: pmap=%p va=0x%x",
902 pmap, va);
903
904 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
905 invlpg(va);
906 PT_UPDATES_FLUSH();
907 }
908
909 PMAP_INLINE void
910 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
911 {
912 vm_offset_t addr;
913
914 if (eva - sva > PAGE_SIZE)
915 CTR3(KTR_PMAP, "pmap_invalidate_range: pmap=%p sva=0x%x eva=0x%x",
916 pmap, sva, eva);
917
918 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
919 for (addr = sva; addr < eva; addr += PAGE_SIZE)
920 invlpg(addr);
921 PT_UPDATES_FLUSH();
922 }
923
924 PMAP_INLINE void
925 pmap_invalidate_all(pmap_t pmap)
926 {
927
928 CTR1(KTR_PMAP, "pmap_invalidate_all: pmap=%p", pmap);
929
930 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
931 invltlb();
932 }
933
934 PMAP_INLINE void
935 pmap_invalidate_cache(void)
936 {
937
938 wbinvd();
939 }
940 #endif /* !SMP */
941
942 void
943 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva)
944 {
945
946 KASSERT((sva & PAGE_MASK) == 0,
947 ("pmap_invalidate_cache_range: sva not page-aligned"));
948 KASSERT((eva & PAGE_MASK) == 0,
949 ("pmap_invalidate_cache_range: eva not page-aligned"));
950
951 if (cpu_feature & CPUID_SS)
952 ; /* If "Self Snoop" is supported, do nothing. */
953 else if (cpu_feature & CPUID_CLFSH) {
954
955 /*
956 * Otherwise, do per-cache line flush. Use the mfence
957 * instruction to insure that previous stores are
958 * included in the write-back. The processor
959 * propagates flush to other processors in the cache
960 * coherence domain.
961 */
962 mfence();
963 for (; sva < eva; sva += cpu_clflush_line_size)
964 clflush(sva);
965 mfence();
966 } else {
967
968 /*
969 * No targeted cache flush methods are supported by CPU,
970 * globally invalidate cache as a last resort.
971 */
972 pmap_invalidate_cache();
973 }
974 }
975
976 /*
977 * Are we current address space or kernel? N.B. We return FALSE when
978 * a pmap's page table is in use because a kernel thread is borrowing
979 * it. The borrowed page table can change spontaneously, making any
980 * dependence on its continued use subject to a race condition.
981 */
982 static __inline int
983 pmap_is_current(pmap_t pmap)
984 {
985
986 return (pmap == kernel_pmap ||
987 (pmap == vmspace_pmap(curthread->td_proc->p_vmspace) &&
988 (pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] & PG_FRAME)));
989 }
990
991 /*
992 * If the given pmap is not the current or kernel pmap, the returned pte must
993 * be released by passing it to pmap_pte_release().
994 */
995 pt_entry_t *
996 pmap_pte(pmap_t pmap, vm_offset_t va)
997 {
998 pd_entry_t newpf;
999 pd_entry_t *pde;
1000
1001 pde = pmap_pde(pmap, va);
1002 if (*pde & PG_PS)
1003 return (pde);
1004 if (*pde != 0) {
1005 /* are we current address space or kernel? */
1006 if (pmap_is_current(pmap))
1007 return (vtopte(va));
1008 mtx_lock(&PMAP2mutex);
1009 newpf = *pde & PG_FRAME;
1010 if ((*PMAP2 & PG_FRAME) != newpf) {
1011 vm_page_lock_queues();
1012 PT_SET_MA(PADDR2, newpf | PG_V | PG_A | PG_M);
1013 vm_page_unlock_queues();
1014 CTR3(KTR_PMAP, "pmap_pte: pmap=%p va=0x%x newpte=0x%08x",
1015 pmap, va, (*PMAP2 & 0xffffffff));
1016 }
1017
1018 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1)));
1019 }
1020 return (0);
1021 }
1022
1023 /*
1024 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte
1025 * being NULL.
1026 */
1027 static __inline void
1028 pmap_pte_release(pt_entry_t *pte)
1029 {
1030
1031 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2) {
1032 CTR1(KTR_PMAP, "pmap_pte_release: pte=0x%jx",
1033 *PMAP2);
1034 vm_page_lock_queues();
1035 PT_SET_VA(PMAP2, 0, TRUE);
1036 vm_page_unlock_queues();
1037 mtx_unlock(&PMAP2mutex);
1038 }
1039 }
1040
1041 static __inline void
1042 invlcaddr(void *caddr)
1043 {
1044
1045 invlpg((u_int)caddr);
1046 PT_UPDATES_FLUSH();
1047 }
1048
1049 /*
1050 * Super fast pmap_pte routine best used when scanning
1051 * the pv lists. This eliminates many coarse-grained
1052 * invltlb calls. Note that many of the pv list
1053 * scans are across different pmaps. It is very wasteful
1054 * to do an entire invltlb for checking a single mapping.
1055 *
1056 * If the given pmap is not the current pmap, vm_page_queue_mtx
1057 * must be held and curthread pinned to a CPU.
1058 */
1059 static pt_entry_t *
1060 pmap_pte_quick(pmap_t pmap, vm_offset_t va)
1061 {
1062 pd_entry_t newpf;
1063 pd_entry_t *pde;
1064
1065 pde = pmap_pde(pmap, va);
1066 if (*pde & PG_PS)
1067 return (pde);
1068 if (*pde != 0) {
1069 /* are we current address space or kernel? */
1070 if (pmap_is_current(pmap))
1071 return (vtopte(va));
1072 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1073 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1074 newpf = *pde & PG_FRAME;
1075 if ((*PMAP1 & PG_FRAME) != newpf) {
1076 PT_SET_MA(PADDR1, newpf | PG_V | PG_A | PG_M);
1077 CTR3(KTR_PMAP, "pmap_pte_quick: pmap=%p va=0x%x newpte=0x%08x",
1078 pmap, va, (u_long)*PMAP1);
1079
1080 #ifdef SMP
1081 PMAP1cpu = PCPU_GET(cpuid);
1082 #endif
1083 PMAP1changed++;
1084 } else
1085 #ifdef SMP
1086 if (PMAP1cpu != PCPU_GET(cpuid)) {
1087 PMAP1cpu = PCPU_GET(cpuid);
1088 invlcaddr(PADDR1);
1089 PMAP1changedcpu++;
1090 } else
1091 #endif
1092 PMAP1unchanged++;
1093 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1)));
1094 }
1095 return (0);
1096 }
1097
1098 /*
1099 * Routine: pmap_extract
1100 * Function:
1101 * Extract the physical page address associated
1102 * with the given map/virtual_address pair.
1103 */
1104 vm_paddr_t
1105 pmap_extract(pmap_t pmap, vm_offset_t va)
1106 {
1107 vm_paddr_t rtval;
1108 pt_entry_t *pte;
1109 pd_entry_t pde;
1110 pt_entry_t pteval;
1111
1112 rtval = 0;
1113 PMAP_LOCK(pmap);
1114 pde = pmap->pm_pdir[va >> PDRSHIFT];
1115 if (pde != 0) {
1116 if ((pde & PG_PS) != 0) {
1117 rtval = xpmap_mtop(pde & PG_PS_FRAME) | (va & PDRMASK);
1118 PMAP_UNLOCK(pmap);
1119 return rtval;
1120 }
1121 pte = pmap_pte(pmap, va);
1122 pteval = *pte ? xpmap_mtop(*pte) : 0;
1123 rtval = (pteval & PG_FRAME) | (va & PAGE_MASK);
1124 pmap_pte_release(pte);
1125 }
1126 PMAP_UNLOCK(pmap);
1127 return (rtval);
1128 }
1129
1130 /*
1131 * Routine: pmap_extract_ma
1132 * Function:
1133 * Like pmap_extract, but returns machine address
1134 */
1135 vm_paddr_t
1136 pmap_extract_ma(pmap_t pmap, vm_offset_t va)
1137 {
1138 vm_paddr_t rtval;
1139 pt_entry_t *pte;
1140 pd_entry_t pde;
1141
1142 rtval = 0;
1143 PMAP_LOCK(pmap);
1144 pde = pmap->pm_pdir[va >> PDRSHIFT];
1145 if (pde != 0) {
1146 if ((pde & PG_PS) != 0) {
1147 rtval = (pde & ~PDRMASK) | (va & PDRMASK);
1148 PMAP_UNLOCK(pmap);
1149 return rtval;
1150 }
1151 pte = pmap_pte(pmap, va);
1152 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK);
1153 pmap_pte_release(pte);
1154 }
1155 PMAP_UNLOCK(pmap);
1156 return (rtval);
1157 }
1158
1159 /*
1160 * Routine: pmap_extract_and_hold
1161 * Function:
1162 * Atomically extract and hold the physical page
1163 * with the given pmap and virtual address pair
1164 * if that mapping permits the given protection.
1165 */
1166 vm_page_t
1167 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1168 {
1169 pd_entry_t pde;
1170 pt_entry_t pte;
1171 vm_page_t m;
1172 vm_paddr_t pa;
1173
1174 pa = 0;
1175 m = NULL;
1176 PMAP_LOCK(pmap);
1177 retry:
1178 pde = PT_GET(pmap_pde(pmap, va));
1179 if (pde != 0) {
1180 if (pde & PG_PS) {
1181 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1182 if (vm_page_pa_tryrelock(pmap, (pde & PG_PS_FRAME) |
1183 (va & PDRMASK), &pa))
1184 goto retry;
1185 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
1186 (va & PDRMASK));
1187 vm_page_hold(m);
1188 }
1189 } else {
1190 sched_pin();
1191 pte = PT_GET(pmap_pte_quick(pmap, va));
1192 if (*PMAP1)
1193 PT_SET_MA(PADDR1, 0);
1194 if ((pte & PG_V) &&
1195 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1196 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME, &pa))
1197 goto retry;
1198 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
1199 vm_page_hold(m);
1200 }
1201 sched_unpin();
1202 }
1203 }
1204 PA_UNLOCK_COND(pa);
1205 PMAP_UNLOCK(pmap);
1206 return (m);
1207 }
1208
1209 /***************************************************
1210 * Low level mapping routines.....
1211 ***************************************************/
1212
1213 /*
1214 * Add a wired page to the kva.
1215 * Note: not SMP coherent.
1216 */
1217 void
1218 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1219 {
1220 PT_SET_MA(va, xpmap_ptom(pa)| PG_RW | PG_V | pgeflag);
1221 }
1222
1223 void
1224 pmap_kenter_ma(vm_offset_t va, vm_paddr_t ma)
1225 {
1226 pt_entry_t *pte;
1227
1228 pte = vtopte(va);
1229 pte_store_ma(pte, ma | PG_RW | PG_V | pgeflag);
1230 }
1231
1232
1233 static __inline void
1234 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1235 {
1236 PT_SET_MA(va, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0));
1237 }
1238
1239 /*
1240 * Remove a page from the kernel pagetables.
1241 * Note: not SMP coherent.
1242 */
1243 PMAP_INLINE void
1244 pmap_kremove(vm_offset_t va)
1245 {
1246 pt_entry_t *pte;
1247
1248 pte = vtopte(va);
1249 PT_CLEAR_VA(pte, FALSE);
1250 }
1251
1252 /*
1253 * Used to map a range of physical addresses into kernel
1254 * virtual address space.
1255 *
1256 * The value passed in '*virt' is a suggested virtual address for
1257 * the mapping. Architectures which can support a direct-mapped
1258 * physical to virtual region can return the appropriate address
1259 * within that region, leaving '*virt' unchanged. Other
1260 * architectures should map the pages starting at '*virt' and
1261 * update '*virt' with the first usable address after the mapped
1262 * region.
1263 */
1264 vm_offset_t
1265 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1266 {
1267 vm_offset_t va, sva;
1268
1269 va = sva = *virt;
1270 CTR4(KTR_PMAP, "pmap_map: va=0x%x start=0x%jx end=0x%jx prot=0x%x",
1271 va, start, end, prot);
1272 while (start < end) {
1273 pmap_kenter(va, start);
1274 va += PAGE_SIZE;
1275 start += PAGE_SIZE;
1276 }
1277 pmap_invalidate_range(kernel_pmap, sva, va);
1278 *virt = va;
1279 return (sva);
1280 }
1281
1282
1283 /*
1284 * Add a list of wired pages to the kva
1285 * this routine is only used for temporary
1286 * kernel mappings that do not need to have
1287 * page modification or references recorded.
1288 * Note that old mappings are simply written
1289 * over. The page *must* be wired.
1290 * Note: SMP coherent. Uses a ranged shootdown IPI.
1291 */
1292 void
1293 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1294 {
1295 pt_entry_t *endpte, *pte;
1296 vm_paddr_t pa;
1297 vm_offset_t va = sva;
1298 int mclcount = 0;
1299 multicall_entry_t mcl[16];
1300 multicall_entry_t *mclp = mcl;
1301 int error;
1302
1303 CTR2(KTR_PMAP, "pmap_qenter:sva=0x%x count=%d", va, count);
1304 pte = vtopte(sva);
1305 endpte = pte + count;
1306 while (pte < endpte) {
1307 pa = VM_PAGE_TO_MACH(*ma) | pgeflag | PG_RW | PG_V | PG_M | PG_A;
1308
1309 mclp->op = __HYPERVISOR_update_va_mapping;
1310 mclp->args[0] = va;
1311 mclp->args[1] = (uint32_t)(pa & 0xffffffff);
1312 mclp->args[2] = (uint32_t)(pa >> 32);
1313 mclp->args[3] = (*pte & PG_V) ? UVMF_INVLPG|UVMF_ALL : 0;
1314
1315 va += PAGE_SIZE;
1316 pte++;
1317 ma++;
1318 mclp++;
1319 mclcount++;
1320 if (mclcount == 16) {
1321 error = HYPERVISOR_multicall(mcl, mclcount);
1322 mclp = mcl;
1323 mclcount = 0;
1324 KASSERT(error == 0, ("bad multicall %d", error));
1325 }
1326 }
1327 if (mclcount) {
1328 error = HYPERVISOR_multicall(mcl, mclcount);
1329 KASSERT(error == 0, ("bad multicall %d", error));
1330 }
1331
1332 #ifdef INVARIANTS
1333 for (pte = vtopte(sva), mclcount = 0; mclcount < count; mclcount++, pte++)
1334 KASSERT(*pte, ("pte not set for va=0x%x", sva + mclcount*PAGE_SIZE));
1335 #endif
1336 }
1337
1338
1339 /*
1340 * This routine tears out page mappings from the
1341 * kernel -- it is meant only for temporary mappings.
1342 * Note: SMP coherent. Uses a ranged shootdown IPI.
1343 */
1344 void
1345 pmap_qremove(vm_offset_t sva, int count)
1346 {
1347 vm_offset_t va;
1348
1349 CTR2(KTR_PMAP, "pmap_qremove: sva=0x%x count=%d", sva, count);
1350 va = sva;
1351 vm_page_lock_queues();
1352 critical_enter();
1353 while (count-- > 0) {
1354 pmap_kremove(va);
1355 va += PAGE_SIZE;
1356 }
1357 PT_UPDATES_FLUSH();
1358 pmap_invalidate_range(kernel_pmap, sva, va);
1359 critical_exit();
1360 vm_page_unlock_queues();
1361 }
1362
1363 /***************************************************
1364 * Page table page management routines.....
1365 ***************************************************/
1366 static __inline void
1367 pmap_free_zero_pages(vm_page_t free)
1368 {
1369 vm_page_t m;
1370
1371 while (free != NULL) {
1372 m = free;
1373 free = m->right;
1374 vm_page_free_zero(m);
1375 }
1376 }
1377
1378 /*
1379 * This routine unholds page table pages, and if the hold count
1380 * drops to zero, then it decrements the wire count.
1381 */
1382 static __inline int
1383 pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free)
1384 {
1385
1386 --m->wire_count;
1387 if (m->wire_count == 0)
1388 return _pmap_unwire_pte_hold(pmap, m, free);
1389 else
1390 return 0;
1391 }
1392
1393 static int
1394 _pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free)
1395 {
1396 vm_offset_t pteva;
1397
1398 PT_UPDATES_FLUSH();
1399 /*
1400 * unmap the page table page
1401 */
1402 xen_pt_unpin(pmap->pm_pdir[m->pindex]);
1403 /*
1404 * page *might* contain residual mapping :-/
1405 */
1406 PD_CLEAR_VA(pmap, m->pindex, TRUE);
1407 pmap_zero_page(m);
1408 --pmap->pm_stats.resident_count;
1409
1410 /*
1411 * This is a release store so that the ordinary store unmapping
1412 * the page table page is globally performed before TLB shoot-
1413 * down is begun.
1414 */
1415 atomic_subtract_rel_int(&cnt.v_wire_count, 1);
1416
1417 /*
1418 * Do an invltlb to make the invalidated mapping
1419 * take effect immediately.
1420 */
1421 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex);
1422 pmap_invalidate_page(pmap, pteva);
1423
1424 /*
1425 * Put page on a list so that it is released after
1426 * *ALL* TLB shootdown is done
1427 */
1428 m->right = *free;
1429 *free = m;
1430
1431 return 1;
1432 }
1433
1434 /*
1435 * After removing a page table entry, this routine is used to
1436 * conditionally free the page, and manage the hold/wire counts.
1437 */
1438 static int
1439 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, vm_page_t *free)
1440 {
1441 pd_entry_t ptepde;
1442 vm_page_t mpte;
1443
1444 if (va >= VM_MAXUSER_ADDRESS)
1445 return 0;
1446 ptepde = PT_GET(pmap_pde(pmap, va));
1447 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
1448 return pmap_unwire_pte_hold(pmap, mpte, free);
1449 }
1450
1451 void
1452 pmap_pinit0(pmap_t pmap)
1453 {
1454
1455 PMAP_LOCK_INIT(pmap);
1456 pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD);
1457 #ifdef PAE
1458 pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT);
1459 #endif
1460 CPU_ZERO(&pmap->pm_active);
1461 PCPU_SET(curpmap, pmap);
1462 TAILQ_INIT(&pmap->pm_pvchunk);
1463 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1464 mtx_lock_spin(&allpmaps_lock);
1465 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list);
1466 mtx_unlock_spin(&allpmaps_lock);
1467 }
1468
1469 /*
1470 * Initialize a preallocated and zeroed pmap structure,
1471 * such as one in a vmspace structure.
1472 */
1473 int
1474 pmap_pinit(pmap_t pmap)
1475 {
1476 vm_page_t m, ptdpg[NPGPTD + 1];
1477 int npgptd = NPGPTD + 1;
1478 static int color;
1479 int i;
1480
1481 #ifdef HAMFISTED_LOCKING
1482 mtx_lock(&createdelete_lock);
1483 #endif
1484
1485 PMAP_LOCK_INIT(pmap);
1486
1487 /*
1488 * No need to allocate page table space yet but we do need a valid
1489 * page directory table.
1490 */
1491 if (pmap->pm_pdir == NULL) {
1492 pmap->pm_pdir = (pd_entry_t *)kmem_alloc_nofault(kernel_map,
1493 NBPTD);
1494 if (pmap->pm_pdir == NULL) {
1495 PMAP_LOCK_DESTROY(pmap);
1496 #ifdef HAMFISTED_LOCKING
1497 mtx_unlock(&createdelete_lock);
1498 #endif
1499 return (0);
1500 }
1501 #ifdef PAE
1502 pmap->pm_pdpt = (pd_entry_t *)kmem_alloc_nofault(kernel_map, 1);
1503 #endif
1504 }
1505
1506 /*
1507 * allocate the page directory page(s)
1508 */
1509 for (i = 0; i < npgptd;) {
1510 m = vm_page_alloc(NULL, color++,
1511 VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
1512 VM_ALLOC_ZERO);
1513 if (m == NULL)
1514 VM_WAIT;
1515 else {
1516 ptdpg[i++] = m;
1517 }
1518 }
1519 pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD);
1520 for (i = 0; i < NPGPTD; i++) {
1521 if ((ptdpg[i]->flags & PG_ZERO) == 0)
1522 pagezero(&pmap->pm_pdir[i*NPTEPG]);
1523 }
1524
1525 mtx_lock_spin(&allpmaps_lock);
1526 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list);
1527 mtx_unlock_spin(&allpmaps_lock);
1528 /* Wire in kernel global address entries. */
1529
1530 bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t));
1531 #ifdef PAE
1532 pmap_qenter((vm_offset_t)pmap->pm_pdpt, &ptdpg[NPGPTD], 1);
1533 if ((ptdpg[NPGPTD]->flags & PG_ZERO) == 0)
1534 bzero(pmap->pm_pdpt, PAGE_SIZE);
1535 for (i = 0; i < NPGPTD; i++) {
1536 vm_paddr_t ma;
1537
1538 ma = VM_PAGE_TO_MACH(ptdpg[i]);
1539 pmap->pm_pdpt[i] = ma | PG_V;
1540
1541 }
1542 #endif
1543 for (i = 0; i < NPGPTD; i++) {
1544 pt_entry_t *pd;
1545 vm_paddr_t ma;
1546
1547 ma = VM_PAGE_TO_MACH(ptdpg[i]);
1548 pd = pmap->pm_pdir + (i * NPDEPG);
1549 PT_SET_MA(pd, *vtopte((vm_offset_t)pd) & ~(PG_M|PG_A|PG_U|PG_RW));
1550 #if 0
1551 xen_pgd_pin(ma);
1552 #endif
1553 }
1554
1555 #ifdef PAE
1556 PT_SET_MA(pmap->pm_pdpt, *vtopte((vm_offset_t)pmap->pm_pdpt) & ~PG_RW);
1557 #endif
1558 vm_page_lock_queues();
1559 xen_flush_queue();
1560 xen_pgdpt_pin(VM_PAGE_TO_MACH(ptdpg[NPGPTD]));
1561 for (i = 0; i < NPGPTD; i++) {
1562 vm_paddr_t ma = VM_PAGE_TO_MACH(ptdpg[i]);
1563 PT_SET_VA_MA(&pmap->pm_pdir[PTDPTDI + i], ma | PG_V | PG_A, FALSE);
1564 }
1565 xen_flush_queue();
1566 vm_page_unlock_queues();
1567 CPU_ZERO(&pmap->pm_active);
1568 TAILQ_INIT(&pmap->pm_pvchunk);
1569 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1570
1571 #ifdef HAMFISTED_LOCKING
1572 mtx_unlock(&createdelete_lock);
1573 #endif
1574 return (1);
1575 }
1576
1577 /*
1578 * this routine is called if the page table page is not
1579 * mapped correctly.
1580 */
1581 static vm_page_t
1582 _pmap_allocpte(pmap_t pmap, unsigned int ptepindex, int flags)
1583 {
1584 vm_paddr_t ptema;
1585 vm_page_t m;
1586
1587 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT ||
1588 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK,
1589 ("_pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK"));
1590
1591 /*
1592 * Allocate a page table page.
1593 */
1594 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1595 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1596 if (flags & M_WAITOK) {
1597 PMAP_UNLOCK(pmap);
1598 vm_page_unlock_queues();
1599 VM_WAIT;
1600 vm_page_lock_queues();
1601 PMAP_LOCK(pmap);
1602 }
1603
1604 /*
1605 * Indicate the need to retry. While waiting, the page table
1606 * page may have been allocated.
1607 */
1608 return (NULL);
1609 }
1610 if ((m->flags & PG_ZERO) == 0)
1611 pmap_zero_page(m);
1612
1613 /*
1614 * Map the pagetable page into the process address space, if
1615 * it isn't already there.
1616 */
1617 pmap->pm_stats.resident_count++;
1618
1619 ptema = VM_PAGE_TO_MACH(m);
1620 xen_pt_pin(ptema);
1621 PT_SET_VA_MA(&pmap->pm_pdir[ptepindex],
1622 (ptema | PG_U | PG_RW | PG_V | PG_A | PG_M), TRUE);
1623
1624 KASSERT(pmap->pm_pdir[ptepindex],
1625 ("_pmap_allocpte: ptepindex=%d did not get mapped", ptepindex));
1626 return (m);
1627 }
1628
1629 static vm_page_t
1630 pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags)
1631 {
1632 unsigned ptepindex;
1633 pd_entry_t ptema;
1634 vm_page_t m;
1635
1636 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT ||
1637 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK,
1638 ("pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK"));
1639
1640 /*
1641 * Calculate pagetable page index
1642 */
1643 ptepindex = va >> PDRSHIFT;
1644 retry:
1645 /*
1646 * Get the page directory entry
1647 */
1648 ptema = pmap->pm_pdir[ptepindex];
1649
1650 /*
1651 * This supports switching from a 4MB page to a
1652 * normal 4K page.
1653 */
1654 if (ptema & PG_PS) {
1655 /*
1656 * XXX
1657 */
1658 pmap->pm_pdir[ptepindex] = 0;
1659 ptema = 0;
1660 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
1661 pmap_invalidate_all(kernel_pmap);
1662 }
1663
1664 /*
1665 * If the page table page is mapped, we just increment the
1666 * hold count, and activate it.
1667 */
1668 if (ptema & PG_V) {
1669 m = PHYS_TO_VM_PAGE(xpmap_mtop(ptema) & PG_FRAME);
1670 m->wire_count++;
1671 } else {
1672 /*
1673 * Here if the pte page isn't mapped, or if it has
1674 * been deallocated.
1675 */
1676 CTR3(KTR_PMAP, "pmap_allocpte: pmap=%p va=0x%08x flags=0x%x",
1677 pmap, va, flags);
1678 m = _pmap_allocpte(pmap, ptepindex, flags);
1679 if (m == NULL && (flags & M_WAITOK))
1680 goto retry;
1681
1682 KASSERT(pmap->pm_pdir[ptepindex], ("ptepindex=%d did not get mapped", ptepindex));
1683 }
1684 return (m);
1685 }
1686
1687
1688 /***************************************************
1689 * Pmap allocation/deallocation routines.
1690 ***************************************************/
1691
1692 #ifdef SMP
1693 /*
1694 * Deal with a SMP shootdown of other users of the pmap that we are
1695 * trying to dispose of. This can be a bit hairy.
1696 */
1697 static cpuset_t *lazymask;
1698 static u_int lazyptd;
1699 static volatile u_int lazywait;
1700
1701 void pmap_lazyfix_action(void);
1702
1703 void
1704 pmap_lazyfix_action(void)
1705 {
1706
1707 #ifdef COUNT_IPIS
1708 (*ipi_lazypmap_counts[PCPU_GET(cpuid)])++;
1709 #endif
1710 if (rcr3() == lazyptd)
1711 load_cr3(PCPU_GET(curpcb)->pcb_cr3);
1712 CPU_CLR_ATOMIC(PCPU_GET(cpuid), lazymask);
1713 atomic_store_rel_int(&lazywait, 1);
1714 }
1715
1716 static void
1717 pmap_lazyfix_self(u_int cpuid)
1718 {
1719
1720 if (rcr3() == lazyptd)
1721 load_cr3(PCPU_GET(curpcb)->pcb_cr3);
1722 CPU_CLR_ATOMIC(cpuid, lazymask);
1723 }
1724
1725
1726 static void
1727 pmap_lazyfix(pmap_t pmap)
1728 {
1729 cpuset_t mymask, mask;
1730 u_int cpuid, spins;
1731 int lsb;
1732
1733 mask = pmap->pm_active;
1734 while (!CPU_EMPTY(&mask)) {
1735 spins = 50000000;
1736
1737 /* Find least significant set bit. */
1738 lsb = cpusetobj_ffs(&mask);
1739 MPASS(lsb != 0);
1740 lsb--;
1741 CPU_SETOF(lsb, &mask);
1742 mtx_lock_spin(&smp_ipi_mtx);
1743 #ifdef PAE
1744 lazyptd = vtophys(pmap->pm_pdpt);
1745 #else
1746 lazyptd = vtophys(pmap->pm_pdir);
1747 #endif
1748 cpuid = PCPU_GET(cpuid);
1749
1750 /* Use a cpuset just for having an easy check. */
1751 CPU_SETOF(cpuid, &mymask);
1752 if (!CPU_CMP(&mask, &mymask)) {
1753 lazymask = &pmap->pm_active;
1754 pmap_lazyfix_self(cpuid);
1755 } else {
1756 atomic_store_rel_int((u_int *)&lazymask,
1757 (u_int)&pmap->pm_active);
1758 atomic_store_rel_int(&lazywait, 0);
1759 ipi_selected(mask, IPI_LAZYPMAP);
1760 while (lazywait == 0) {
1761 ia32_pause();
1762 if (--spins == 0)
1763 break;
1764 }
1765 }
1766 mtx_unlock_spin(&smp_ipi_mtx);
1767 if (spins == 0)
1768 printf("pmap_lazyfix: spun for 50000000\n");
1769 mask = pmap->pm_active;
1770 }
1771 }
1772
1773 #else /* SMP */
1774
1775 /*
1776 * Cleaning up on uniprocessor is easy. For various reasons, we're
1777 * unlikely to have to even execute this code, including the fact
1778 * that the cleanup is deferred until the parent does a wait(2), which
1779 * means that another userland process has run.
1780 */
1781 static void
1782 pmap_lazyfix(pmap_t pmap)
1783 {
1784 u_int cr3;
1785
1786 cr3 = vtophys(pmap->pm_pdir);
1787 if (cr3 == rcr3()) {
1788 load_cr3(PCPU_GET(curpcb)->pcb_cr3);
1789 CPU_CLR(PCPU_GET(cpuid), &pmap->pm_active);
1790 }
1791 }
1792 #endif /* SMP */
1793
1794 /*
1795 * Release any resources held by the given physical map.
1796 * Called when a pmap initialized by pmap_pinit is being released.
1797 * Should only be called if the map contains no valid mappings.
1798 */
1799 void
1800 pmap_release(pmap_t pmap)
1801 {
1802 vm_page_t m, ptdpg[2*NPGPTD+1];
1803 vm_paddr_t ma;
1804 int i;
1805 #ifdef PAE
1806 int npgptd = NPGPTD + 1;
1807 #else
1808 int npgptd = NPGPTD;
1809 #endif
1810 KASSERT(pmap->pm_stats.resident_count == 0,
1811 ("pmap_release: pmap resident count %ld != 0",
1812 pmap->pm_stats.resident_count));
1813 PT_UPDATES_FLUSH();
1814
1815 #ifdef HAMFISTED_LOCKING
1816 mtx_lock(&createdelete_lock);
1817 #endif
1818
1819 pmap_lazyfix(pmap);
1820 mtx_lock_spin(&allpmaps_lock);
1821 LIST_REMOVE(pmap, pm_list);
1822 mtx_unlock_spin(&allpmaps_lock);
1823
1824 for (i = 0; i < NPGPTD; i++)
1825 ptdpg[i] = PHYS_TO_VM_PAGE(vtophys(pmap->pm_pdir + (i*NPDEPG)) & PG_FRAME);
1826 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD);
1827 #ifdef PAE
1828 ptdpg[NPGPTD] = PHYS_TO_VM_PAGE(vtophys(pmap->pm_pdpt));
1829 #endif
1830
1831 for (i = 0; i < npgptd; i++) {
1832 m = ptdpg[i];
1833 ma = VM_PAGE_TO_MACH(m);
1834 /* unpinning L1 and L2 treated the same */
1835 #if 0
1836 xen_pgd_unpin(ma);
1837 #else
1838 if (i == NPGPTD)
1839 xen_pgd_unpin(ma);
1840 #endif
1841 #ifdef PAE
1842 if (i < NPGPTD)
1843 KASSERT(VM_PAGE_TO_MACH(m) == (pmap->pm_pdpt[i] & PG_FRAME),
1844 ("pmap_release: got wrong ptd page"));
1845 #endif
1846 m->wire_count--;
1847 atomic_subtract_int(&cnt.v_wire_count, 1);
1848 vm_page_free(m);
1849 }
1850 #ifdef PAE
1851 pmap_qremove((vm_offset_t)pmap->pm_pdpt, 1);
1852 #endif
1853 PMAP_LOCK_DESTROY(pmap);
1854
1855 #ifdef HAMFISTED_LOCKING
1856 mtx_unlock(&createdelete_lock);
1857 #endif
1858 }
1859
1860 static int
1861 kvm_size(SYSCTL_HANDLER_ARGS)
1862 {
1863 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE;
1864
1865 return sysctl_handle_long(oidp, &ksize, 0, req);
1866 }
1867 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
1868 0, 0, kvm_size, "IU", "Size of KVM");
1869
1870 static int
1871 kvm_free(SYSCTL_HANDLER_ARGS)
1872 {
1873 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
1874
1875 return sysctl_handle_long(oidp, &kfree, 0, req);
1876 }
1877 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
1878 0, 0, kvm_free, "IU", "Amount of KVM free");
1879
1880 /*
1881 * grow the number of kernel page table entries, if needed
1882 */
1883 void
1884 pmap_growkernel(vm_offset_t addr)
1885 {
1886 struct pmap *pmap;
1887 vm_paddr_t ptppaddr;
1888 vm_page_t nkpg;
1889 pd_entry_t newpdir;
1890
1891 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
1892 if (kernel_vm_end == 0) {
1893 kernel_vm_end = KERNBASE;
1894 nkpt = 0;
1895 while (pdir_pde(PTD, kernel_vm_end)) {
1896 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1);
1897 nkpt++;
1898 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
1899 kernel_vm_end = kernel_map->max_offset;
1900 break;
1901 }
1902 }
1903 }
1904 addr = roundup2(addr, PAGE_SIZE * NPTEPG);
1905 if (addr - 1 >= kernel_map->max_offset)
1906 addr = kernel_map->max_offset;
1907 while (kernel_vm_end < addr) {
1908 if (pdir_pde(PTD, kernel_vm_end)) {
1909 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1);
1910 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
1911 kernel_vm_end = kernel_map->max_offset;
1912 break;
1913 }
1914 continue;
1915 }
1916
1917 /*
1918 * This index is bogus, but out of the way
1919 */
1920 nkpg = vm_page_alloc(NULL, nkpt,
1921 VM_ALLOC_NOOBJ | VM_ALLOC_SYSTEM | VM_ALLOC_WIRED);
1922 if (!nkpg)
1923 panic("pmap_growkernel: no memory to grow kernel");
1924
1925 nkpt++;
1926
1927 pmap_zero_page(nkpg);
1928 ptppaddr = VM_PAGE_TO_PHYS(nkpg);
1929 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M);
1930 vm_page_lock_queues();
1931 PD_SET_VA(kernel_pmap, (kernel_vm_end >> PDRSHIFT), newpdir, TRUE);
1932 mtx_lock_spin(&allpmaps_lock);
1933 LIST_FOREACH(pmap, &allpmaps, pm_list)
1934 PD_SET_VA(pmap, (kernel_vm_end >> PDRSHIFT), newpdir, TRUE);
1935
1936 mtx_unlock_spin(&allpmaps_lock);
1937 vm_page_unlock_queues();
1938
1939 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1);
1940 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
1941 kernel_vm_end = kernel_map->max_offset;
1942 break;
1943 }
1944 }
1945 }
1946
1947
1948 /***************************************************
1949 * page management routines.
1950 ***************************************************/
1951
1952 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
1953 CTASSERT(_NPCM == 11);
1954
1955 static __inline struct pv_chunk *
1956 pv_to_chunk(pv_entry_t pv)
1957 {
1958
1959 return (struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK);
1960 }
1961
1962 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
1963
1964 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
1965 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
1966
1967 static uint32_t pc_freemask[11] = {
1968 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
1969 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
1970 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
1971 PC_FREE0_9, PC_FREE10
1972 };
1973
1974 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
1975 "Current number of pv entries");
1976
1977 #ifdef PV_STATS
1978 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
1979
1980 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
1981 "Current number of pv entry chunks");
1982 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
1983 "Current number of pv entry chunks allocated");
1984 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
1985 "Current number of pv entry chunks frees");
1986 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
1987 "Number of times tried to get a chunk page but failed.");
1988
1989 static long pv_entry_frees, pv_entry_allocs;
1990 static int pv_entry_spare;
1991
1992 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
1993 "Current number of pv entry frees");
1994 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
1995 "Current number of pv entry allocs");
1996 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
1997 "Current number of spare pv entries");
1998
1999 static int pmap_collect_inactive, pmap_collect_active;
2000
2001 SYSCTL_INT(_vm_pmap, OID_AUTO, pmap_collect_inactive, CTLFLAG_RD, &pmap_collect_inactive, 0,
2002 "Current number times pmap_collect called on inactive queue");
2003 SYSCTL_INT(_vm_pmap, OID_AUTO, pmap_collect_active, CTLFLAG_RD, &pmap_collect_active, 0,
2004 "Current number times pmap_collect called on active queue");
2005 #endif
2006
2007 /*
2008 * We are in a serious low memory condition. Resort to
2009 * drastic measures to free some pages so we can allocate
2010 * another pv entry chunk. This is normally called to
2011 * unmap inactive pages, and if necessary, active pages.
2012 */
2013 static void
2014 pmap_collect(pmap_t locked_pmap, struct vpgqueues *vpq)
2015 {
2016 pmap_t pmap;
2017 pt_entry_t *pte, tpte;
2018 pv_entry_t next_pv, pv;
2019 vm_offset_t va;
2020 vm_page_t m, free;
2021
2022 sched_pin();
2023 TAILQ_FOREACH(m, &vpq->pl, pageq) {
2024 if ((m->flags & PG_MARKER) != 0 || m->hold_count || m->busy)
2025 continue;
2026 TAILQ_FOREACH_SAFE(pv, &m->md.pv_list, pv_list, next_pv) {
2027 va = pv->pv_va;
2028 pmap = PV_PMAP(pv);
2029 /* Avoid deadlock and lock recursion. */
2030 if (pmap > locked_pmap)
2031 PMAP_LOCK(pmap);
2032 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap))
2033 continue;
2034 pmap->pm_stats.resident_count--;
2035 pte = pmap_pte_quick(pmap, va);
2036 tpte = pte_load_clear(pte);
2037 KASSERT((tpte & PG_W) == 0,
2038 ("pmap_collect: wired pte %#jx", (uintmax_t)tpte));
2039 if (tpte & PG_A)
2040 vm_page_aflag_set(m, PGA_REFERENCED);
2041 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2042 vm_page_dirty(m);
2043 free = NULL;
2044 pmap_unuse_pt(pmap, va, &free);
2045 pmap_invalidate_page(pmap, va);
2046 pmap_free_zero_pages(free);
2047 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
2048 free_pv_entry(pmap, pv);
2049 if (pmap != locked_pmap)
2050 PMAP_UNLOCK(pmap);
2051 }
2052 if (TAILQ_EMPTY(&m->md.pv_list))
2053 vm_page_aflag_clear(m, PGA_WRITEABLE);
2054 }
2055 sched_unpin();
2056 }
2057
2058
2059 /*
2060 * free the pv_entry back to the free list
2061 */
2062 static void
2063 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2064 {
2065 vm_page_t m;
2066 struct pv_chunk *pc;
2067 int idx, field, bit;
2068
2069 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2070 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2071 PV_STAT(pv_entry_frees++);
2072 PV_STAT(pv_entry_spare++);
2073 pv_entry_count--;
2074 pc = pv_to_chunk(pv);
2075 idx = pv - &pc->pc_pventry[0];
2076 field = idx / 32;
2077 bit = idx % 32;
2078 pc->pc_map[field] |= 1ul << bit;
2079 /* move to head of list */
2080 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2081 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2082 for (idx = 0; idx < _NPCM; idx++)
2083 if (pc->pc_map[idx] != pc_freemask[idx])
2084 return;
2085 PV_STAT(pv_entry_spare -= _NPCPV);
2086 PV_STAT(pc_chunk_count--);
2087 PV_STAT(pc_chunk_frees++);
2088 /* entire chunk is free, return it */
2089 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2090 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2091 pmap_qremove((vm_offset_t)pc, 1);
2092 vm_page_unwire(m, 0);
2093 vm_page_free(m);
2094 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2095 }
2096
2097 /*
2098 * get a new pv_entry, allocating a block from the system
2099 * when needed.
2100 */
2101 static pv_entry_t
2102 get_pv_entry(pmap_t pmap, int try)
2103 {
2104 static const struct timeval printinterval = { 60, 0 };
2105 static struct timeval lastprint;
2106 static vm_pindex_t colour;
2107 struct vpgqueues *pq;
2108 int bit, field;
2109 pv_entry_t pv;
2110 struct pv_chunk *pc;
2111 vm_page_t m;
2112
2113 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2114 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2115 PV_STAT(pv_entry_allocs++);
2116 pv_entry_count++;
2117 if (pv_entry_count > pv_entry_high_water)
2118 if (ratecheck(&lastprint, &printinterval))
2119 printf("Approaching the limit on PV entries, consider "
2120 "increasing either the vm.pmap.shpgperproc or the "
2121 "vm.pmap.pv_entry_max tunable.\n");
2122 pq = NULL;
2123 retry:
2124 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2125 if (pc != NULL) {
2126 for (field = 0; field < _NPCM; field++) {
2127 if (pc->pc_map[field]) {
2128 bit = bsfl(pc->pc_map[field]);
2129 break;
2130 }
2131 }
2132 if (field < _NPCM) {
2133 pv = &pc->pc_pventry[field * 32 + bit];
2134 pc->pc_map[field] &= ~(1ul << bit);
2135 /* If this was the last item, move it to tail */
2136 for (field = 0; field < _NPCM; field++)
2137 if (pc->pc_map[field] != 0) {
2138 PV_STAT(pv_entry_spare--);
2139 return (pv); /* not full, return */
2140 }
2141 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2142 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2143 PV_STAT(pv_entry_spare--);
2144 return (pv);
2145 }
2146 }
2147 /*
2148 * Access to the ptelist "pv_vafree" is synchronized by the page
2149 * queues lock. If "pv_vafree" is currently non-empty, it will
2150 * remain non-empty until pmap_ptelist_alloc() completes.
2151 */
2152 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, colour, (pq ==
2153 &vm_page_queues[PQ_ACTIVE] ? VM_ALLOC_SYSTEM : VM_ALLOC_NORMAL) |
2154 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
2155 if (try) {
2156 pv_entry_count--;
2157 PV_STAT(pc_chunk_tryfail++);
2158 return (NULL);
2159 }
2160 /*
2161 * Reclaim pv entries: At first, destroy mappings to
2162 * inactive pages. After that, if a pv chunk entry
2163 * is still needed, destroy mappings to active pages.
2164 */
2165 if (pq == NULL) {
2166 PV_STAT(pmap_collect_inactive++);
2167 pq = &vm_page_queues[PQ_INACTIVE];
2168 } else if (pq == &vm_page_queues[PQ_INACTIVE]) {
2169 PV_STAT(pmap_collect_active++);
2170 pq = &vm_page_queues[PQ_ACTIVE];
2171 } else
2172 panic("get_pv_entry: increase vm.pmap.shpgperproc");
2173 pmap_collect(pmap, pq);
2174 goto retry;
2175 }
2176 PV_STAT(pc_chunk_count++);
2177 PV_STAT(pc_chunk_allocs++);
2178 colour++;
2179 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree);
2180 pmap_qenter((vm_offset_t)pc, &m, 1);
2181 if ((m->flags & PG_ZERO) == 0)
2182 pagezero(pc);
2183 pc->pc_pmap = pmap;
2184 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
2185 for (field = 1; field < _NPCM; field++)
2186 pc->pc_map[field] = pc_freemask[field];
2187 pv = &pc->pc_pventry[0];
2188 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2189 PV_STAT(pv_entry_spare += _NPCPV - 1);
2190 return (pv);
2191 }
2192
2193 static __inline pv_entry_t
2194 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2195 {
2196 pv_entry_t pv;
2197
2198 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2199 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
2200 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2201 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list);
2202 break;
2203 }
2204 }
2205 return (pv);
2206 }
2207
2208 static void
2209 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2210 {
2211 pv_entry_t pv;
2212
2213 pv = pmap_pvh_remove(pvh, pmap, va);
2214 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2215 free_pv_entry(pmap, pv);
2216 }
2217
2218 static void
2219 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
2220 {
2221
2222 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2223 pmap_pvh_free(&m->md, pmap, va);
2224 if (TAILQ_EMPTY(&m->md.pv_list))
2225 vm_page_aflag_clear(m, PGA_WRITEABLE);
2226 }
2227
2228 /*
2229 * Conditionally create a pv entry.
2230 */
2231 static boolean_t
2232 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2233 {
2234 pv_entry_t pv;
2235
2236 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2237 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2238 if (pv_entry_count < pv_entry_high_water &&
2239 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2240 pv->pv_va = va;
2241 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
2242 return (TRUE);
2243 } else
2244 return (FALSE);
2245 }
2246
2247 /*
2248 * pmap_remove_pte: do the things to unmap a page in a process
2249 */
2250 static int
2251 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va, vm_page_t *free)
2252 {
2253 pt_entry_t oldpte;
2254 vm_page_t m;
2255
2256 CTR3(KTR_PMAP, "pmap_remove_pte: pmap=%p *ptq=0x%x va=0x%x",
2257 pmap, (u_long)*ptq, va);
2258
2259 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2260 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2261 oldpte = *ptq;
2262 PT_SET_VA_MA(ptq, 0, TRUE);
2263 if (oldpte & PG_W)
2264 pmap->pm_stats.wired_count -= 1;
2265 /*
2266 * Machines that don't support invlpg, also don't support
2267 * PG_G.
2268 */
2269 if (oldpte & PG_G)
2270 pmap_invalidate_page(kernel_pmap, va);
2271 pmap->pm_stats.resident_count -= 1;
2272 if (oldpte & PG_MANAGED) {
2273 m = PHYS_TO_VM_PAGE(xpmap_mtop(oldpte) & PG_FRAME);
2274 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2275 vm_page_dirty(m);
2276 if (oldpte & PG_A)
2277 vm_page_aflag_set(m, PGA_REFERENCED);
2278 pmap_remove_entry(pmap, m, va);
2279 }
2280 return (pmap_unuse_pt(pmap, va, free));
2281 }
2282
2283 /*
2284 * Remove a single page from a process address space
2285 */
2286 static void
2287 pmap_remove_page(pmap_t pmap, vm_offset_t va, vm_page_t *free)
2288 {
2289 pt_entry_t *pte;
2290
2291 CTR2(KTR_PMAP, "pmap_remove_page: pmap=%p va=0x%x",
2292 pmap, va);
2293
2294 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2295 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
2296 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2297 if ((pte = pmap_pte_quick(pmap, va)) == NULL || (*pte & PG_V) == 0)
2298 return;
2299 pmap_remove_pte(pmap, pte, va, free);
2300 pmap_invalidate_page(pmap, va);
2301 if (*PMAP1)
2302 PT_SET_MA(PADDR1, 0);
2303
2304 }
2305
2306 /*
2307 * Remove the given range of addresses from the specified map.
2308 *
2309 * It is assumed that the start and end are properly
2310 * rounded to the page size.
2311 */
2312 void
2313 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2314 {
2315 vm_offset_t pdnxt;
2316 pd_entry_t ptpaddr;
2317 pt_entry_t *pte;
2318 vm_page_t free = NULL;
2319 int anyvalid;
2320
2321 CTR3(KTR_PMAP, "pmap_remove: pmap=%p sva=0x%x eva=0x%x",
2322 pmap, sva, eva);
2323
2324 /*
2325 * Perform an unsynchronized read. This is, however, safe.
2326 */
2327 if (pmap->pm_stats.resident_count == 0)
2328 return;
2329
2330 anyvalid = 0;
2331
2332 vm_page_lock_queues();
2333 sched_pin();
2334 PMAP_LOCK(pmap);
2335
2336 /*
2337 * special handling of removing one page. a very
2338 * common operation and easy to short circuit some
2339 * code.
2340 */
2341 if ((sva + PAGE_SIZE == eva) &&
2342 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) {
2343 pmap_remove_page(pmap, sva, &free);
2344 goto out;
2345 }
2346
2347 for (; sva < eva; sva = pdnxt) {
2348 unsigned pdirindex;
2349
2350 /*
2351 * Calculate index for next page table.
2352 */
2353 pdnxt = (sva + NBPDR) & ~PDRMASK;
2354 if (pmap->pm_stats.resident_count == 0)
2355 break;
2356
2357 pdirindex = sva >> PDRSHIFT;
2358 ptpaddr = pmap->pm_pdir[pdirindex];
2359
2360 /*
2361 * Weed out invalid mappings. Note: we assume that the page
2362 * directory table is always allocated, and in kernel virtual.
2363 */
2364 if (ptpaddr == 0)
2365 continue;
2366
2367 /*
2368 * Check for large page.
2369 */
2370 if ((ptpaddr & PG_PS) != 0) {
2371 PD_CLEAR_VA(pmap, pdirindex, TRUE);
2372 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
2373 anyvalid = 1;
2374 continue;
2375 }
2376
2377 /*
2378 * Limit our scan to either the end of the va represented
2379 * by the current page table page, or to the end of the
2380 * range being removed.
2381 */
2382 if (pdnxt > eva)
2383 pdnxt = eva;
2384
2385 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
2386 sva += PAGE_SIZE) {
2387 if ((*pte & PG_V) == 0)
2388 continue;
2389
2390 /*
2391 * The TLB entry for a PG_G mapping is invalidated
2392 * by pmap_remove_pte().
2393 */
2394 if ((*pte & PG_G) == 0)
2395 anyvalid = 1;
2396 if (pmap_remove_pte(pmap, pte, sva, &free))
2397 break;
2398 }
2399 }
2400 PT_UPDATES_FLUSH();
2401 if (*PMAP1)
2402 PT_SET_VA_MA(PMAP1, 0, TRUE);
2403 out:
2404 if (anyvalid)
2405 pmap_invalidate_all(pmap);
2406 sched_unpin();
2407 vm_page_unlock_queues();
2408 PMAP_UNLOCK(pmap);
2409 pmap_free_zero_pages(free);
2410 }
2411
2412 /*
2413 * Routine: pmap_remove_all
2414 * Function:
2415 * Removes this physical page from
2416 * all physical maps in which it resides.
2417 * Reflects back modify bits to the pager.
2418 *
2419 * Notes:
2420 * Original versions of this routine were very
2421 * inefficient because they iteratively called
2422 * pmap_remove (slow...)
2423 */
2424
2425 void
2426 pmap_remove_all(vm_page_t m)
2427 {
2428 pv_entry_t pv;
2429 pmap_t pmap;
2430 pt_entry_t *pte, tpte;
2431 vm_page_t free;
2432
2433 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2434 ("pmap_remove_all: page %p is not managed", m));
2435 free = NULL;
2436 vm_page_lock_queues();
2437 sched_pin();
2438 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
2439 pmap = PV_PMAP(pv);
2440 PMAP_LOCK(pmap);
2441 pmap->pm_stats.resident_count--;
2442 pte = pmap_pte_quick(pmap, pv->pv_va);
2443
2444 tpte = *pte;
2445 PT_SET_VA_MA(pte, 0, TRUE);
2446 if (tpte & PG_W)
2447 pmap->pm_stats.wired_count--;
2448 if (tpte & PG_A)
2449 vm_page_aflag_set(m, PGA_REFERENCED);
2450
2451 /*
2452 * Update the vm_page_t clean and reference bits.
2453 */
2454 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2455 vm_page_dirty(m);
2456 pmap_unuse_pt(pmap, pv->pv_va, &free);
2457 pmap_invalidate_page(pmap, pv->pv_va);
2458 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
2459 free_pv_entry(pmap, pv);
2460 PMAP_UNLOCK(pmap);
2461 }
2462 vm_page_aflag_clear(m, PGA_WRITEABLE);
2463 PT_UPDATES_FLUSH();
2464 if (*PMAP1)
2465 PT_SET_MA(PADDR1, 0);
2466 sched_unpin();
2467 vm_page_unlock_queues();
2468 pmap_free_zero_pages(free);
2469 }
2470
2471 /*
2472 * Set the physical protection on the
2473 * specified range of this map as requested.
2474 */
2475 void
2476 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
2477 {
2478 vm_offset_t pdnxt;
2479 pd_entry_t ptpaddr;
2480 pt_entry_t *pte;
2481 int anychanged;
2482
2483 CTR4(KTR_PMAP, "pmap_protect: pmap=%p sva=0x%x eva=0x%x prot=0x%x",
2484 pmap, sva, eva, prot);
2485
2486 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
2487 pmap_remove(pmap, sva, eva);
2488 return;
2489 }
2490
2491 #ifdef PAE
2492 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
2493 (VM_PROT_WRITE|VM_PROT_EXECUTE))
2494 return;
2495 #else
2496 if (prot & VM_PROT_WRITE)
2497 return;
2498 #endif
2499
2500 anychanged = 0;
2501
2502 vm_page_lock_queues();
2503 sched_pin();
2504 PMAP_LOCK(pmap);
2505 for (; sva < eva; sva = pdnxt) {
2506 pt_entry_t obits, pbits;
2507 unsigned pdirindex;
2508
2509 pdnxt = (sva + NBPDR) & ~PDRMASK;
2510
2511 pdirindex = sva >> PDRSHIFT;
2512 ptpaddr = pmap->pm_pdir[pdirindex];
2513
2514 /*
2515 * Weed out invalid mappings. Note: we assume that the page
2516 * directory table is always allocated, and in kernel virtual.
2517 */
2518 if (ptpaddr == 0)
2519 continue;
2520
2521 /*
2522 * Check for large page.
2523 */
2524 if ((ptpaddr & PG_PS) != 0) {
2525 if ((prot & VM_PROT_WRITE) == 0)
2526 pmap->pm_pdir[pdirindex] &= ~(PG_M|PG_RW);
2527 #ifdef PAE
2528 if ((prot & VM_PROT_EXECUTE) == 0)
2529 pmap->pm_pdir[pdirindex] |= pg_nx;
2530 #endif
2531 anychanged = 1;
2532 continue;
2533 }
2534
2535 if (pdnxt > eva)
2536 pdnxt = eva;
2537
2538 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
2539 sva += PAGE_SIZE) {
2540 vm_page_t m;
2541
2542 retry:
2543 /*
2544 * Regardless of whether a pte is 32 or 64 bits in
2545 * size, PG_RW, PG_A, and PG_M are among the least
2546 * significant 32 bits.
2547 */
2548 obits = pbits = *pte;
2549 if ((pbits & PG_V) == 0)
2550 continue;
2551
2552 if ((prot & VM_PROT_WRITE) == 0) {
2553 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
2554 (PG_MANAGED | PG_M | PG_RW)) {
2555 m = PHYS_TO_VM_PAGE(xpmap_mtop(pbits) &
2556 PG_FRAME);
2557 vm_page_dirty(m);
2558 }
2559 pbits &= ~(PG_RW | PG_M);
2560 }
2561 #ifdef PAE
2562 if ((prot & VM_PROT_EXECUTE) == 0)
2563 pbits |= pg_nx;
2564 #endif
2565
2566 if (pbits != obits) {
2567 obits = *pte;
2568 PT_SET_VA_MA(pte, pbits, TRUE);
2569 if (*pte != pbits)
2570 goto retry;
2571 if (obits & PG_G)
2572 pmap_invalidate_page(pmap, sva);
2573 else
2574 anychanged = 1;
2575 }
2576 }
2577 }
2578 PT_UPDATES_FLUSH();
2579 if (*PMAP1)
2580 PT_SET_VA_MA(PMAP1, 0, TRUE);
2581 if (anychanged)
2582 pmap_invalidate_all(pmap);
2583 sched_unpin();
2584 vm_page_unlock_queues();
2585 PMAP_UNLOCK(pmap);
2586 }
2587
2588 /*
2589 * Insert the given physical page (p) at
2590 * the specified virtual address (v) in the
2591 * target physical map with the protection requested.
2592 *
2593 * If specified, the page will be wired down, meaning
2594 * that the related pte can not be reclaimed.
2595 *
2596 * NB: This is the only routine which MAY NOT lazy-evaluate
2597 * or lose information. That is, this routine must actually
2598 * insert this page into the given map NOW.
2599 */
2600 void
2601 pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m,
2602 vm_prot_t prot, boolean_t wired)
2603 {
2604 pd_entry_t *pde;
2605 pt_entry_t *pte;
2606 pt_entry_t newpte, origpte;
2607 pv_entry_t pv;
2608 vm_paddr_t opa, pa;
2609 vm_page_t mpte, om;
2610 boolean_t invlva;
2611
2612 CTR6(KTR_PMAP, "pmap_enter: pmap=%08p va=0x%08x access=0x%x ma=0x%08x prot=0x%x wired=%d",
2613 pmap, va, access, VM_PAGE_TO_MACH(m), prot, wired);
2614 va = trunc_page(va);
2615 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
2616 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
2617 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)",
2618 va));
2619 KASSERT((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) != 0,
2620 ("pmap_enter: page %p is not busy", m));
2621
2622 mpte = NULL;
2623
2624 vm_page_lock_queues();
2625 PMAP_LOCK(pmap);
2626 sched_pin();
2627
2628 /*
2629 * In the case that a page table page is not
2630 * resident, we are creating it here.
2631 */
2632 if (va < VM_MAXUSER_ADDRESS) {
2633 mpte = pmap_allocpte(pmap, va, M_WAITOK);
2634 }
2635
2636 pde = pmap_pde(pmap, va);
2637 if ((*pde & PG_PS) != 0)
2638 panic("pmap_enter: attempted pmap_enter on 4MB page");
2639 pte = pmap_pte_quick(pmap, va);
2640
2641 /*
2642 * Page Directory table entry not valid, we need a new PT page
2643 */
2644 if (pte == NULL) {
2645 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x",
2646 (uintmax_t)pmap->pm_pdir[va >> PDRSHIFT], va);
2647 }
2648
2649 pa = VM_PAGE_TO_PHYS(m);
2650 om = NULL;
2651 opa = origpte = 0;
2652
2653 #if 0
2654 KASSERT((*pte & PG_V) || (*pte == 0), ("address set but not valid pte=%p *pte=0x%016jx",
2655 pte, *pte));
2656 #endif
2657 origpte = *pte;
2658 if (origpte)
2659 origpte = xpmap_mtop(origpte);
2660 opa = origpte & PG_FRAME;
2661
2662 /*
2663 * Mapping has not changed, must be protection or wiring change.
2664 */
2665 if (origpte && (opa == pa)) {
2666 /*
2667 * Wiring change, just update stats. We don't worry about
2668 * wiring PT pages as they remain resident as long as there
2669 * are valid mappings in them. Hence, if a user page is wired,
2670 * the PT page will be also.
2671 */
2672 if (wired && ((origpte & PG_W) == 0))
2673 pmap->pm_stats.wired_count++;
2674 else if (!wired && (origpte & PG_W))
2675 pmap->pm_stats.wired_count--;
2676
2677 /*
2678 * Remove extra pte reference
2679 */
2680 if (mpte)
2681 mpte->wire_count--;
2682
2683 if (origpte & PG_MANAGED) {
2684 om = m;
2685 pa |= PG_MANAGED;
2686 }
2687 goto validate;
2688 }
2689
2690 pv = NULL;
2691
2692 /*
2693 * Mapping has changed, invalidate old range and fall through to
2694 * handle validating new mapping.
2695 */
2696 if (opa) {
2697 if (origpte & PG_W)
2698 pmap->pm_stats.wired_count--;
2699 if (origpte & PG_MANAGED) {
2700 om = PHYS_TO_VM_PAGE(opa);
2701 pv = pmap_pvh_remove(&om->md, pmap, va);
2702 } else if (va < VM_MAXUSER_ADDRESS)
2703 printf("va=0x%x is unmanaged :-( \n", va);
2704
2705 if (mpte != NULL) {
2706 mpte->wire_count--;
2707 KASSERT(mpte->wire_count > 0,
2708 ("pmap_enter: missing reference to page table page,"
2709 " va: 0x%x", va));
2710 }
2711 } else
2712 pmap->pm_stats.resident_count++;
2713
2714 /*
2715 * Enter on the PV list if part of our managed memory.
2716 */
2717 if ((m->oflags & VPO_UNMANAGED) == 0) {
2718 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva,
2719 ("pmap_enter: managed mapping within the clean submap"));
2720 if (pv == NULL)
2721 pv = get_pv_entry(pmap, FALSE);
2722 pv->pv_va = va;
2723 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
2724 pa |= PG_MANAGED;
2725 } else if (pv != NULL)
2726 free_pv_entry(pmap, pv);
2727
2728 /*
2729 * Increment counters
2730 */
2731 if (wired)
2732 pmap->pm_stats.wired_count++;
2733
2734 validate:
2735 /*
2736 * Now validate mapping with desired protection/wiring.
2737 */
2738 newpte = (pt_entry_t)(pa | PG_V);
2739 if ((prot & VM_PROT_WRITE) != 0) {
2740 newpte |= PG_RW;
2741 if ((newpte & PG_MANAGED) != 0)
2742 vm_page_aflag_set(m, PGA_WRITEABLE);
2743 }
2744 #ifdef PAE
2745 if ((prot & VM_PROT_EXECUTE) == 0)
2746 newpte |= pg_nx;
2747 #endif
2748 if (wired)
2749 newpte |= PG_W;
2750 if (va < VM_MAXUSER_ADDRESS)
2751 newpte |= PG_U;
2752 if (pmap == kernel_pmap)
2753 newpte |= pgeflag;
2754
2755 critical_enter();
2756 /*
2757 * if the mapping or permission bits are different, we need
2758 * to update the pte.
2759 */
2760 if ((origpte & ~(PG_M|PG_A)) != newpte) {
2761 if (origpte) {
2762 invlva = FALSE;
2763 origpte = *pte;
2764 PT_SET_VA(pte, newpte | PG_A, FALSE);
2765 if (origpte & PG_A) {
2766 if (origpte & PG_MANAGED)
2767 vm_page_aflag_set(om, PGA_REFERENCED);
2768 if (opa != VM_PAGE_TO_PHYS(m))
2769 invlva = TRUE;
2770 #ifdef PAE
2771 if ((origpte & PG_NX) == 0 &&
2772 (newpte & PG_NX) != 0)
2773 invlva = TRUE;
2774 #endif
2775 }
2776 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
2777 if ((origpte & PG_MANAGED) != 0)
2778 vm_page_dirty(om);
2779 if ((prot & VM_PROT_WRITE) == 0)
2780 invlva = TRUE;
2781 }
2782 if ((origpte & PG_MANAGED) != 0 &&
2783 TAILQ_EMPTY(&om->md.pv_list))
2784 vm_page_aflag_clear(om, PGA_WRITEABLE);
2785 if (invlva)
2786 pmap_invalidate_page(pmap, va);
2787 } else{
2788 PT_SET_VA(pte, newpte | PG_A, FALSE);
2789 }
2790
2791 }
2792 PT_UPDATES_FLUSH();
2793 critical_exit();
2794 if (*PMAP1)
2795 PT_SET_VA_MA(PMAP1, 0, TRUE);
2796 sched_unpin();
2797 vm_page_unlock_queues();
2798 PMAP_UNLOCK(pmap);
2799 }
2800
2801 /*
2802 * Maps a sequence of resident pages belonging to the same object.
2803 * The sequence begins with the given page m_start. This page is
2804 * mapped at the given virtual address start. Each subsequent page is
2805 * mapped at a virtual address that is offset from start by the same
2806 * amount as the page is offset from m_start within the object. The
2807 * last page in the sequence is the page with the largest offset from
2808 * m_start that can be mapped at a virtual address less than the given
2809 * virtual address end. Not every virtual page between start and end
2810 * is mapped; only those for which a resident page exists with the
2811 * corresponding offset from m_start are mapped.
2812 */
2813 void
2814 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
2815 vm_page_t m_start, vm_prot_t prot)
2816 {
2817 vm_page_t m, mpte;
2818 vm_pindex_t diff, psize;
2819 multicall_entry_t mcl[16];
2820 multicall_entry_t *mclp = mcl;
2821 int error, count = 0;
2822
2823 VM_OBJECT_LOCK_ASSERT(m_start->object, MA_OWNED);
2824 psize = atop(end - start);
2825
2826 mpte = NULL;
2827 m = m_start;
2828 vm_page_lock_queues();
2829 PMAP_LOCK(pmap);
2830 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
2831 mpte = pmap_enter_quick_locked(&mclp, &count, pmap, start + ptoa(diff), m,
2832 prot, mpte);
2833 m = TAILQ_NEXT(m, listq);
2834 if (count == 16) {
2835 error = HYPERVISOR_multicall(mcl, count);
2836 KASSERT(error == 0, ("bad multicall %d", error));
2837 mclp = mcl;
2838 count = 0;
2839 }
2840 }
2841 if (count) {
2842 error = HYPERVISOR_multicall(mcl, count);
2843 KASSERT(error == 0, ("bad multicall %d", error));
2844 }
2845 vm_page_unlock_queues();
2846 PMAP_UNLOCK(pmap);
2847 }
2848
2849 /*
2850 * this code makes some *MAJOR* assumptions:
2851 * 1. Current pmap & pmap exists.
2852 * 2. Not wired.
2853 * 3. Read access.
2854 * 4. No page table pages.
2855 * but is *MUCH* faster than pmap_enter...
2856 */
2857
2858 void
2859 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
2860 {
2861 multicall_entry_t mcl, *mclp;
2862 int count = 0;
2863 mclp = &mcl;
2864
2865 CTR4(KTR_PMAP, "pmap_enter_quick: pmap=%p va=0x%x m=%p prot=0x%x",
2866 pmap, va, m, prot);
2867
2868 vm_page_lock_queues();
2869 PMAP_LOCK(pmap);
2870 (void)pmap_enter_quick_locked(&mclp, &count, pmap, va, m, prot, NULL);
2871 if (count)
2872 HYPERVISOR_multicall(&mcl, count);
2873 vm_page_unlock_queues();
2874 PMAP_UNLOCK(pmap);
2875 }
2876
2877 #ifdef notyet
2878 void
2879 pmap_enter_quick_range(pmap_t pmap, vm_offset_t *addrs, vm_page_t *pages, vm_prot_t *prots, int count)
2880 {
2881 int i, error, index = 0;
2882 multicall_entry_t mcl[16];
2883 multicall_entry_t *mclp = mcl;
2884
2885 PMAP_LOCK(pmap);
2886 for (i = 0; i < count; i++, addrs++, pages++, prots++) {
2887 if (!pmap_is_prefaultable_locked(pmap, *addrs))
2888 continue;
2889
2890 (void) pmap_enter_quick_locked(&mclp, &index, pmap, *addrs, *pages, *prots, NULL);
2891 if (index == 16) {
2892 error = HYPERVISOR_multicall(mcl, index);
2893 mclp = mcl;
2894 index = 0;
2895 KASSERT(error == 0, ("bad multicall %d", error));
2896 }
2897 }
2898 if (index) {
2899 error = HYPERVISOR_multicall(mcl, index);
2900 KASSERT(error == 0, ("bad multicall %d", error));
2901 }
2902
2903 PMAP_UNLOCK(pmap);
2904 }
2905 #endif
2906
2907 static vm_page_t
2908 pmap_enter_quick_locked(multicall_entry_t **mclpp, int *count, pmap_t pmap, vm_offset_t va, vm_page_t m,
2909 vm_prot_t prot, vm_page_t mpte)
2910 {
2911 pt_entry_t *pte;
2912 vm_paddr_t pa;
2913 vm_page_t free;
2914 multicall_entry_t *mcl = *mclpp;
2915
2916 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
2917 (m->oflags & VPO_UNMANAGED) != 0,
2918 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
2919 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2920 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2921
2922 /*
2923 * In the case that a page table page is not
2924 * resident, we are creating it here.
2925 */
2926 if (va < VM_MAXUSER_ADDRESS) {
2927 unsigned ptepindex;
2928 pd_entry_t ptema;
2929
2930 /*
2931 * Calculate pagetable page index
2932 */
2933 ptepindex = va >> PDRSHIFT;
2934 if (mpte && (mpte->pindex == ptepindex)) {
2935 mpte->wire_count++;
2936 } else {
2937 /*
2938 * Get the page directory entry
2939 */
2940 ptema = pmap->pm_pdir[ptepindex];
2941
2942 /*
2943 * If the page table page is mapped, we just increment
2944 * the hold count, and activate it.
2945 */
2946 if (ptema & PG_V) {
2947 if (ptema & PG_PS)
2948 panic("pmap_enter_quick: unexpected mapping into 4MB page");
2949 mpte = PHYS_TO_VM_PAGE(xpmap_mtop(ptema) & PG_FRAME);
2950 mpte->wire_count++;
2951 } else {
2952 mpte = _pmap_allocpte(pmap, ptepindex,
2953 M_NOWAIT);
2954 if (mpte == NULL)
2955 return (mpte);
2956 }
2957 }
2958 } else {
2959 mpte = NULL;
2960 }
2961
2962 /*
2963 * This call to vtopte makes the assumption that we are
2964 * entering the page into the current pmap. In order to support
2965 * quick entry into any pmap, one would likely use pmap_pte_quick.
2966 * But that isn't as quick as vtopte.
2967 */
2968 KASSERT(pmap_is_current(pmap), ("entering pages in non-current pmap"));
2969 pte = vtopte(va);
2970 if (*pte & PG_V) {
2971 if (mpte != NULL) {
2972 mpte->wire_count--;
2973 mpte = NULL;
2974 }
2975 return (mpte);
2976 }
2977
2978 /*
2979 * Enter on the PV list if part of our managed memory.
2980 */
2981 if ((m->oflags & VPO_UNMANAGED) == 0 &&
2982 !pmap_try_insert_pv_entry(pmap, va, m)) {
2983 if (mpte != NULL) {
2984 free = NULL;
2985 if (pmap_unwire_pte_hold(pmap, mpte, &free)) {
2986 pmap_invalidate_page(pmap, va);
2987 pmap_free_zero_pages(free);
2988 }
2989
2990 mpte = NULL;
2991 }
2992 return (mpte);
2993 }
2994
2995 /*
2996 * Increment counters
2997 */
2998 pmap->pm_stats.resident_count++;
2999
3000 pa = VM_PAGE_TO_PHYS(m);
3001 #ifdef PAE
3002 if ((prot & VM_PROT_EXECUTE) == 0)
3003 pa |= pg_nx;
3004 #endif
3005
3006 #if 0
3007 /*
3008 * Now validate mapping with RO protection
3009 */
3010 if ((m->oflags & VPO_UNMANAGED) != 0)
3011 pte_store(pte, pa | PG_V | PG_U);
3012 else
3013 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
3014 #else
3015 /*
3016 * Now validate mapping with RO protection
3017 */
3018 if ((m->oflags & VPO_UNMANAGED) != 0)
3019 pa = xpmap_ptom(pa | PG_V | PG_U);
3020 else
3021 pa = xpmap_ptom(pa | PG_V | PG_U | PG_MANAGED);
3022
3023 mcl->op = __HYPERVISOR_update_va_mapping;
3024 mcl->args[0] = va;
3025 mcl->args[1] = (uint32_t)(pa & 0xffffffff);
3026 mcl->args[2] = (uint32_t)(pa >> 32);
3027 mcl->args[3] = 0;
3028 *mclpp = mcl + 1;
3029 *count = *count + 1;
3030 #endif
3031 return mpte;
3032 }
3033
3034 /*
3035 * Make a temporary mapping for a physical address. This is only intended
3036 * to be used for panic dumps.
3037 */
3038 void *
3039 pmap_kenter_temporary(vm_paddr_t pa, int i)
3040 {
3041 vm_offset_t va;
3042 vm_paddr_t ma = xpmap_ptom(pa);
3043
3044 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
3045 PT_SET_MA(va, (ma & ~PAGE_MASK) | PG_V | pgeflag);
3046 invlpg(va);
3047 return ((void *)crashdumpmap);
3048 }
3049
3050 /*
3051 * This code maps large physical mmap regions into the
3052 * processor address space. Note that some shortcuts
3053 * are taken, but the code works.
3054 */
3055 void
3056 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr,
3057 vm_object_t object, vm_pindex_t pindex,
3058 vm_size_t size)
3059 {
3060 pd_entry_t *pde;
3061 vm_paddr_t pa, ptepa;
3062 vm_page_t p;
3063 int pat_mode;
3064
3065 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED);
3066 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3067 ("pmap_object_init_pt: non-device object"));
3068 if (pseflag &&
3069 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
3070 if (!vm_object_populate(object, pindex, pindex + atop(size)))
3071 return;
3072 p = vm_page_lookup(object, pindex);
3073 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3074 ("pmap_object_init_pt: invalid page %p", p));
3075 pat_mode = p->md.pat_mode;
3076 /*
3077 * Abort the mapping if the first page is not physically
3078 * aligned to a 2/4MB page boundary.
3079 */
3080 ptepa = VM_PAGE_TO_PHYS(p);
3081 if (ptepa & (NBPDR - 1))
3082 return;
3083 /*
3084 * Skip the first page. Abort the mapping if the rest of
3085 * the pages are not physically contiguous or have differing
3086 * memory attributes.
3087 */
3088 p = TAILQ_NEXT(p, listq);
3089 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
3090 pa += PAGE_SIZE) {
3091 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3092 ("pmap_object_init_pt: invalid page %p", p));
3093 if (pa != VM_PAGE_TO_PHYS(p) ||
3094 pat_mode != p->md.pat_mode)
3095 return;
3096 p = TAILQ_NEXT(p, listq);
3097 }
3098 /* Map using 2/4MB pages. */
3099 PMAP_LOCK(pmap);
3100 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa +
3101 size; pa += NBPDR) {
3102 pde = pmap_pde(pmap, addr);
3103 if (*pde == 0) {
3104 pde_store(pde, pa | PG_PS | PG_M | PG_A |
3105 PG_U | PG_RW | PG_V);
3106 pmap->pm_stats.resident_count += NBPDR /
3107 PAGE_SIZE;
3108 pmap_pde_mappings++;
3109 }
3110 /* Else continue on if the PDE is already valid. */
3111 addr += NBPDR;
3112 }
3113 PMAP_UNLOCK(pmap);
3114 }
3115 }
3116
3117 /*
3118 * Routine: pmap_change_wiring
3119 * Function: Change the wiring attribute for a map/virtual-address
3120 * pair.
3121 * In/out conditions:
3122 * The mapping must already exist in the pmap.
3123 */
3124 void
3125 pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired)
3126 {
3127 pt_entry_t *pte;
3128
3129 vm_page_lock_queues();
3130 PMAP_LOCK(pmap);
3131 pte = pmap_pte(pmap, va);
3132
3133 if (wired && !pmap_pte_w(pte)) {
3134 PT_SET_VA_MA((pte), *(pte) | PG_W, TRUE);
3135 pmap->pm_stats.wired_count++;
3136 } else if (!wired && pmap_pte_w(pte)) {
3137 PT_SET_VA_MA((pte), *(pte) & ~PG_W, TRUE);
3138 pmap->pm_stats.wired_count--;
3139 }
3140
3141 /*
3142 * Wiring is not a hardware characteristic so there is no need to
3143 * invalidate TLB.
3144 */
3145 pmap_pte_release(pte);
3146 PMAP_UNLOCK(pmap);
3147 vm_page_unlock_queues();
3148 }
3149
3150
3151
3152 /*
3153 * Copy the range specified by src_addr/len
3154 * from the source map to the range dst_addr/len
3155 * in the destination map.
3156 *
3157 * This routine is only advisory and need not do anything.
3158 */
3159
3160 void
3161 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
3162 vm_offset_t src_addr)
3163 {
3164 vm_page_t free;
3165 vm_offset_t addr;
3166 vm_offset_t end_addr = src_addr + len;
3167 vm_offset_t pdnxt;
3168
3169 if (dst_addr != src_addr)
3170 return;
3171
3172 if (!pmap_is_current(src_pmap)) {
3173 CTR2(KTR_PMAP,
3174 "pmap_copy, skipping: pdir[PTDPTDI]=0x%jx PTDpde[0]=0x%jx",
3175 (src_pmap->pm_pdir[PTDPTDI] & PG_FRAME), (PTDpde[0] & PG_FRAME));
3176
3177 return;
3178 }
3179 CTR5(KTR_PMAP, "pmap_copy: dst_pmap=%p src_pmap=%p dst_addr=0x%x len=%d src_addr=0x%x",
3180 dst_pmap, src_pmap, dst_addr, len, src_addr);
3181
3182 #ifdef HAMFISTED_LOCKING
3183 mtx_lock(&createdelete_lock);
3184 #endif
3185
3186 vm_page_lock_queues();
3187 if (dst_pmap < src_pmap) {
3188 PMAP_LOCK(dst_pmap);
3189 PMAP_LOCK(src_pmap);
3190 } else {
3191 PMAP_LOCK(src_pmap);
3192 PMAP_LOCK(dst_pmap);
3193 }
3194 sched_pin();
3195 for (addr = src_addr; addr < end_addr; addr = pdnxt) {
3196 pt_entry_t *src_pte, *dst_pte;
3197 vm_page_t dstmpte, srcmpte;
3198 pd_entry_t srcptepaddr;
3199 unsigned ptepindex;
3200
3201 KASSERT(addr < UPT_MIN_ADDRESS,
3202 ("pmap_copy: invalid to pmap_copy page tables"));
3203
3204 pdnxt = (addr + NBPDR) & ~PDRMASK;
3205 ptepindex = addr >> PDRSHIFT;
3206
3207 srcptepaddr = PT_GET(&src_pmap->pm_pdir[ptepindex]);
3208 if (srcptepaddr == 0)
3209 continue;
3210
3211 if (srcptepaddr & PG_PS) {
3212 if (dst_pmap->pm_pdir[ptepindex] == 0) {
3213 PD_SET_VA(dst_pmap, ptepindex, srcptepaddr & ~PG_W, TRUE);
3214 dst_pmap->pm_stats.resident_count +=
3215 NBPDR / PAGE_SIZE;
3216 }
3217 continue;
3218 }
3219
3220 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME);
3221 KASSERT(srcmpte->wire_count > 0,
3222 ("pmap_copy: source page table page is unused"));
3223
3224 if (pdnxt > end_addr)
3225 pdnxt = end_addr;
3226
3227 src_pte = vtopte(addr);
3228 while (addr < pdnxt) {
3229 pt_entry_t ptetemp;
3230 ptetemp = *src_pte;
3231 /*
3232 * we only virtual copy managed pages
3233 */
3234 if ((ptetemp & PG_MANAGED) != 0) {
3235 dstmpte = pmap_allocpte(dst_pmap, addr,
3236 M_NOWAIT);
3237 if (dstmpte == NULL)
3238 break;
3239 dst_pte = pmap_pte_quick(dst_pmap, addr);
3240 if (*dst_pte == 0 &&
3241 pmap_try_insert_pv_entry(dst_pmap, addr,
3242 PHYS_TO_VM_PAGE(xpmap_mtop(ptetemp) & PG_FRAME))) {
3243 /*
3244 * Clear the wired, modified, and
3245 * accessed (referenced) bits
3246 * during the copy.
3247 */
3248 KASSERT(ptetemp != 0, ("src_pte not set"));
3249 PT_SET_VA_MA(dst_pte, ptetemp & ~(PG_W | PG_M | PG_A), TRUE /* XXX debug */);
3250 KASSERT(*dst_pte == (ptetemp & ~(PG_W | PG_M | PG_A)),
3251 ("no pmap copy expected: 0x%jx saw: 0x%jx",
3252 ptetemp & ~(PG_W | PG_M | PG_A), *dst_pte));
3253 dst_pmap->pm_stats.resident_count++;
3254 } else {
3255 free = NULL;
3256 if (pmap_unwire_pte_hold(dst_pmap,
3257 dstmpte, &free)) {
3258 pmap_invalidate_page(dst_pmap,
3259 addr);
3260 pmap_free_zero_pages(free);
3261 }
3262 }
3263 if (dstmpte->wire_count >= srcmpte->wire_count)
3264 break;
3265 }
3266 addr += PAGE_SIZE;
3267 src_pte++;
3268 }
3269 }
3270 PT_UPDATES_FLUSH();
3271 sched_unpin();
3272 vm_page_unlock_queues();
3273 PMAP_UNLOCK(src_pmap);
3274 PMAP_UNLOCK(dst_pmap);
3275
3276 #ifdef HAMFISTED_LOCKING
3277 mtx_unlock(&createdelete_lock);
3278 #endif
3279 }
3280
3281 static __inline void
3282 pagezero(void *page)
3283 {
3284 #if defined(I686_CPU)
3285 if (cpu_class == CPUCLASS_686) {
3286 #if defined(CPU_ENABLE_SSE)
3287 if (cpu_feature & CPUID_SSE2)
3288 sse2_pagezero(page);
3289 else
3290 #endif
3291 i686_pagezero(page);
3292 } else
3293 #endif
3294 bzero(page, PAGE_SIZE);
3295 }
3296
3297 /*
3298 * pmap_zero_page zeros the specified hardware page by mapping
3299 * the page into KVM and using bzero to clear its contents.
3300 */
3301 void
3302 pmap_zero_page(vm_page_t m)
3303 {
3304 struct sysmaps *sysmaps;
3305
3306 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
3307 mtx_lock(&sysmaps->lock);
3308 if (*sysmaps->CMAP2)
3309 panic("pmap_zero_page: CMAP2 busy");
3310 sched_pin();
3311 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | VM_PAGE_TO_MACH(m) | PG_A | PG_M);
3312 pagezero(sysmaps->CADDR2);
3313 PT_SET_MA(sysmaps->CADDR2, 0);
3314 sched_unpin();
3315 mtx_unlock(&sysmaps->lock);
3316 }
3317
3318 /*
3319 * pmap_zero_page_area zeros the specified hardware page by mapping
3320 * the page into KVM and using bzero to clear its contents.
3321 *
3322 * off and size may not cover an area beyond a single hardware page.
3323 */
3324 void
3325 pmap_zero_page_area(vm_page_t m, int off, int size)
3326 {
3327 struct sysmaps *sysmaps;
3328
3329 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
3330 mtx_lock(&sysmaps->lock);
3331 if (*sysmaps->CMAP2)
3332 panic("pmap_zero_page: CMAP2 busy");
3333 sched_pin();
3334 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | VM_PAGE_TO_MACH(m) | PG_A | PG_M);
3335
3336 if (off == 0 && size == PAGE_SIZE)
3337 pagezero(sysmaps->CADDR2);
3338 else
3339 bzero((char *)sysmaps->CADDR2 + off, size);
3340 PT_SET_MA(sysmaps->CADDR2, 0);
3341 sched_unpin();
3342 mtx_unlock(&sysmaps->lock);
3343 }
3344
3345 /*
3346 * pmap_zero_page_idle zeros the specified hardware page by mapping
3347 * the page into KVM and using bzero to clear its contents. This
3348 * is intended to be called from the vm_pagezero process only and
3349 * outside of Giant.
3350 */
3351 void
3352 pmap_zero_page_idle(vm_page_t m)
3353 {
3354
3355 if (*CMAP3)
3356 panic("pmap_zero_page: CMAP3 busy");
3357 sched_pin();
3358 PT_SET_MA(CADDR3, PG_V | PG_RW | VM_PAGE_TO_MACH(m) | PG_A | PG_M);
3359 pagezero(CADDR3);
3360 PT_SET_MA(CADDR3, 0);
3361 sched_unpin();
3362 }
3363
3364 /*
3365 * pmap_copy_page copies the specified (machine independent)
3366 * page by mapping the page into virtual memory and using
3367 * bcopy to copy the page, one machine dependent page at a
3368 * time.
3369 */
3370 void
3371 pmap_copy_page(vm_page_t src, vm_page_t dst)
3372 {
3373 struct sysmaps *sysmaps;
3374
3375 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
3376 mtx_lock(&sysmaps->lock);
3377 if (*sysmaps->CMAP1)
3378 panic("pmap_copy_page: CMAP1 busy");
3379 if (*sysmaps->CMAP2)
3380 panic("pmap_copy_page: CMAP2 busy");
3381 sched_pin();
3382 PT_SET_MA(sysmaps->CADDR1, PG_V | VM_PAGE_TO_MACH(src) | PG_A);
3383 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | VM_PAGE_TO_MACH(dst) | PG_A | PG_M);
3384 bcopy(sysmaps->CADDR1, sysmaps->CADDR2, PAGE_SIZE);
3385 PT_SET_MA(sysmaps->CADDR1, 0);
3386 PT_SET_MA(sysmaps->CADDR2, 0);
3387 sched_unpin();
3388 mtx_unlock(&sysmaps->lock);
3389 }
3390
3391 /*
3392 * Returns true if the pmap's pv is one of the first
3393 * 16 pvs linked to from this page. This count may
3394 * be changed upwards or downwards in the future; it
3395 * is only necessary that true be returned for a small
3396 * subset of pmaps for proper page aging.
3397 */
3398 boolean_t
3399 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
3400 {
3401 pv_entry_t pv;
3402 int loops = 0;
3403 boolean_t rv;
3404
3405 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3406 ("pmap_page_exists_quick: page %p is not managed", m));
3407 rv = FALSE;
3408 vm_page_lock_queues();
3409 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
3410 if (PV_PMAP(pv) == pmap) {
3411 rv = TRUE;
3412 break;
3413 }
3414 loops++;
3415 if (loops >= 16)
3416 break;
3417 }
3418 vm_page_unlock_queues();
3419 return (rv);
3420 }
3421
3422 /*
3423 * pmap_page_wired_mappings:
3424 *
3425 * Return the number of managed mappings to the given physical page
3426 * that are wired.
3427 */
3428 int
3429 pmap_page_wired_mappings(vm_page_t m)
3430 {
3431 pv_entry_t pv;
3432 pt_entry_t *pte;
3433 pmap_t pmap;
3434 int count;
3435
3436 count = 0;
3437 if ((m->oflags & VPO_UNMANAGED) != 0)
3438 return (count);
3439 vm_page_lock_queues();
3440 sched_pin();
3441 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
3442 pmap = PV_PMAP(pv);
3443 PMAP_LOCK(pmap);
3444 pte = pmap_pte_quick(pmap, pv->pv_va);
3445 if ((*pte & PG_W) != 0)
3446 count++;
3447 PMAP_UNLOCK(pmap);
3448 }
3449 sched_unpin();
3450 vm_page_unlock_queues();
3451 return (count);
3452 }
3453
3454 /*
3455 * Returns TRUE if the given page is mapped individually or as part of
3456 * a 4mpage. Otherwise, returns FALSE.
3457 */
3458 boolean_t
3459 pmap_page_is_mapped(vm_page_t m)
3460 {
3461 boolean_t rv;
3462
3463 if ((m->oflags & VPO_UNMANAGED) != 0)
3464 return (FALSE);
3465 vm_page_lock_queues();
3466 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
3467 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list);
3468 vm_page_unlock_queues();
3469 return (rv);
3470 }
3471
3472 /*
3473 * Remove all pages from specified address space
3474 * this aids process exit speeds. Also, this code
3475 * is special cased for current process only, but
3476 * can have the more generic (and slightly slower)
3477 * mode enabled. This is much faster than pmap_remove
3478 * in the case of running down an entire address space.
3479 */
3480 void
3481 pmap_remove_pages(pmap_t pmap)
3482 {
3483 pt_entry_t *pte, tpte;
3484 vm_page_t m, free = NULL;
3485 pv_entry_t pv;
3486 struct pv_chunk *pc, *npc;
3487 int field, idx;
3488 int32_t bit;
3489 uint32_t inuse, bitmask;
3490 int allfree;
3491
3492 CTR1(KTR_PMAP, "pmap_remove_pages: pmap=%p", pmap);
3493
3494 if (pmap != vmspace_pmap(curthread->td_proc->p_vmspace)) {
3495 printf("warning: pmap_remove_pages called with non-current pmap\n");
3496 return;
3497 }
3498 vm_page_lock_queues();
3499 KASSERT(pmap_is_current(pmap), ("removing pages from non-current pmap"));
3500 PMAP_LOCK(pmap);
3501 sched_pin();
3502 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
3503 allfree = 1;
3504 for (field = 0; field < _NPCM; field++) {
3505 inuse = (~(pc->pc_map[field])) & pc_freemask[field];
3506 while (inuse != 0) {
3507 bit = bsfl(inuse);
3508 bitmask = 1UL << bit;
3509 idx = field * 32 + bit;
3510 pv = &pc->pc_pventry[idx];
3511 inuse &= ~bitmask;
3512
3513 pte = vtopte(pv->pv_va);
3514 tpte = *pte ? xpmap_mtop(*pte) : 0;
3515
3516 if (tpte == 0) {
3517 printf(
3518 "TPTE at %p IS ZERO @ VA %08x\n",
3519 pte, pv->pv_va);
3520 panic("bad pte");
3521 }
3522
3523 /*
3524 * We cannot remove wired pages from a process' mapping at this time
3525 */
3526 if (tpte & PG_W) {
3527 allfree = 0;
3528 continue;
3529 }
3530
3531 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
3532 KASSERT(m->phys_addr == (tpte & PG_FRAME),
3533 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
3534 m, (uintmax_t)m->phys_addr,
3535 (uintmax_t)tpte));
3536
3537 KASSERT(m < &vm_page_array[vm_page_array_size],
3538 ("pmap_remove_pages: bad tpte %#jx",
3539 (uintmax_t)tpte));
3540
3541
3542 PT_CLEAR_VA(pte, FALSE);
3543
3544 /*
3545 * Update the vm_page_t clean/reference bits.
3546 */
3547 if (tpte & PG_M)
3548 vm_page_dirty(m);
3549
3550 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
3551 if (TAILQ_EMPTY(&m->md.pv_list))
3552 vm_page_aflag_clear(m, PGA_WRITEABLE);
3553
3554 pmap_unuse_pt(pmap, pv->pv_va, &free);
3555
3556 /* Mark free */
3557 PV_STAT(pv_entry_frees++);
3558 PV_STAT(pv_entry_spare++);
3559 pv_entry_count--;
3560 pc->pc_map[field] |= bitmask;
3561 pmap->pm_stats.resident_count--;
3562 }
3563 }
3564 PT_UPDATES_FLUSH();
3565 if (allfree) {
3566 PV_STAT(pv_entry_spare -= _NPCPV);
3567 PV_STAT(pc_chunk_count--);
3568 PV_STAT(pc_chunk_frees++);
3569 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3570 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
3571 pmap_qremove((vm_offset_t)pc, 1);
3572 vm_page_unwire(m, 0);
3573 vm_page_free(m);
3574 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
3575 }
3576 }
3577 PT_UPDATES_FLUSH();
3578 if (*PMAP1)
3579 PT_SET_MA(PADDR1, 0);
3580
3581 sched_unpin();
3582 pmap_invalidate_all(pmap);
3583 vm_page_unlock_queues();
3584 PMAP_UNLOCK(pmap);
3585 pmap_free_zero_pages(free);
3586 }
3587
3588 /*
3589 * pmap_is_modified:
3590 *
3591 * Return whether or not the specified physical page was modified
3592 * in any physical maps.
3593 */
3594 boolean_t
3595 pmap_is_modified(vm_page_t m)
3596 {
3597 pv_entry_t pv;
3598 pt_entry_t *pte;
3599 pmap_t pmap;
3600 boolean_t rv;
3601
3602 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3603 ("pmap_is_modified: page %p is not managed", m));
3604 rv = FALSE;
3605
3606 /*
3607 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be
3608 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
3609 * is clear, no PTEs can have PG_M set.
3610 */
3611 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
3612 if ((m->oflags & VPO_BUSY) == 0 &&
3613 (m->aflags & PGA_WRITEABLE) == 0)
3614 return (rv);
3615 vm_page_lock_queues();
3616 sched_pin();
3617 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
3618 pmap = PV_PMAP(pv);
3619 PMAP_LOCK(pmap);
3620 pte = pmap_pte_quick(pmap, pv->pv_va);
3621 rv = (*pte & PG_M) != 0;
3622 PMAP_UNLOCK(pmap);
3623 if (rv)
3624 break;
3625 }
3626 if (*PMAP1)
3627 PT_SET_MA(PADDR1, 0);
3628 sched_unpin();
3629 vm_page_unlock_queues();
3630 return (rv);
3631 }
3632
3633 /*
3634 * pmap_is_prefaultable:
3635 *
3636 * Return whether or not the specified virtual address is elgible
3637 * for prefault.
3638 */
3639 static boolean_t
3640 pmap_is_prefaultable_locked(pmap_t pmap, vm_offset_t addr)
3641 {
3642 pt_entry_t *pte;
3643 boolean_t rv = FALSE;
3644
3645 return (rv);
3646
3647 if (pmap_is_current(pmap) && *pmap_pde(pmap, addr)) {
3648 pte = vtopte(addr);
3649 rv = (*pte == 0);
3650 }
3651 return (rv);
3652 }
3653
3654 boolean_t
3655 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
3656 {
3657 boolean_t rv;
3658
3659 PMAP_LOCK(pmap);
3660 rv = pmap_is_prefaultable_locked(pmap, addr);
3661 PMAP_UNLOCK(pmap);
3662 return (rv);
3663 }
3664
3665 boolean_t
3666 pmap_is_referenced(vm_page_t m)
3667 {
3668 pv_entry_t pv;
3669 pt_entry_t *pte;
3670 pmap_t pmap;
3671 boolean_t rv;
3672
3673 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3674 ("pmap_is_referenced: page %p is not managed", m));
3675 rv = FALSE;
3676 vm_page_lock_queues();
3677 sched_pin();
3678 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
3679 pmap = PV_PMAP(pv);
3680 PMAP_LOCK(pmap);
3681 pte = pmap_pte_quick(pmap, pv->pv_va);
3682 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V);
3683 PMAP_UNLOCK(pmap);
3684 if (rv)
3685 break;
3686 }
3687 if (*PMAP1)
3688 PT_SET_MA(PADDR1, 0);
3689 sched_unpin();
3690 vm_page_unlock_queues();
3691 return (rv);
3692 }
3693
3694 void
3695 pmap_map_readonly(pmap_t pmap, vm_offset_t va, int len)
3696 {
3697 int i, npages = round_page(len) >> PAGE_SHIFT;
3698 for (i = 0; i < npages; i++) {
3699 pt_entry_t *pte;
3700 pte = pmap_pte(pmap, (vm_offset_t)(va + i*PAGE_SIZE));
3701 vm_page_lock_queues();
3702 pte_store(pte, xpmap_mtop(*pte & ~(PG_RW|PG_M)));
3703 vm_page_unlock_queues();
3704 PMAP_MARK_PRIV(xpmap_mtop(*pte));
3705 pmap_pte_release(pte);
3706 }
3707 }
3708
3709 void
3710 pmap_map_readwrite(pmap_t pmap, vm_offset_t va, int len)
3711 {
3712 int i, npages = round_page(len) >> PAGE_SHIFT;
3713 for (i = 0; i < npages; i++) {
3714 pt_entry_t *pte;
3715 pte = pmap_pte(pmap, (vm_offset_t)(va + i*PAGE_SIZE));
3716 PMAP_MARK_UNPRIV(xpmap_mtop(*pte));
3717 vm_page_lock_queues();
3718 pte_store(pte, xpmap_mtop(*pte) | (PG_RW|PG_M));
3719 vm_page_unlock_queues();
3720 pmap_pte_release(pte);
3721 }
3722 }
3723
3724 /*
3725 * Clear the write and modified bits in each of the given page's mappings.
3726 */
3727 void
3728 pmap_remove_write(vm_page_t m)
3729 {
3730 pv_entry_t pv;
3731 pmap_t pmap;
3732 pt_entry_t oldpte, *pte;
3733
3734 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3735 ("pmap_remove_write: page %p is not managed", m));
3736
3737 /*
3738 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by
3739 * another thread while the object is locked. Thus, if PGA_WRITEABLE
3740 * is clear, no page table entries need updating.
3741 */
3742 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
3743 if ((m->oflags & VPO_BUSY) == 0 &&
3744 (m->aflags & PGA_WRITEABLE) == 0)
3745 return;
3746 vm_page_lock_queues();
3747 sched_pin();
3748 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
3749 pmap = PV_PMAP(pv);
3750 PMAP_LOCK(pmap);
3751 pte = pmap_pte_quick(pmap, pv->pv_va);
3752 retry:
3753 oldpte = *pte;
3754 if ((oldpte & PG_RW) != 0) {
3755 vm_paddr_t newpte = oldpte & ~(PG_RW | PG_M);
3756
3757 /*
3758 * Regardless of whether a pte is 32 or 64 bits
3759 * in size, PG_RW and PG_M are among the least
3760 * significant 32 bits.
3761 */
3762 PT_SET_VA_MA(pte, newpte, TRUE);
3763 if (*pte != newpte)
3764 goto retry;
3765
3766 if ((oldpte & PG_M) != 0)
3767 vm_page_dirty(m);
3768 pmap_invalidate_page(pmap, pv->pv_va);
3769 }
3770 PMAP_UNLOCK(pmap);
3771 }
3772 vm_page_aflag_clear(m, PGA_WRITEABLE);
3773 PT_UPDATES_FLUSH();
3774 if (*PMAP1)
3775 PT_SET_MA(PADDR1, 0);
3776 sched_unpin();
3777 vm_page_unlock_queues();
3778 }
3779
3780 /*
3781 * pmap_ts_referenced:
3782 *
3783 * Return a count of reference bits for a page, clearing those bits.
3784 * It is not necessary for every reference bit to be cleared, but it
3785 * is necessary that 0 only be returned when there are truly no
3786 * reference bits set.
3787 *
3788 * XXX: The exact number of bits to check and clear is a matter that
3789 * should be tested and standardized at some point in the future for
3790 * optimal aging of shared pages.
3791 */
3792 int
3793 pmap_ts_referenced(vm_page_t m)
3794 {
3795 pv_entry_t pv, pvf, pvn;
3796 pmap_t pmap;
3797 pt_entry_t *pte;
3798 int rtval = 0;
3799
3800 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3801 ("pmap_ts_referenced: page %p is not managed", m));
3802 vm_page_lock_queues();
3803 sched_pin();
3804 if ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3805 pvf = pv;
3806 do {
3807 pvn = TAILQ_NEXT(pv, pv_list);
3808 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
3809 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
3810 pmap = PV_PMAP(pv);
3811 PMAP_LOCK(pmap);
3812 pte = pmap_pte_quick(pmap, pv->pv_va);
3813 if ((*pte & PG_A) != 0) {
3814 PT_SET_VA_MA(pte, *pte & ~PG_A, FALSE);
3815 pmap_invalidate_page(pmap, pv->pv_va);
3816 rtval++;
3817 if (rtval > 4)
3818 pvn = NULL;
3819 }
3820 PMAP_UNLOCK(pmap);
3821 } while ((pv = pvn) != NULL && pv != pvf);
3822 }
3823 PT_UPDATES_FLUSH();
3824 if (*PMAP1)
3825 PT_SET_MA(PADDR1, 0);
3826
3827 sched_unpin();
3828 vm_page_unlock_queues();
3829 return (rtval);
3830 }
3831
3832 /*
3833 * Clear the modify bits on the specified physical page.
3834 */
3835 void
3836 pmap_clear_modify(vm_page_t m)
3837 {
3838 pv_entry_t pv;
3839 pmap_t pmap;
3840 pt_entry_t *pte;
3841
3842 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3843 ("pmap_clear_modify: page %p is not managed", m));
3844 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
3845 KASSERT((m->oflags & VPO_BUSY) == 0,
3846 ("pmap_clear_modify: page %p is busy", m));
3847
3848 /*
3849 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
3850 * If the object containing the page is locked and the page is not
3851 * VPO_BUSY, then PGA_WRITEABLE cannot be concurrently set.
3852 */
3853 if ((m->aflags & PGA_WRITEABLE) == 0)
3854 return;
3855 vm_page_lock_queues();
3856 sched_pin();
3857 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
3858 pmap = PV_PMAP(pv);
3859 PMAP_LOCK(pmap);
3860 pte = pmap_pte_quick(pmap, pv->pv_va);
3861 if ((*pte & PG_M) != 0) {
3862 /*
3863 * Regardless of whether a pte is 32 or 64 bits
3864 * in size, PG_M is among the least significant
3865 * 32 bits.
3866 */
3867 PT_SET_VA_MA(pte, *pte & ~PG_M, FALSE);
3868 pmap_invalidate_page(pmap, pv->pv_va);
3869 }
3870 PMAP_UNLOCK(pmap);
3871 }
3872 sched_unpin();
3873 vm_page_unlock_queues();
3874 }
3875
3876 /*
3877 * pmap_clear_reference:
3878 *
3879 * Clear the reference bit on the specified physical page.
3880 */
3881 void
3882 pmap_clear_reference(vm_page_t m)
3883 {
3884 pv_entry_t pv;
3885 pmap_t pmap;
3886 pt_entry_t *pte;
3887
3888 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3889 ("pmap_clear_reference: page %p is not managed", m));
3890 vm_page_lock_queues();
3891 sched_pin();
3892 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
3893 pmap = PV_PMAP(pv);
3894 PMAP_LOCK(pmap);
3895 pte = pmap_pte_quick(pmap, pv->pv_va);
3896 if ((*pte & PG_A) != 0) {
3897 /*
3898 * Regardless of whether a pte is 32 or 64 bits
3899 * in size, PG_A is among the least significant
3900 * 32 bits.
3901 */
3902 PT_SET_VA_MA(pte, *pte & ~PG_A, FALSE);
3903 pmap_invalidate_page(pmap, pv->pv_va);
3904 }
3905 PMAP_UNLOCK(pmap);
3906 }
3907 sched_unpin();
3908 vm_page_unlock_queues();
3909 }
3910
3911 /*
3912 * Miscellaneous support routines follow
3913 */
3914
3915 /*
3916 * Map a set of physical memory pages into the kernel virtual
3917 * address space. Return a pointer to where it is mapped. This
3918 * routine is intended to be used for mapping device memory,
3919 * NOT real memory.
3920 */
3921 void *
3922 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
3923 {
3924 vm_offset_t va, offset;
3925 vm_size_t tmpsize;
3926
3927 offset = pa & PAGE_MASK;
3928 size = roundup(offset + size, PAGE_SIZE);
3929 pa = pa & PG_FRAME;
3930
3931 if (pa < KERNLOAD && pa + size <= KERNLOAD)
3932 va = KERNBASE + pa;
3933 else
3934 va = kmem_alloc_nofault(kernel_map, size);
3935 if (!va)
3936 panic("pmap_mapdev: Couldn't alloc kernel virtual memory");
3937
3938 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
3939 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
3940 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
3941 pmap_invalidate_cache_range(va, va + size);
3942 return ((void *)(va + offset));
3943 }
3944
3945 void *
3946 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
3947 {
3948
3949 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
3950 }
3951
3952 void *
3953 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
3954 {
3955
3956 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
3957 }
3958
3959 void
3960 pmap_unmapdev(vm_offset_t va, vm_size_t size)
3961 {
3962 vm_offset_t base, offset, tmpva;
3963
3964 if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD)
3965 return;
3966 base = trunc_page(va);
3967 offset = va & PAGE_MASK;
3968 size = roundup(offset + size, PAGE_SIZE);
3969 critical_enter();
3970 for (tmpva = base; tmpva < (base + size); tmpva += PAGE_SIZE)
3971 pmap_kremove(tmpva);
3972 pmap_invalidate_range(kernel_pmap, va, tmpva);
3973 critical_exit();
3974 kmem_free(kernel_map, base, size);
3975 }
3976
3977 /*
3978 * Sets the memory attribute for the specified page.
3979 */
3980 void
3981 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
3982 {
3983 struct sysmaps *sysmaps;
3984 vm_offset_t sva, eva;
3985
3986 m->md.pat_mode = ma;
3987 if ((m->flags & PG_FICTITIOUS) != 0)
3988 return;
3989
3990 /*
3991 * If "m" is a normal page, flush it from the cache.
3992 * See pmap_invalidate_cache_range().
3993 *
3994 * First, try to find an existing mapping of the page by sf
3995 * buffer. sf_buf_invalidate_cache() modifies mapping and
3996 * flushes the cache.
3997 */
3998 if (sf_buf_invalidate_cache(m))
3999 return;
4000
4001 /*
4002 * If page is not mapped by sf buffer, but CPU does not
4003 * support self snoop, map the page transient and do
4004 * invalidation. In the worst case, whole cache is flushed by
4005 * pmap_invalidate_cache_range().
4006 */
4007 if ((cpu_feature & (CPUID_SS|CPUID_CLFSH)) == CPUID_CLFSH) {
4008 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4009 mtx_lock(&sysmaps->lock);
4010 if (*sysmaps->CMAP2)
4011 panic("pmap_page_set_memattr: CMAP2 busy");
4012 sched_pin();
4013 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW |
4014 VM_PAGE_TO_MACH(m) | PG_A | PG_M |
4015 pmap_cache_bits(m->md.pat_mode, 0));
4016 invlcaddr(sysmaps->CADDR2);
4017 sva = (vm_offset_t)sysmaps->CADDR2;
4018 eva = sva + PAGE_SIZE;
4019 } else
4020 sva = eva = 0; /* gcc */
4021 pmap_invalidate_cache_range(sva, eva);
4022 if (sva != 0) {
4023 PT_SET_MA(sysmaps->CADDR2, 0);
4024 sched_unpin();
4025 mtx_unlock(&sysmaps->lock);
4026 }
4027 }
4028
4029 int
4030 pmap_change_attr(va, size, mode)
4031 vm_offset_t va;
4032 vm_size_t size;
4033 int mode;
4034 {
4035 vm_offset_t base, offset, tmpva;
4036 pt_entry_t *pte;
4037 u_int opte, npte;
4038 pd_entry_t *pde;
4039 boolean_t changed;
4040
4041 base = trunc_page(va);
4042 offset = va & PAGE_MASK;
4043 size = roundup(offset + size, PAGE_SIZE);
4044
4045 /* Only supported on kernel virtual addresses. */
4046 if (base <= VM_MAXUSER_ADDRESS)
4047 return (EINVAL);
4048
4049 /* 4MB pages and pages that aren't mapped aren't supported. */
4050 for (tmpva = base; tmpva < (base + size); tmpva += PAGE_SIZE) {
4051 pde = pmap_pde(kernel_pmap, tmpva);
4052 if (*pde & PG_PS)
4053 return (EINVAL);
4054 if ((*pde & PG_V) == 0)
4055 return (EINVAL);
4056 pte = vtopte(va);
4057 if ((*pte & PG_V) == 0)
4058 return (EINVAL);
4059 }
4060
4061 changed = FALSE;
4062
4063 /*
4064 * Ok, all the pages exist and are 4k, so run through them updating
4065 * their cache mode.
4066 */
4067 for (tmpva = base; size > 0; ) {
4068 pte = vtopte(tmpva);
4069
4070 /*
4071 * The cache mode bits are all in the low 32-bits of the
4072 * PTE, so we can just spin on updating the low 32-bits.
4073 */
4074 do {
4075 opte = *(u_int *)pte;
4076 npte = opte & ~(PG_PTE_PAT | PG_NC_PCD | PG_NC_PWT);
4077 npte |= pmap_cache_bits(mode, 0);
4078 PT_SET_VA_MA(pte, npte, TRUE);
4079 } while (npte != opte && (*pte != npte));
4080 if (npte != opte)
4081 changed = TRUE;
4082 tmpva += PAGE_SIZE;
4083 size -= PAGE_SIZE;
4084 }
4085
4086 /*
4087 * Flush CPU caches to make sure any data isn't cached that shouldn't
4088 * be, etc.
4089 */
4090 if (changed) {
4091 pmap_invalidate_range(kernel_pmap, base, tmpva);
4092 pmap_invalidate_cache_range(base, tmpva);
4093 }
4094 return (0);
4095 }
4096
4097 /*
4098 * perform the pmap work for mincore
4099 */
4100 int
4101 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
4102 {
4103 pt_entry_t *ptep, pte;
4104 vm_paddr_t pa;
4105 int val;
4106
4107 PMAP_LOCK(pmap);
4108 retry:
4109 ptep = pmap_pte(pmap, addr);
4110 pte = (ptep != NULL) ? PT_GET(ptep) : 0;
4111 pmap_pte_release(ptep);
4112 val = 0;
4113 if ((pte & PG_V) != 0) {
4114 val |= MINCORE_INCORE;
4115 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4116 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
4117 if ((pte & PG_A) != 0)
4118 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
4119 }
4120 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
4121 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
4122 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
4123 pa = pte & PG_FRAME;
4124 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
4125 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
4126 goto retry;
4127 } else
4128 PA_UNLOCK_COND(*locked_pa);
4129 PMAP_UNLOCK(pmap);
4130 return (val);
4131 }
4132
4133 void
4134 pmap_activate(struct thread *td)
4135 {
4136 pmap_t pmap, oldpmap;
4137 u_int cpuid;
4138 u_int32_t cr3;
4139
4140 critical_enter();
4141 pmap = vmspace_pmap(td->td_proc->p_vmspace);
4142 oldpmap = PCPU_GET(curpmap);
4143 cpuid = PCPU_GET(cpuid);
4144 #if defined(SMP)
4145 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
4146 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
4147 #else
4148 CPU_CLR(cpuid, &oldpmap->pm_active);
4149 CPU_SET(cpuid, &pmap->pm_active);
4150 #endif
4151 #ifdef PAE
4152 cr3 = vtophys(pmap->pm_pdpt);
4153 #else
4154 cr3 = vtophys(pmap->pm_pdir);
4155 #endif
4156 /*
4157 * pmap_activate is for the current thread on the current cpu
4158 */
4159 td->td_pcb->pcb_cr3 = cr3;
4160 PT_UPDATES_FLUSH();
4161 load_cr3(cr3);
4162 PCPU_SET(curpmap, pmap);
4163 critical_exit();
4164 }
4165
4166 void
4167 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
4168 {
4169 }
4170
4171 /*
4172 * Increase the starting virtual address of the given mapping if a
4173 * different alignment might result in more superpage mappings.
4174 */
4175 void
4176 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
4177 vm_offset_t *addr, vm_size_t size)
4178 {
4179 vm_offset_t superpage_offset;
4180
4181 if (size < NBPDR)
4182 return;
4183 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
4184 offset += ptoa(object->pg_color);
4185 superpage_offset = offset & PDRMASK;
4186 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
4187 (*addr & PDRMASK) == superpage_offset)
4188 return;
4189 if ((*addr & PDRMASK) < superpage_offset)
4190 *addr = (*addr & ~PDRMASK) + superpage_offset;
4191 else
4192 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
4193 }
4194
4195 void
4196 pmap_suspend()
4197 {
4198 pmap_t pmap;
4199 int i, pdir, offset;
4200 vm_paddr_t pdirma;
4201 mmu_update_t mu[4];
4202
4203 /*
4204 * We need to remove the recursive mapping structure from all
4205 * our pmaps so that Xen doesn't get confused when it restores
4206 * the page tables. The recursive map lives at page directory
4207 * index PTDPTDI. We assume that the suspend code has stopped
4208 * the other vcpus (if any).
4209 */
4210 LIST_FOREACH(pmap, &allpmaps, pm_list) {
4211 for (i = 0; i < 4; i++) {
4212 /*
4213 * Figure out which page directory (L2) page
4214 * contains this bit of the recursive map and
4215 * the offset within that page of the map
4216 * entry
4217 */
4218 pdir = (PTDPTDI + i) / NPDEPG;
4219 offset = (PTDPTDI + i) % NPDEPG;
4220 pdirma = pmap->pm_pdpt[pdir] & PG_FRAME;
4221 mu[i].ptr = pdirma + offset * sizeof(pd_entry_t);
4222 mu[i].val = 0;
4223 }
4224 HYPERVISOR_mmu_update(mu, 4, NULL, DOMID_SELF);
4225 }
4226 }
4227
4228 void
4229 pmap_resume()
4230 {
4231 pmap_t pmap;
4232 int i, pdir, offset;
4233 vm_paddr_t pdirma;
4234 mmu_update_t mu[4];
4235
4236 /*
4237 * Restore the recursive map that we removed on suspend.
4238 */
4239 LIST_FOREACH(pmap, &allpmaps, pm_list) {
4240 for (i = 0; i < 4; i++) {
4241 /*
4242 * Figure out which page directory (L2) page
4243 * contains this bit of the recursive map and
4244 * the offset within that page of the map
4245 * entry
4246 */
4247 pdir = (PTDPTDI + i) / NPDEPG;
4248 offset = (PTDPTDI + i) % NPDEPG;
4249 pdirma = pmap->pm_pdpt[pdir] & PG_FRAME;
4250 mu[i].ptr = pdirma + offset * sizeof(pd_entry_t);
4251 mu[i].val = (pmap->pm_pdpt[i] & PG_FRAME) | PG_V;
4252 }
4253 HYPERVISOR_mmu_update(mu, 4, NULL, DOMID_SELF);
4254 }
4255 }
4256
4257 #if defined(PMAP_DEBUG)
4258 pmap_pid_dump(int pid)
4259 {
4260 pmap_t pmap;
4261 struct proc *p;
4262 int npte = 0;
4263 int index;
4264
4265 sx_slock(&allproc_lock);
4266 FOREACH_PROC_IN_SYSTEM(p) {
4267 if (p->p_pid != pid)
4268 continue;
4269
4270 if (p->p_vmspace) {
4271 int i,j;
4272 index = 0;
4273 pmap = vmspace_pmap(p->p_vmspace);
4274 for (i = 0; i < NPDEPTD; i++) {
4275 pd_entry_t *pde;
4276 pt_entry_t *pte;
4277 vm_offset_t base = i << PDRSHIFT;
4278
4279 pde = &pmap->pm_pdir[i];
4280 if (pde && pmap_pde_v(pde)) {
4281 for (j = 0; j < NPTEPG; j++) {
4282 vm_offset_t va = base + (j << PAGE_SHIFT);
4283 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) {
4284 if (index) {
4285 index = 0;
4286 printf("\n");
4287 }
4288 sx_sunlock(&allproc_lock);
4289 return npte;
4290 }
4291 pte = pmap_pte(pmap, va);
4292 if (pte && pmap_pte_v(pte)) {
4293 pt_entry_t pa;
4294 vm_page_t m;
4295 pa = PT_GET(pte);
4296 m = PHYS_TO_VM_PAGE(pa & PG_FRAME);
4297 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x",
4298 va, pa, m->hold_count, m->wire_count, m->flags);
4299 npte++;
4300 index++;
4301 if (index >= 2) {
4302 index = 0;
4303 printf("\n");
4304 } else {
4305 printf(" ");
4306 }
4307 }
4308 }
4309 }
4310 }
4311 }
4312 }
4313 sx_sunlock(&allproc_lock);
4314 return npte;
4315 }
4316 #endif
4317
4318 #if defined(DEBUG)
4319
4320 static void pads(pmap_t pm);
4321 void pmap_pvdump(vm_paddr_t pa);
4322
4323 /* print address space of pmap*/
4324 static void
4325 pads(pmap_t pm)
4326 {
4327 int i, j;
4328 vm_paddr_t va;
4329 pt_entry_t *ptep;
4330
4331 if (pm == kernel_pmap)
4332 return;
4333 for (i = 0; i < NPDEPTD; i++)
4334 if (pm->pm_pdir[i])
4335 for (j = 0; j < NPTEPG; j++) {
4336 va = (i << PDRSHIFT) + (j << PAGE_SHIFT);
4337 if (pm == kernel_pmap && va < KERNBASE)
4338 continue;
4339 if (pm != kernel_pmap && va > UPT_MAX_ADDRESS)
4340 continue;
4341 ptep = pmap_pte(pm, va);
4342 if (pmap_pte_v(ptep))
4343 printf("%x:%x ", va, *ptep);
4344 };
4345
4346 }
4347
4348 void
4349 pmap_pvdump(vm_paddr_t pa)
4350 {
4351 pv_entry_t pv;
4352 pmap_t pmap;
4353 vm_page_t m;
4354
4355 printf("pa %x", pa);
4356 m = PHYS_TO_VM_PAGE(pa);
4357 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
4358 pmap = PV_PMAP(pv);
4359 printf(" -> pmap %p, va %x", (void *)pmap, pv->pv_va);
4360 pads(pmap);
4361 }
4362 printf(" ");
4363 }
4364 #endif
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