FreeBSD/Linux Kernel Cross Reference
sys/i386at/blitreg.h
1 /*
2 * Mach Operating System
3 * Copyright (c) 1991,1990,1989 Carnegie Mellon University
4 * All Rights Reserved.
5 *
6 * Permission to use, copy, modify and distribute this software and its
7 * documentation is hereby granted, provided that both the copyright
8 * notice and this permission notice appear in all copies of the
9 * software, derivative works or modified versions, and any portions
10 * thereof, and that both notices appear in supporting documentation.
11 *
12 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
13 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
14 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
15 *
16 * Carnegie Mellon requests users of this software to return to
17 *
18 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
19 * School of Computer Science
20 * Carnegie Mellon University
21 * Pittsburgh PA 15213-3890
22 *
23 * any improvements or extensions that they make and grant Carnegie Mellon
24 * the rights to redistribute these changes.
25 */
26 /*
27 * HISTORY
28 * $Log: blitreg.h,v $
29 * Revision 2.5 91/05/14 16:20:18 mrt
30 * Correcting copyright
31 *
32 * Revision 2.4 91/02/05 17:16:11 mrt
33 * Changed to new Mach copyright
34 * [91/02/01 17:41:52 mrt]
35 *
36 * Revision 2.3 90/11/26 14:49:03 rvb
37 * jsb bet me to XMK34, sigh ...
38 * [90/11/26 rvb]
39 * Synched 2.5 & 3.0 at I386q (r1.4.1.4) & XMK35 (r2.3)
40 * [90/11/15 rvb]
41 *
42 * Revision 1.4.1.3 90/06/07 08:05:29 rvb
43 * Fix to prevent obnoxious flickering. [kupfer]
44 *
45 * Revision 2.2 90/05/03 15:40:55 dbg
46 * First checkin.
47 *
48 * Revision 1.4.1.2 90/02/28 15:49:01 rvb
49 * Fix numerous typo's in Olivetti disclaimer.
50 * [90/02/28 rvb]
51 *
52 * Revision 1.4.1.1 90/01/08 13:32:18 rvb
53 * Add Olivetti copyright.
54 * [90/01/08 rvb]
55 *
56 * Revision 1.4 89/03/09 20:04:56 rpd
57 * More cleanup.
58 *
59 * Revision 1.3 89/02/26 12:41:24 gm0w
60 * Changes for cleanup.
61 *
62 */
63
64 /* **********************************************************************
65 File: blitreg.h
66 Description: Bell Tech Blit card hardware description
67
68 $ Header: $
69
70 Copyright Ing. C. Olivetti & C. S.p.A. 1988, 1989.
71 All rights reserved.
72 ********************************************************************** */
73 /*
74 Copyright 1988, 1989 by Olivetti Advanced Technology Center, Inc.,
75 Cupertino, California.
76
77 All Rights Reserved
78
79 Permission to use, copy, modify, and distribute this software and
80 its documentation for any purpose and without fee is hereby
81 granted, provided that the above copyright notice appears in all
82 copies and that both the copyright notice and this permission notice
83 appear in supporting documentation, and that the name of Olivetti
84 not be used in advertising or publicity pertaining to distribution
85 of the software without specific, written prior permission.
86
87 OLIVETTI DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE
88 INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS,
89 IN NO EVENT SHALL OLIVETTI BE LIABLE FOR ANY SPECIAL, INDIRECT, OR
90 CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
91 LOSS OF USE, DATA OR PROFITS, WHETHER IN ACTION OF CONTRACT,
92 NEGLIGENCE, OR OTHER TORTIOUS ACTION, ARISING OUR OF OR IN CONNECTION
93 WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
94 */
95
96 /*
97 * Some code taken from Bob Glossman's 1987 "minimal Blit Express
98 * driver", copyright unknown. Probably copyright Intel, too.
99 */
100
101
102 #ifndef blitreg_DEFINED
103 #define blitreg_DEFINED
104
105
106 /*
107 * Registers accessible through AT I/O space. These addresses can be
108 * changed by changing bits 4-8 of the Blit's DIP switch.
109 */
110
111 #define BLIT_CONFIG_ADDR 0x304
112 #define BLIT_DIAG_ADDR 0x306
113
114 #if defined(sun386) || defined(i386)
115
116
117 /*
118 * Layout of Blit control register.
119 */
120
121 union blit_config_reg {
122 struct config_bits {
123 unsigned dos_segment : 4;
124 unsigned reset : 1;
125 unsigned mode : 1;
126 #define BLIT_UNIX_MODE 1
127 #define BLIT_DOS_MODE 0
128 unsigned invisible : 1;
129 #define BLIT_INVISIBLE 1
130 #define BLIT_VISIBLE 0
131 unsigned unused : 1;
132 } reg;
133 u_char byte;
134 };
135
136
137 /*
138 * Blit Diag register.
139 * The UNIX base address is currently hardwired to BLIT_BASE_ADDR.
140 */
141
142 #define BLIT_BASE_ADDR 0xd80000 /* base of blit memory (phys addr) */
143
144 union blit_diag_reg {
145 struct diag_bits {
146 unsigned unix_base_addr : 5; /* phys addr (ignored) */
147 unsigned led0 : 1;
148 unsigned led1 : 1;
149 unsigned led2 : 1;
150 #define BLIT_LED_ON 1
151 #define BLIT_LED_OFF 0
152 } reg;
153 u_char byte;
154 };
155
156 #endif /* sun386 || i386 */
157
158
159 /*
160 * Graphics memory, 786 registers, static RAM, and EPROM, all
161 * accessible through mapped memory.
162 */
163
164 #define BLIT_MONOWIDTH 1664
165 #define BLIT_MONOHEIGHT 1200
166 #define BLIT_MONOFBSIZE ((BLIT_MONOWIDTH*BLIT_MONOHEIGHT)/8)
167 /* byte size of monochrome fb */
168
169 #define BLIT_MEMSIZE 0x100000 /* num bytes mapped graphics memory */
170
171 #define BLIT_REGSIZE 128 /* bytes taken by 786 registers */
172 #define BLIT_REGPAD (0x10000 - BLIT_REGSIZE)
173 /* padding between reg's and SRAM */
174
175 #define BLIT_SRAMSIZE 0x4000 /* num bytes mapped for SRAM */
176 #define BLIT_SRAMPAD (0x10000 - BLIT_SRAMSIZE)
177 /* padding between SRAM and EPROM */
178
179 #define BLIT_EPROMSIZE 0x20000 /* num bytes mapped for EPROM */
180
181
182 /*
183 * Layout of the Blit's mapped memory. The physical address is (or
184 * will be, eventually) determined by the Diag register (above).
185 */
186
187 struct blitdev {
188 u_char graphmem[BLIT_MEMSIZE];
189 u_char reg786[BLIT_REGSIZE];
190 u_char pad1[BLIT_REGPAD];
191 u_char sram[BLIT_SRAMSIZE];
192 u_char pad2[BLIT_SRAMPAD];
193 u_char eprom[BLIT_EPROMSIZE];
194 };
195
196 #define BLIT_MAPPED_SIZE sizeof(struct blitdev)
197
198
199 /*
200 * Offsets for 786 registers (i.e., indices into reg786[]).
201 */
202
203 #define INTER_RELOC 0x00 /* Internal Relocation Register */
204 #define BIU_CONTROL 0x04 /* BIU Control Register */
205 #define DRAM_REFRESH 0x06 /* DRAM Refresh control register */
206 #define DRAM_CONTROL 0x08 /* DRAM control register */
207 #define DP_PRIORITY 0x0A /* DP priority register */
208 #define GP_PRIORITY 0x0C /* GP priority register*/
209 #define EXT_PRIORITY 0x0E /* External Priority Register*/
210 #define GP_OPCODE_REG 0x20 /* GP opcode register */
211 #define GP_PARM1_REG 0x22 /* GP Parameter 1 Register */
212 #define GP_PARM2_REG 0x24 /* GP Parameter 2 Register*/
213 #define GP_STAT_REG 0x26 /* GP Status Register*/
214 #define DP_OPCODE_REG 0x40 /* DP opcode register */
215 #define DP_PARM1_REG 0x42 /* DP Parameter 1 Register*/
216 #define DP_PARM2_REG 0x44 /* DP Parameter 2 Register*/
217 #define DP_PARM3_REG 0x46 /* DP Parameter 3 Register*/
218 #define DP_STAT_REG 0x48 /* DP Status Register*/
219 #define DEF_VIDEO_REG 0x4A /* DP Default Video Register*/
220
221
222 /*
223 * 786 BIU Control Register values.
224 */
225
226 #define BIU_WP1 0x02 /* Write Protect One; 1 = on */
227 #define BIU_16BIT 0x10 /* access 786 registers as words; 0 = bytes */
228
229
230 /*
231 * 786 DRAM/VRAM Control Register values.
232 */
233
234 /* RW bits */
235 #define MEMROWS1 0
236 #define MEMROWS2 0x20
237 #define MEMROWS3 0x40
238 #define MEMROWS4 0x60
239
240 /* DC bits */
241 #define PG_NONINTERLV 0
242 #define FASTPG_NONINTERLV 0x10
243 #define PG_INTERLV 0x08
244 #define FASTPG_INTERLV 0x18
245
246 /* HT bits */
247 #define HEIGHT_8K 0
248 #define HEIGHT_16K 0x1
249 #define HEIGHT_32K 0x2
250 #define HEIGHT_64K 0x3
251 #define HEIGHT_128K 0x4
252 #define HEIGHT_256K 0x5
253 #define HEIGHT_512K 0x6
254 #define HEIGHT_1M 0x7
255
256
257 /*
258 * 786 Graphics Processor opcodes.
259 */
260
261 #define GECL 0x001 /* end of command list */
262 #define OP_LINK 0x200 /* LINK - "link next cmd" */
263
264
265 /*
266 * 786 Display Processor opcodes.
267 */
268
269 #define DECL 1 /* end of list */
270 #define DP_LOADALL 0x500
271
272
273 /*
274 * Macros for accessing 786 registers (see BIU_16BIT) and EPROM.
275 */
276
277 #define WRITEREG8(base,offset,val) \
278 (base)->reg786[(offset)] = (val) & 0xff, \
279 (base)->reg786[(offset)+1] = ((val) & 0xff00) >> 8
280
281 #define WRITEREG16(base,offset,val) \
282 (*((u_short *)((base)->reg786+(offset)))) = (val)
283
284 #define READREG(base,offset) \
285 (*((u_short *)(((base)->reg786+(offset)))))
286
287 #define WRITEROM(romp,offset,val) \
288 (*((u_short *)((romp)+(offset)))) = (val)
289
290 #define READROM(romp,offset) \
291 (*((u_short *)(((romp)+(offset)))))
292
293
294 /*
295 * Layout of Display Processor Control Block Registers. This block is
296 * allocated somewhere in the Blit's graphics memory, and a pointer to
297 * it is passed to the Display Processor.
298 *
299 * NOTE: The 786 only sees the memory mapped by the Blit. Thus all
300 * addresses passed to the 786 are relative to the start of the Blit's
301 * mapped memory.
302 */
303
304 typedef int addr786_t; /* 0 = start of Blit mapped memory */
305
306 typedef struct {
307 u_short vidstat; /* video status */
308 u_short intrmask; /* interrupt mask */
309 u_short trip_point;
310 u_short frame_intr; /* frame interrupt */
311 u_short reserved1;
312 u_short crtmode; /* CRT controller mode */
313 u_short hsyncstop; /* monitor parameters */
314 u_short hfldstart;
315 u_short hfldstop;
316 u_short linelength;
317 u_short vsyncstop;
318 u_short vfldstart;
319 u_short vfldstop;
320 u_short vframelen;
321 u_short descl; /* descriptor pointer low part */
322 u_short desch; /* descriptor pointer high part */
323 u_short reserved2;
324 u_short xyzoom;
325 u_short fldcolor;
326 u_short bordercolor;
327 u_short bpp_pad1;
328 u_short bpp_pad2;
329 u_short bpp_pad4;
330 u_short csrmode; /* & CsrPad */
331 u_short cursorx; /* cursor x location */
332 u_short cursory; /* cursor y location */
333 u_short cursorpat[16]; /* cursor pattern */
334 } DPCONTROLBLK;
335
336
337 /*
338 * Values for 786 Display Processor Control Block Registers.
339 */
340
341 /* video status */
342 #define DP_DSP_ON 1 /* display on */
343 #define DP_CSR_ON 2 /* cursor on */
344
345 /* CRT controller modes */
346 #define CRTM_NONINTER 0 /* non-interlaced */
347 #define CRTM_INTERLCD 0x40 /* interlaced */
348 #define CRTM_INTERSYN 0x60 /* interlaced - sync */
349 #define CRTM_WIN_STAT_ENABLE 0x10 /* window status enable */
350 #define CRTM_SYNC_SLAVE_MODE 0x08 /* on = operate as slave */
351 #define CRTM_BLANK_SLAVE_MODE 0x04 /* on = Blank is input */
352 #define CRTM_NORMAL_SPEED 0x00
353 #define CRTM_HIGH_SPEED 0x01
354 #define CRTM_VRYHIGH_SPEED 0x02
355 #define CRTM_SUPHIGH_SPEED 0x03
356
357 /* cursor style */
358 #define DP_CURSOR_16X16 0x8000 /* off = 8x8 */
359 #define DP_CURSOR_CROSSHAIR 0x4000 /* off = block cursor */
360 #define DP_CURSOR_TRANSPRNT 0x2000 /* off = cursor is opaque */
361
362
363 /*
364 * Types for dealing with 786 Display Processor.
365 */
366
367 typedef struct {
368 u_short lines; /* (lines in strip) - 1 */
369 u_short linkl; /* link to next strip low part */
370 u_short linkh; /* link to next strip high part */
371 u_short tiles; /* C bit, (tiles in strip) - 1 */
372 } STRIPHEADER;
373
374 /*
375 * If the C bit is turned on, the display processor "automatically
376 * displays the background color" for areas not defined by the strips.
377 * See section 3.1.3.2 of the '786 User's Manual.
378 */
379 #define DP_C_BIT 0x8000
380
381 typedef struct {
382 u_short bitmapw; /* width of bitmap */
383 u_short meml; /* btb mem address low part */
384 u_short memh; /* btb mem address high part */
385 u_short bppss; /* bpp, start and stop fields */
386 u_short fetchcnt; /* fetch count */
387 u_short flags; /* various flags */
388 } TILEDESC;
389
390
391 /*
392 * Macros for encoding addresses for strip headers & tile descriptors.
393 * addr786 is relative to the start of the Blit's mapped memory.
394 */
395
396 #define DP_ADDRLOW(addr786) (((int)(addr786)) & 0xffff)
397 #define DP_ADDRHIGH(addr786) ((((int)(addr786)) >> 16) & 0x3f)
398
399
400 /*
401 * Byte offsets to useful data words within the EPROM.
402 */
403
404 #define EP_MAGIC1 0
405 #define EP_MAGIC1_VAL 0x7856
406 #define EP_MAGIC2 2
407 #define EP_MAGIC2_VAL 0x6587
408 #define EP_DPSTART 4 /* start of DP ctl block */
409 /* (0 = start of EPROM) */
410 #define EP_DPLEN 6 /* byte length of DP control block */
411
412 #define EP_FONTSTART 8 /* start of font */
413 /* (0 = start of EPROM) */
414 #define EP_FONTLEN 10 /* byte length of font */
415 #define EP_CHARWIDTH 12 /* bit width of each char in font */
416 #define EP_CHARHEIGHT 14
417 #define EP_NUMCHARS 16 /* num chars in font */
418
419 /* where in the bitmap the 25x80 console screen starts */
420 #define EP_XSTART 18
421 #define EP_YSTART 20
422
423 #define EP_SCREENWIDTH 22 /* pixels per scan line */
424 #define EP_SCREENHEIGHT 24 /* number of scan lines */
425
426 #define EP_FIXUP_X 26 /* magic numbers for displaying */
427 #define EP_FIXUP_Y 28 /* hardware cursor */
428
429 #define EP_BPP 30 /* bits per pixel */
430
431
432 /*
433 * Miscellaneous.
434 */
435
436 #define BLIT_BLACK_BIT 0 /* try saying that 3 times fast */
437 #define BLIT_WHITE_BIT 1
438 #define BLIT_BLACK_BYTE 0
439 #define BLIT_WHITE_BYTE 0xff
440
441
442 #endif /* blitreg_DEFINED */
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