FreeBSD/Linux Kernel Cross Reference
sys/i386at/if_3c501.h
1 /*
2 * Mach Operating System
3 * Copyright (c) 1991,1990,1989 Carnegie Mellon University
4 * All Rights Reserved.
5 *
6 * Permission to use, copy, modify and distribute this software and its
7 * documentation is hereby granted, provided that both the copyright
8 * notice and this permission notice appear in all copies of the
9 * software, derivative works or modified versions, and any portions
10 * thereof, and that both notices appear in supporting documentation.
11 *
12 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
13 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
14 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
15 *
16 * Carnegie Mellon requests users of this software to return to
17 *
18 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
19 * School of Computer Science
20 * Carnegie Mellon University
21 * Pittsburgh PA 15213-3890
22 *
23 * any improvements or extensions that they make and grant Carnegie Mellon
24 * the rights to redistribute these changes.
25 */
26 /*
27 * HISTORY
28 * $Log: if_3c501.h,v $
29 * Revision 2.6 93/11/17 16:46:27 dbg
30 * Removed local declaration of HZ.
31 * [93/01/29 dbg]
32 *
33 * Revision 2.5 91/05/14 16:24:31 mrt
34 * Correcting copyright
35 *
36 * Revision 2.4 91/02/05 17:17:41 mrt
37 * Added OSF permision and disclaimer clause per instructions
38 * of Philippe Bernadat.
39 * [91/02/04 mrt]
40 * Changed to new Mach copyright
41 * [91/02/01 17:43:49 mrt]
42 *
43 * Revision 2.3 90/11/26 14:49:56 rvb
44 * jsb beat me to XMK34, sigh ...
45 * [90/11/26 rvb]
46 * Synched 2.5 & 3.0 at I386q (r2.1.1.2) & XMK35 (r2.3)
47 * [90/11/15 rvb]
48 *
49 * Revision 2.2 90/05/03 15:44:05 dbg
50 * First checkin.
51 *
52 * Revision 2.1.1.1 90/03/16 18:15:44 rvb
53 * installed
54 * [90/03/13 rvb]
55 *
56 * Created by Philippe Bernadat
57 */
58 /*
59 * File: if_3c501.h
60 * Author: Philippe Bernadat
61 * Date: 1989
62 * Copyright (c) 1989 OSF Research Institute
63 *
64 * 3COM Etherlink 3C501 Mach Ethernet drvier
65 */
66 /*
67 Copyright 1990 by Open Software Foundation,
68 Cambridge, MA.
69
70 All Rights Reserved
71
72 Permission to use, copy, modify, and distribute this software and
73 its documentation for any purpose and without fee is hereby granted,
74 provided that the above copyright notice appears in all copies and
75 that both the copyright notice and this permission notice appear in
76 supporting documentation, and that the name of OSF or Open Software
77 Foundation not be used in advertising or publicity pertaining to
78 distribution of the software without specific, written prior
79 permission.
80
81 OSF DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE
82 INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS,
83 IN NO EVENT SHALL OSF BE LIABLE FOR ANY SPECIAL, INDIRECT, OR
84 CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
85 LOSS OF USE, DATA OR PROFITS, WHETHER IN ACTION OF CONTRACT,
86 NEGLIGENCE, OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION
87 WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
88 */
89
90 /* The various IE command registers */
91
92 #define EDLC_ADDR(base) (base) /* EDLC station address, 6 bytes*/
93 #define EDLC_RCV(base) ((base)+0x6) /* EDLC receive cmd. & stat. */
94 #define EDLC_XMT(base) ((base)+0x7) /* EDLC transmit cmd. & stat. */
95 #define IE_GP(base) ((base)+0x8) /* General Purpose pointer */
96 #define IE_RP(base) ((base)+0xa) /* Receive buffer pointer */
97 #define IE_SAPROM(base) ((base)+0xc) /* station addr prom window */
98 #define IE_CSR(base) ((base)+0xe) /* IE command and status */
99 #define IE_BFR(base) ((base)+0xf) /* 1 byte window on packet buffer*/
100
101 /* CSR Status Register (read)
102 *
103 * _______________________________________________________________________
104 * | | | | | | | | |
105 * | XMTBSY | RIDE | DMA | EDMA | BUFCTL | | RCVBSY |
106 * |________|________|________|________|________|________|________|________|
107 *
108 */
109
110 /* CSR Command Register (write)
111 *
112 * _______________________________________________________________________
113 * | | | | | | | | |
114 * | RESET | RIDE | DMA | | BUFCTL | | IRE |
115 * |________|________|________|________|________|________|________|________|
116 *
117 */
118
119 #define IE_XMTBSY 0x80 /* Transmitter busy (ro) */
120 #define IE_RESET 0x80 /* reset the controller (wo) */
121 #define IE_RIDE 0x40 /* request interrupt/DMA enable (rw) */
122 #define IE_DMA 0x20 /* DMA request (rw) */
123 #define IE_EDMA 0x10 /* DMA done (ro) */
124 #define IE_BUFCTL 0x0c /* mask for buffer control field (rw) */
125 #define IE_RCVBSY 0x01 /* receive in progress (ro) */
126 #define IE_IRE 0x01 /* Interrupt request enable */
127
128 /* BUFCTL values */
129
130 #define IE_LOOP 0x0c /* 2 bit field in bits 2,3, loopback */
131 #define IE_RCVEDLC 0x08 /* gives buffer to receiver */
132 #define IE_XMTEDLC 0x04 /* gives buffer to transmit */
133 #define IE_SYSBFR 0x00 /* gives buffer to processor */
134
135 /* XMTCSR Transmit Status Register (read)
136 *
137 * _______________________________________________________________________
138 * | | | | | | | | |
139 * | | | | | IDLE | 16 | JAM | UNDER |
140 * |________|________|________|________|________|________|________|________|
141 *
142 */
143
144 /* XMTCSR Transmit Command Register (write) enables interrupts when written
145 *
146 * _______________________________________________________________________
147 * | | | | | | | | |
148 * | | | | | | | | |
149 * |________|________|________|________|________|________|________|________|
150 *
151 */
152
153 #define EDLC_IDLE 0x08 /* transmit idle */
154 #define EDLC_16 0x04 /* packet experienced 16 collisions */
155 #define EDLC_JAM 0x02 /* packet experienced a collision */
156 #define EDLC_UNDER 0x01 /* data underflow */
157
158 /* RCVCSR Receive Status Register (read)
159 *
160 * _______________________________________________________________________
161 * | | | | | | | | |
162 * | STALE | | GOOD | ANY | SHORT | DRIBBLE| FCS | OVER |
163 * |________|________|________|________|________|________|________|________|
164 *
165 */
166
167 /* RCVCSR Receive Command Register (write) enables interrupt when written
168 *
169 * _______________________________________________________________________
170 * | | | | | | | | |
171 * | ADDR MATCH MODE | GOOD | ANY | SHORT | DRIBBLE| FCS | OVER |
172 * |________|________|________|________|________|________|________|________|
173 *
174 */
175
176 #define EDLC_STALE 0x80 /* receive CSR status previously read */
177 #define EDLC_GOOD 0x20 /* well formed packets only */
178 #define EDLC_ANY 0x10 /* any packet, even those with errors */
179 #define EDLC_SHORT 0x08 /* short frame */
180 #define EDLC_DRIBBLE 0x04 /* dribble error */
181 #define EDLC_FCS 0x02 /* CRC error */
182 #define EDLC_OVER 0x01 /* data overflow */
183
184 /* Address Match Mode */
185
186 #define EDLC_NONE 0x00 /* match mode in bits 5-6, write only */
187 #define EDLC_ALL 0x40 /* promiscuous receive, write only */
188 #define EDLC_BROAD 0x80 /* station address plus broadcast */
189 #define EDLC_MULTI 0xc0 /* station address plus multicast */
190
191 /* Packet Buffer size */
192
193 #define BFRSIZ 2048
194
195 #define NAT3C501 1
196 #define ETHER_ADD_SIZE 6 /* size of a MAC address */
197
198 #ifndef TRUE
199 #define TRUE 1
200 #endif TRUE
201
202 #define DSF_LOCK 1
203 #define DSF_RUNNING 2
204
205 #define MOD_ENAL 1
206 #define MOD_PROM 2
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