if_3c503.h

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    1 /* 
    2  * Mach Operating System
    3  * Copyright (c) 1991 Carnegie-Mellon University
    4  * All Rights Reserved.
    5  * 
    6  * Permission to use, copy, modify and distribute this software and its
    7  * documentation is hereby granted, provided that both the copyright
    8  * notice and this permission notice appear in all copies of the
    9  * software, derivative works or modified versions, and any portions
   10  * thereof, and that both notices appear in supporting documentation.
   11  * 
   12  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
   13  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
   14  * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
   15  * 
   16  * Carnegie Mellon requests users of this software to return to
   17  * 
   18  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
   19  *  School of Computer Science
   20  *  Carnegie Mellon University
   21  *  Pittsburgh PA 15213-3890
   22  * 
   23  * any improvements or extensions that they make and grant Carnegie Mellon
   24  * the rights to redistribute these changes.
   25  */
   26 /* 
   27  * HISTORY
   28  * $Log:        if_3c503.h,v $
   29  * Revision 2.4  91/05/14  16:24:41  mrt
   30  *      Correcting copyright
   31  * 
   32  * Revision 2.3  91/02/05  17:17:45  mrt
   33  *      Changed to new Mach copyright
   34  *      [91/02/01  17:43:55  mrt]
   35  * 
   36  * Revision 2.2  91/01/08  17:32:58  rpd
   37  *      Etherlink II device specific info.
   38  *      [91/01/04  12:19:07  rvb]
   39  * 
   40  */
   41 
   42 /* Gate Array Description */
   43 
   44 #define PSTR    0x400
   45 #define PSPR    0x401
   46 #define DQTR    0x402
   47 #define BCFR    0x403
   48 #define PCFR    0x404
   49 #define GACFR   0x405
   50 #define CTLR    0x406
   51 #define STREG   0x407
   52 #define IDCFR   0x408
   53 #define DAMSB   0x409
   54 #define DALSB   0x40A
   55 #define VPTR2   0x40B
   56 #define VPTR1   0x40C
   57 #define VPTR0   0x40D
   58 #define RFMSB   0x40E
   59 #define RFLSB   0x40F
   60 
   61                 /*      PSTR    400     */
   62 /* int */
   63                 /*      PSPR    401     */
   64 /* int */
   65                 /*      DQTR    402     */
   66 /* dma only */
   67                 /*      BCFR    403     */
   68 #define B7_300  0x300
   69 #define B6_310  0x310
   70 #define B5_330  0x330
   71 #define B4_350  0x350
   72 #define B3_250  0x250
   73 #define B2_280  0x280
   74 #define B1_2A0  0x2a0
   75 #define B0_2E0  0x2e0
   76                 /*      PCFR    404     */
   77 
   78                 /*      GACFR   405     */
   79 #define GACFR_NIM       0x80
   80 #define GACFR_TCM       0x40
   81 #define GACFR_OWS       0x20
   82 #define GACFR_TEST      0x10
   83 #define GACFR_RSEL      0x08
   84 #define GACFR_MBS2      0x04
   85 #define GACFR_MBS1      0x02
   86 #define GACFR_MBS0      0x01
   87         /*
   88          * This definition is only for the std 8k window on an 8k board.
   89          * It is incorrect for a 32K board.  But they do not exists yet
   90          * and I don't even know how to tell I am looking at one.
   91          */
   92 #define GACFR_8K        (GACFR_RSEL|0x1)
   93                 /*      CTLR    406     */
   94 #define CTLR_START      0x80
   95 #define CTLR_DDIR       0x40
   96 #define CTLR_DBSEL      0x20
   97 #define CTLR_SHARE      0x10
   98 #define CTLR_EAHI       0x08
   99 #define CTLR_EALO       0x04
  100 #define CTLR_XSEL       0x02
  101 #define CTLR_RST        0x01
  102 #define CTLR_EA         0x0c
  103 #define CTLR_STA_ADDR   0x04
  104 #define CTLR_THIN       0x02
  105 #define CTLR_THICK      0x00
  106                 /*      STREG   407     */
  107 /* DMA */
  108                 /*      IDCFR   408     */
  109 #define IDCFR_IRQ5      0x80
  110 #define IDCFR_IRQ4      0x40
  111 #define IDCFR_IRQ3      0x20
  112 #define IDCFR_IRQ2      0x10
  113 #define IDCFR_DRQ3      0x04
  114 #define IDCFR_DRQ2      0x02
  115 #define IDCFR_DRQ1      0x01
  116                 /*      DAMSB   409     */
  117 /* int & dma */
  118                 /*      DALSB   40A     */
  119 /* int & dma */
  120                 /*      VPTR2   40B     */
  121                 /*      VPTR1   40C     */
  122                 /*      VPTR0   40D     */
  123                 /*      RFMSB   40E     */
  124 /* what's a register file */
  125                 /*      RFLSB   40F     */

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FreeBSD/Linux Kernel Cross Reference sys/i386at/if_3c503.h

FreeBSD/Linux Kernel Cross Reference
sys/i386at/if_3c503.h