1 /*
2 * Mach Operating System
3 * Copyright (c) 1991,1990,1989 Carnegie Mellon University
4 * All Rights Reserved.
5 *
6 * Permission to use, copy, modify and distribute this software and its
7 * documentation is hereby granted, provided that both the copyright
8 * notice and this permission notice appear in all copies of the
9 * software, derivative works or modified versions, and any portions
10 * thereof, and that both notices appear in supporting documentation.
11 *
12 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
13 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
14 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
15 *
16 * Carnegie Mellon requests users of this software to return to
17 *
18 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
19 * School of Computer Science
20 * Carnegie Mellon University
21 * Pittsburgh PA 15213-3890
22 *
23 * any improvements or extensions that they make and grant Carnegie Mellon
24 * the rights to redistribute these changes.
25 */
26 /*
27 * HISTORY
28 * $Log: if_ns8390.h,v $
29 * Revision 2.6 91/05/14 16:25:20 mrt
30 * Correcting copyright
31 *
32 * Revision 2.5 91/02/05 17:18:10 mrt
33 * Changed to new Mach copyright
34 * [91/02/01 17:44:20 mrt]
35 *
36 * Revision 2.4 91/01/08 17:33:15 rpd
37 * Restrict to defines for the 8390 only.
38 * [91/01/04 12:25:57 rvb]
39 *
40 * Revision 2.1.1.3 90/11/27 13:43:32 rvb
41 * Synched 2.5 & 3.0 at I386q (r2.1.1.3) & XMK35 (r2.3)
42 * [90/11/15 rvb]
43 *
44 * Revision 2.2 90/10/01 14:23:27 jeffreyh
45 * Revision 2.1 90/09/26 10:33:25 jeffreyh
46 * Created.
47 * [90/09/26 10:34:39 jeffreyh]
48 *
49 * Revision 2.1.1.2 90/07/27 11:25:45 rvb
50 * Add boardID definitions. [rweiss]
51 *
52 * Revision 2.1.1.1 90/07/10 11:45:00 rvb
53 * Added to system.
54 * [90/07/06 rvb]
55 *
56 */
57 /*
58 * Western Digital Mach Ethernet driver
59 * Copyright (c) 1990 OSF Research Institute
60 */
61 /*
62 Copyright 1990 by Open Software Foundation,
63 Cambridge, MA.
64
65 All Rights Reserved
66
67 Permission to use, copy, modify, and distribute this software and
68 its documentation for any purpose and without fee is hereby granted,
69 provided that the above copyright notice appears in all copies and
70 that both the copyright notice and this permission notice appear in
71 supporting documentation, and that the name of OSF or Open Software
72 Foundation not be used in advertising or publicity pertaining to
73 distribution of the software without specific, written prior
74 permission.
75
76 OSF DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE
77 INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS,
78 IN NO EVENT SHALL OSF BE LIABLE FOR ANY SPECIAL, INDIRECT, OR
79 CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
80 LOSS OF USE, DATA OR PROFITS, WHETHER IN ACTION OF CONTRACT,
81 NEGLIGENCE, OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION
82 WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
83 */
84
85 /********************************************/
86 /* Defines for the NIC 8390 Lan Controller */
87 /********************************************/
88
89
90 /*-- page 0, rd --*/
91 #define CR 0x00 /* Command Register */
92 #define CLDA0 0x01 /* Current Local DMA Address 0 */
93 #define CLDA1 0x02 /* Current Local DMA Address 1 */
94 #define BNRY 0x03 /* Boundary Pointer */
95 #define TSR 0x04 /* Transmit Status Register */
96 #define NCR 0x05 /* Number of Collisions Register */
97 #define FIFO 0x06 /* FIFO */
98 #define ISR 0x07 /* Interrupt Status Register */
99 #define CRDA0 0x08 /* Current Remote DMA Address 0 */
100 #define CRDA1 0x09 /* Current Remote DMA Address 1 */
101 /* 0x0A is reserved */
102 /* 0x0B is reserved */
103 #define RSR 0x0C /* Receive Status Register */
104 #define CNTR0 0x0D /* Frame Alignment Errors */
105 #define CNTR1 0x0E /* CRC Errors */
106 #define CNTR2 0x0F /* Missed Packet Errors */
107
108 /*-- page 0, wr --*/
109 /* CR 0x00 Command Register */
110 #define PSTART 0x01 /* Page Start Register */
111 #define PSTOP 0x02 /* Page Stop Register */
112 #define BNDY 0x03 /* Boundary Pointer */
113 #define TPSR 0x04 /* Transmit Page Start Register */
114 #define TBCR0 0x05 /* Transmit Byte Count Register 0*/
115 #define TBCR1 0x06 /* Transmit Byte Count Register 1*/
116 /* ISR 0x07 Interrupt Status Register */
117 #define RSAR0 0x08 /* Remote Start Address Register 0 */
118 #define RSAR1 0x09 /* Remote Start Address Register 1 */
119 #define RBCR0 0x0A /* Remote Byte Count Register 0 */
120 #define RBCR1 0x0B /* Remote Byte Count Register 1 */
121 #define RCR 0x0C /* Receive Configuration Register */
122 #define TCR 0x0D /* Transmit Configuration Register */
123 #define DCR 0x0E /* Data Configuration Register */
124 #define IMR 0x0F /* Interrupt Mask Register */
125
126 /*-- page 1, rd and wr */
127 /* CR 0x00 Control Register */
128 #define PAR0 0x01 /* Physical Address Register 0 */
129 #define PAR1 0x02 /* 1 */
130 #define PAR2 0x03 /* 2 */
131 #define PAR3 0x04 /* 3 */
132 #define PAR4 0x05 /* 4 */
133 #define PAR5 0x06 /* 5 */
134 #define CURR 0x07 /* Current Page Register */
135 #define MAR0 0x08 /* Multicast Address Register 0 */
136 #define MAR1 0x09 /* 1 */
137 #define MAR2 0x0A /* 2 */
138 #define MAR3 0x0B /* 3 */
139 #define MAR4 0x0C /* 4 */
140 #define MAR5 0x0D /* 5 */
141 #define MAR6 0x0E /* 6 */
142 #define MAR7 0x0F /* 7 */
143
144 /*-- page 2, rd --*/
145
146 /*-- page 2, wr --*/
147
148 /*-- Command Register CR description */
149 #define STP 0x01 /* stop; software reset */
150 #define STA 0x02 /* start */
151 #define TXP 0x04 /* transmit packet */
152 #define RD0 0x08
153 #define RD1 0x10
154 #define RD2 0x20
155 #define RRD 0x08 /* remote DMA command - remote read */
156
157 #define RWR 0x10 /* remote DMA command - remote write */
158 #define SPK 0x18 /* remote DMA command - send packet */
159 #define ABR 0x20 /* remote DMA command - abrt/cmplt remote DMA */
160
161 #define PS0 0x00 /* register page select - 0 */
162 #define PS1 0x40 /* register page select - 1 */
163 #define PS2 0x80 /* register page select - 2 */
164
165 #define PS0_STA 0x22 /* page select 0 with start bit maintained */
166 #define PS1_STA 0x62 /* page select 1 with start bit maintained */
167 #define PS2_STA 0x0A2 /* page select 2 with start bit maintained */
168
169 /*-- Interrupt Status Register ISR description */
170 #define PRX 0x01 /* packet received no error */
171 #define PTX 0x02 /* packet transmitted no error */
172 #define RXE 0x04 /* receive error */
173 #define TXE 0x08 /* transmit error */
174 #define OVW 0x10 /* overwrite warning */
175 #define CNT 0x20 /* counter overflow */
176 #define RDC 0x40 /* remote DMA complete */
177 #define RST 0x80 /* reset status */
178
179 /*-- Interrupt Mask Register IMR description */
180 #define PRXE 0x01 /* packet received interrupt enable */
181 #define PTXE 0x02 /* packet transmitted interrupt enable */
182 #define RXEE 0x04 /* receive error interrupt enable */
183 #define TXEE 0x08 /* transmit error interrupt enable */
184 #define OVWE 0x10 /* overwrite warning interrupt enable */
185 #define CNTE 0x20 /* counter overflow interrupt enable */
186 #define RDCE 0x40 /* DMA complete interrupt enable */
187
188 /*-- Data Configuration Register DCR description */
189 #define WTS 0x01 /* word transfer select */
190 #define BOS 0x02 /* byte order select */
191 #define LAS 0x04 /* long address select */
192 #define BMS 0x08 /* burst DMA select */
193 #define AINIT 0x10 /* autoinitialize remote */
194
195 #define FTB2 0x00 /* receive FIFO threshold select - 2 bytes */
196 #define FTB4 0x20 /* receive FIFO threshold select - 4 bytes */
197 #define FTB8 0x40 /* receive FIFO threshold select - 8 bytes */
198 #define FTB12 0x60 /* receive FIFO threshold select - 12 bytes */
199
200 /*-- Transmit Configuration Register TCR description */
201 #define MCRC 0x01 /* manual crc generation */
202 #define LB1 0x02 /* mode 1; internal loopback LPBK=0 */
203 #define LB2 0x04 /* mode 2; internal loopback LPBK=1 */
204 #define LB3 0x06 /* mode 3; internal loopback LPBK=0 */
205
206 #define ATD 0x08 /* auto transmit disable */
207 #define OFST 0x10 /* collision offset enable */
208
209 /*-- Transmit Status Register TSR description --*/
210 #define XMT 0x01 /* packet transmitted without error */
211 #define COL 0x04 /* transmit collided */
212 #define ABT 0x08 /* transmit aborted */
213 #define CRS 0x10 /* carrier sense lost - xmit not aborted */
214 #define FU 0x20 /* FIFO underrun */
215 #define CDH 0x40 /* CD heartbeat */
216 #define OWC 0x80 /* out of window collision - xmit not aborted */
217
218 /*-- Receive Configuration Register RCR description --*/
219 #define SEP 0x01 /* save error packets */
220 #define AR 0x02 /* accept runt packet */
221 #define AB 0x04 /* accept broadcast */
222 #define AM 0x08 /* accept multicast */
223 #define PRO 0x10 /* promiscuous physical */
224 #define MON 0x20 /* monitor mode */
225
226 /*--Receive Status Register RSR description --*/
227 #define RCV 0x01 /* packet received intact */
228 #define CRC 0x02 /* CRC error */
229 #define FAE 0x04 /* frame alignment error */
230 #define FO 0x08 /* FIFO overrun */
231 #define MPA 0x10 /* missed packet */
232 #define PHY 0x20 /* physical/multicast address */
233 #define DIS 0x40 /* receiver disable */
234 #define DFR 0x80 /* deferring */
Cache object: e0a863eb8c708c67b3e7a029acbdbf93
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