The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/i386ipsc/bia.h

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    1 /* 
    2  * Mach Operating System
    3  * Copyright (c) 1991 Carnegie Mellon University
    4  * All Rights Reserved.
    5  * 
    6  * Permission to use, copy, modify and distribute this software and its
    7  * documentation is hereby granted, provided that both the copyright
    8  * notice and this permission notice appear in all copies of the
    9  * software, derivative works or modified versions, and any portions
   10  * thereof, and that both notices appear in supporting documentation.
   11  * 
   12  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
   13  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
   14  * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
   15  * 
   16  * Carnegie Mellon requests users of this software to return to
   17  * 
   18  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
   19  *  School of Computer Science
   20  *  Carnegie Mellon University
   21  *  Pittsburgh PA 15213-3890
   22  * 
   23  * any improvements or extensions that they make and grant Carnegie Mellon
   24  * the rights to redistribute these changes.
   25  */
   26 /*
   27  * Copyright 1988, 1989, 1990, 1991 by Intel Corporation,
   28  * Santa Clara, California.
   29  * 
   30  *                          All Rights Reserved
   31  * 
   32  * Permission to use, copy, modify, and distribute this software and its
   33  * documentation for any purpose and without fee is hereby granted,
   34  * provided that the above copyright notice appears in all copies and that
   35  * both the copyright notice and this permission notice appear in
   36  * supporting documentation, and that the name of Intel not be used in
   37  * advertising or publicity pertaining to distribution of the software
   38  * without specific, written prior permission.
   39  * 
   40  * INTEL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING
   41  * ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT
   42  * SHALL INTEL BE LIABLE FOR ANY SPECIAL, INDIRECT, OR CONSEQUENTIAL
   43  * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
   44  * PROFITS, WHETHER IN ACTION OF CONTRACT, NEGLIGENCE, OR OTHER TORTIOUS
   45  * ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF
   46  * THIS SOFTWARE.
   47  */
   48 /*
   49  * HISTORY
   50  * $Log:        bia.h,v $
   51  * Revision 2.4  91/12/10  16:29:49  jsb
   52  *      Fixes from Intel
   53  *      [91/12/10  15:32:07  jsb]
   54  * 
   55  * Revision 2.3  91/06/18  20:50:02  jsb
   56  *      New copyright from Intel.
   57  *      [91/06/18  20:05:41  jsb]
   58  * 
   59  * Revision 2.2  90/12/04  14:47:00  jsb
   60  *      First checkin.
   61  *      [90/12/04  10:55:26  jsb]
   62  * 
   63  */
   64 /*
   65  *      File:   bia.h
   66  *      Author: Joseph S. Barrera III
   67  *
   68  *      Copyright (c) 1990 Joseph S. Barrera III
   69  *
   70  *      Declarations for VME BIA (Bus Interface Adaptor).
   71  *      Derived from NX's bia.h.
   72  */
   73 
   74 typedef unsigned char   byte;
   75 typedef unsigned short  word16;
   76 typedef unsigned long   word32;
   77 
   78 #define MAX_BIA         3       /* Maximum number of BIA boards in system */
   79 #define DEF_BIA         0       /* Default BIA board number */
   80 #define NUMPATS         7       /* Number of static patterns */
   81 
   82 #define BIA_VME         0x00800000      /* Base address of BIA VME space */
   83 #define BIA_REG         0x00c00000      /* Base address of BIA registers */
   84 #define BIA_OFFSET      0x01000000      /* Address offset for each BIA board */
   85 #define BIA_VMESIZE     BIA_REG-BIA_VME         /* VME address space per BIA */
   86 #define BIA_REGSIZE     BIA_OFFSET-BIA_REG      /* Reg address space per BIA */
   87 
   88 struct bia {
   89         byte    bia_vme[BIA_VMESIZE];
   90         union {
   91                 struct {
   92                         word32  r_isr;
   93 #define                         r_clr_int       r_isr
   94                         word32  r_swap_reg;
   95 #define                         r_control       r_swap_reg
   96                         word32  r_imr;
   97                         word32  r_pag_mod;
   98                 } r;
   99                 byte    b_reg[BIA_REGSIZE];
  100         } bia_u;
  101 };
  102 
  103 #define bia_isr         bia_u.r.r_isr
  104 #define bia_clr_int     bia_u.r.r_clr_int
  105 #define bia_swap_reg    bia_u.r.r_swap_reg
  106 #define bia_control     bia_u.r.r_control
  107 #define bia_imr         bia_u.r.r_imr
  108 #define bia_pag_mod     bia_u.r.r_pag_mod
  109 #define bia_reg         bia_u.b_reg
  110 
  111 #define PAG_MASK        0xffc00000              /* Mask for page bits */
  112 #define MOD_MASK        0x0000003f              /* Mask for modifier bits */
  113 #define P_M_MASK        (PAG_MASK|MOD_MASK)     /* Mask for PAG_MOD register */
  114 
  115 
  116 /* These defines are offsets from a BIA base address for each register */
  117 #define ISR             0x0000          /* Read interrupt status reg */
  118 #define CLR_INT         0x0000          /* Clear interrupt status reg */
  119 #define SWAP_REG        0x0004          /* Read byte swapping test reg */
  120 #define CONTROL         0x0004          /* Write BIA control reg */
  121 #define IMR             0x0008          /* Read/write interrupt mask reg */
  122 #define PAG_MOD         0x000c          /* Read/write VME page address reg */
  123 
  124 
  125 /* These defines are for the interrupt status register bits */
  126 #define ISR_IRQ1_       0x0001          /* Low true, VME IRQ1 */
  127 #define ISR_IRQ2_       0x0002          /* Low true, VME IRQ2 */
  128 #define ISR_IRQ3_       0x0004          /* Low true, VME IRQ3 */
  129 #define ISR_IRQ4_       0x0008          /* Low true, VME IRQ4 */
  130 #define ISR_IRQ5_       0x0010          /* Low true, VME IRQ5 */
  131 #define ISR_IRQ6_       0x0020          /* Low true, VME IRQ6 */
  132 #define ISR_IRQ7_       0x0040          /* Low true, VME IRQ7 */
  133 #define ISR_U1          0x0080          /* Unused bit 1 */
  134 #define ISR_DTACK_      0x0100          /* Low true, slave read/wrote VME */
  135 #define ISR_SYSFAIL_    0x0200          /* Low true, VME SYSFAIL line */
  136 #define ISR_BIA_TO_     0x0400          /* Low true, BIA bus time out error */
  137 #define ISR_BERR_       0x0800          /* Low true, VME bus error */
  138 #define ISR_S1          0x1000          /* Spare bit 1 */
  139 #define ISR_U2          0x2000          /* Unused bit 2 */
  140 #define ISR_U3          0x4000          /* Unused bit 3 */
  141 #define ISR_U4          0x8000          /* Unused bit 4 */
  142 
  143 #define ISR_NONE        0xf7ff          /* Value indicating no ints pending */
  144 #define ISR_ALL_IRQ     0x007f          /* Mask value for IRQ levels only */
  145 
  146 
  147 /* These defines are for the BIA CONTROL register bits */
  148 #define LED_GRN         0x0001          /* Green LED */
  149 #define LED_RED         0x0002          /* Red LED */
  150 #define LED_YEL         0x0004          /* Yellow LED */
  151 #define SHFL0           0x0008          /* LSB of memory mode */
  152 #define CTRL_U1         0x0010          /* Unused bit 1 */
  153 #define CTRL_U2         0x0020          /* Unused bit 2 */
  154 #define CTRL_U3         0x0040          /* Unused bit 3 */
  155 #define CTRL_U4         0x0080          /* Unused bit 4 */
  156 #define SYSFAIL_        0x0100          /* Low true, asserts VME SYSFAIL line */
  157 #define RESET_          0x0200          /* Low true, asserts ?? */
  158 #define TRISTATE_       0x0400          /* Low true, VME address, data, ctrl high */
  159 #define SHFL1           0x0800          /* MSB of memory mode */
  160 #define TEST_NET        0x1000          /* Enables reading of test network latches */
  161 #define BLK_MODE        0x2000          /* Enables VME block mode transfers */
  162 #define VME_IACK        0x4000          /* Enables VME interrupt acknowledge cycle */
  163 #define INT_ENBL        0x8000          /* Enables interrupts through BIA to PBX node */
  164 
  165 /* Values for the Memory Access Modes */
  166 
  167 #define MODE_ARRAY      0               /* Array Compatibility */
  168 #define MODE_16_BIT     SHFL1           /* 16 bit access Mode */
  169 #define MODE_8_BIT      SHFL0           /* 8 bit access Mode */
  170 #define MODE_32_BIT     (SHFL0 | SHFL1) /* 32 bit access MOde */
  171 
  172 /* Value to reset entire BIA control register to */
  173 #define RESET_CTRL      (SYSFAIL_ | RESET_ | TRISTATE_)
  174 #define LED_ON_DELAY    1500L   /* LED on for 1.5 seconds */
  175 #define LED_OFF_DELAY   500L    /* LED off for .5 seconds */
  176 
  177 
  178 /* These defines are for the interrupt mask register bits */
  179 #define IMR_SYSFAIL     0x0001          /* Mask off VME SYSFAIL line */
  180 #define IMR_BIA_TO      0x0002          /* Mask off BIA bus time out error */
  181 #define IMR_BERR        0x0004          /* Mask off VME bus error */
  182 #define IMR_IRQ1        0x0008          /* Mask off VME IRQ1 */
  183 #define IMR_IRQ2        0x0010          /* Mask off VME IRQ2 */
  184 #define IMR_IRQ3        0x0020          /* Mask off VME IRQ3 */
  185 #define IMR_IRQ4        0x0040          /* Mask off VME IRQ4 */
  186 #define IMR_IRQ5        0x0080          /* Mask off VME IRQ5 */
  187 #define IMR_IRQ6        0x0100          /* Mask off VME IRQ6 */
  188 #define IMR_IRQ7        0x0200          /* Mask off VME IRQ7 */
  189 #define IMR_U1          0x0400          /* Unused bit 1 */
  190 #define IMR_U2          0x0800          /* Unused bit 2 */
  191 #define IMR_U3          0x1000          /* Unused bit 3 */
  192 #define IMR_U4          0x2000          /* Unused bit 4 */
  193 #define IMR_U5          0x4000          /* Unused bit 5 */
  194 #define IMR_U6          0x8000          /* Unused bit 6 */
  195 
  196 #define IMR_ALL_IRQ     0x03f8          /* All the IRQs */
  197 #define IMR_MASKALL     0xffff          /* Mask off all interrupts */
  198 #define IMR_NO_MASK     0               /* No masking of any interrupts */
  199 
  200 
  201 /* These defines are for the PAG_MOD register */
  202 #define STD_SUP_BLK     0x003f          /* A24 supervisory block transfer */
  203 #define STD_SUP_DATA    0x003d          /* A24 supervisory data access */
  204 #define STD_NO_P_BLK    0x003b          /* A24 non-privileged block transfer */
  205 #define STD_NO_P_DATA   0x0039          /* A24 non-privileged data access */
  206 #define SHORT_SUP       0x002d          /* A16 supervisory access */
  207 #define SHORT_NO_P      0x0029          /* A16 non-privileged access */
  208 #define EXT_SUP_BLK     0x000f          /* A32 supervisory block transfer */
  209 #define EXT_SUP_DATA    0x000d          /* A32 supervisory data access */
  210 #define EXT_NO_P_BLK    0x000b          /* A32 non-privileged block transfer */
  211 #define EXT_NO_P_DATA   0x0009          /* A32 non-privileged data access */
  212 
  213 /*\
  214 ***   PIC ports and values
  215 \*/
  216 
  217 #define SPIC_PORTB      0xC6
  218 #define NBCR_PORT       0x80
  219 #define NUSMINT         0x20
  220 #define LBXENBL         (NUSMINT | 0x8)
  221 #define LBXENBINT       0x10

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