The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/i386ipsc/dcm_route.s

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    1 /* 
    2  * Mach Operating System
    3  * Copyright (c) 1991 Carnegie Mellon University
    4  * All Rights Reserved.
    5  * 
    6  * Permission to use, copy, modify and distribute this software and its
    7  * documentation is hereby granted, provided that both the copyright
    8  * notice and this permission notice appear in all copies of the
    9  * software, derivative works or modified versions, and any portions
   10  * thereof, and that both notices appear in supporting documentation.
   11  * 
   12  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
   13  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
   14  * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
   15  * 
   16  * Carnegie Mellon requests users of this software to return to
   17  * 
   18  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
   19  *  School of Computer Science
   20  *  Carnegie Mellon University
   21  *  Pittsburgh PA 15213-3890
   22  * 
   23  * any improvements or extensions that they make and grant Carnegie Mellon
   24  * the rights to redistribute these changes.
   25  */
   26 /*
   27  * Copyright 1988, 1989, 1990, 1991 by Intel Corporation,
   28  * Santa Clara, California.
   29  * 
   30  *                          All Rights Reserved
   31  * 
   32  * Permission to use, copy, modify, and distribute this software and its
   33  * documentation for any purpose and without fee is hereby granted,
   34  * provided that the above copyright notice appears in all copies and that
   35  * both the copyright notice and this permission notice appear in
   36  * supporting documentation, and that the name of Intel not be used in
   37  * advertising or publicity pertaining to distribution of the software
   38  * without specific, written prior permission.
   39  * 
   40  * INTEL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING
   41  * ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT
   42  * SHALL INTEL BE LIABLE FOR ANY SPECIAL, INDIRECT, OR CONSEQUENTIAL
   43  * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
   44  * PROFITS, WHETHER IN ACTION OF CONTRACT, NEGLIGENCE, OR OTHER TORTIOUS
   45  * ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF
   46  * THIS SOFTWARE.
   47  */
   48 /*
   49  * HISTORY
   50  * $Log:        dcm_route.s,v $
   51  * Revision 2.5  91/08/03  18:18:04  jsb
   52  *      Removed dcm_send_k, dcm_send_a. Changed send_chan_* to dcm_send_chan_*.
   53  *      [91/07/24  23:18:30  jsb]
   54  * 
   55  *      Changed for rename of recv_chan to dcm_recv_chan.
   56  *      [91/07/17  23:26:00  jsb]
   57  * 
   58  *      Added dcm_send_a; added outb_dx, outw_dx, outb_i macros.
   59  *      [91/07/17  13:58:26  jsb]
   60  * 
   61  * Revision 2.4  91/06/18  20:50:18  jsb
   62  *      New copyright from Intel.
   63  *      [91/06/18  20:06:30  jsb]
   64  * 
   65  * Revision 2.3  91/06/06  17:04:36  jsb
   66  *      Support for new dcm code.
   67  *      [91/05/13  17:01:17  jsb]
   68  * 
   69  * Revision 2.2  90/12/04  14:47:11  jsb
   70  *      First checkin.
   71  *      [90/12/04  10:56:16  jsb]
   72  * 
   73  */ 
   74 
   75 #include <i386/asm.h>
   76 #include <i386ipsc/port.h>
   77 
   78 #define outb_dx .byte 0xee
   79 #define outw_dx .byte 0xef
   80 #define outb_i  .byte 0xe6,
   81 
   82 /*
   83  * dcm_send_1():
   84  * Start ADMA send with dcm_send_chan_1
   85  */
   86 ENTRY(dcm_send_1)
   87         mov     $CPR0L_PORT, %edx
   88         mov     $_dcm_send_chan_1 + 2, %eax
   89         outw_dx
   90         mov     $CPR0H_PORT, %edx
   91         shr     $16, %eax
   92         outw_dx
   93         mul     %eax
   94         mov     $GCR_PORT, %edx
   95         movb    $START_CHAN0, %al
   96         outb_dx
   97         ret
   98 
   99 /*
  100  * dcm_send_2():
  101  * Start ADMA send with dcm_send_chan_2
  102  */
  103 ENTRY(dcm_send_2)
  104         mov     $CPR0L_PORT, %edx
  105         mov     $_dcm_send_chan_2 + 2, %eax
  106         outw_dx
  107         mov     $CPR0H_PORT, %edx
  108         shr     $16, %eax
  109         outw_dx
  110         mul     %eax
  111         mov     $GCR_PORT, %edx
  112         movb    $START_CHAN0, %al
  113         outb_dx
  114         ret
  115 
  116 /*
  117  * dcm_recv():
  118  * Start ADMA recv with dcm_recv_chan
  119  */
  120 ENTRY(dcm_recv)
  121         mov     $CPR2L_PORT, %edx
  122         mov     $_dcm_recv_chan + 2, %eax
  123         outw_dx
  124  
  125         movb    $RLSRCV | NTRESET | NXRESET | NPROGRAM, %al
  126         outb_i  DCC_PORT
  127  
  128         mov     $CPR2H_PORT, %edx
  129         shr     $16, %eax
  130         outw_dx
  131  
  132         movb    $NTRESET | NXRESET | NPROGRAM, %al
  133         outb_i  DCC_PORT
  134  
  135         mov     $GCR_PORT, %edx
  136         movb    $START_CHAN2, %al
  137         outb_dx
  138         ret

Cache object: d308d1f0c70dfd48029220d15176c308


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