core_marvel.h

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    1 /*
    2  * Marvel systems use the IO7 I/O chip provides PCI/PCIX/AGP access
    3  *
    4  * This file is based on:
    5  *
    6  * Marvel / EV7 System Programmer's Manual
    7  * Revision 1.00
    8  * 14 May 2001
    9  */
   10 
   11 #ifndef __ALPHA_MARVEL__H__
   12 #define __ALPHA_MARVEL__H__
   13 
   14 #include <linux/types.h>
   15 #include <linux/pci.h>
   16 #include <linux/spinlock.h>
   17 
   18 #include <asm/compiler.h>
   19 
   20 #define MARVEL_MAX_PIDS          32 /* as long as we rely on 43-bit superpage */
   21 #define MARVEL_IRQ_VEC_PE_SHIFT (10)
   22 #define MARVEL_IRQ_VEC_IRQ_MASK ((1 << MARVEL_IRQ_VEC_PE_SHIFT) - 1)
   23 #define MARVEL_NR_IRQS          \
   24         (16 + (MARVEL_MAX_PIDS * (1 << MARVEL_IRQ_VEC_PE_SHIFT)))
   25 
   26 /*
   27  * EV7 RBOX Registers
   28  */
   29 typedef struct {
   30         volatile unsigned long csr __attribute__((aligned(16)));
   31 } ev7_csr;
   32 
   33 typedef struct {
   34         ev7_csr RBOX_CFG;               /* 0x0000 */
   35         ev7_csr RBOX_NSVC;
   36         ev7_csr RBOX_EWVC;
   37         ev7_csr RBOX_WHAMI;
   38         ev7_csr RBOX_TCTL;              /* 0x0040 */
   39         ev7_csr RBOX_INT;
   40         ev7_csr RBOX_IMASK;
   41         ev7_csr RBOX_IREQ;
   42         ev7_csr RBOX_INTQ;              /* 0x0080 */
   43         ev7_csr RBOX_INTA;
   44         ev7_csr RBOX_IT;
   45         ev7_csr RBOX_SCRATCH1;
   46         ev7_csr RBOX_SCRATCH2;          /* 0x00c0 */
   47         ev7_csr RBOX_L_ERR;
   48 } ev7_csrs;
   49 
   50 /*
   51  * EV7 CSR addressing macros
   52  */
   53 #define EV7_MASK40(addr)        ((addr) & ((1UL << 41) - 1))
   54 #define EV7_KERN_ADDR(addr)     ((void *)(IDENT_ADDR | EV7_MASK40(addr)))
   55 
   56 #define EV7_PE_MASK             0x1ffUL /* 9 bits ( 256 + mem/io ) */
   57 #define EV7_IPE(pe)             ((~((long)(pe)) & EV7_PE_MASK) << 35)
   58 
   59 #define EV7_CSR_PHYS(pe, off)   (EV7_IPE(pe) | (0x7FFCUL << 20) | (off))
   60 #define EV7_CSRS_PHYS(pe)       (EV7_CSR_PHYS(pe, 0UL))
   61 
   62 #define EV7_CSR_KERN(pe, off)   (EV7_KERN_ADDR(EV7_CSR_PHYS(pe, off)))
   63 #define EV7_CSRS_KERN(pe)       (EV7_KERN_ADDR(EV7_CSRS_PHYS(pe)))
   64 
   65 #define EV7_CSR_OFFSET(name)    ((unsigned long)&((ev7_csrs *)NULL)->name.csr)
   66 
   67 /*
   68  * IO7 registers
   69  */
   70 typedef struct {
   71         volatile unsigned long csr __attribute__((aligned(64)));
   72 } io7_csr;
   73 
   74 typedef struct {
   75         /* I/O Port Control Registers */
   76         io7_csr POx_CTRL;               /* 0x0000 */
   77         io7_csr POx_CACHE_CTL;
   78         io7_csr POx_TIMER;
   79         io7_csr POx_IO_ADR_EXT;
   80         io7_csr POx_MEM_ADR_EXT;        /* 0x0100 */
   81         io7_csr POx_XCAL_CTRL;
   82         io7_csr rsvd1[2];       /* ?? spec doesn't show 0x180 */
   83         io7_csr POx_DM_SOURCE;          /* ox0200 */
   84         io7_csr POx_DM_DEST;
   85         io7_csr POx_DM_SIZE;
   86         io7_csr POx_DM_STATE;
   87         io7_csr rsvd2[4];               /* 0x0300 */
   88 
   89         /* AGP Control Registers -- port 3 only */
   90         io7_csr AGP_CAP_ID;             /* 0x0400 */
   91         io7_csr AGP_STAT;
   92         io7_csr AGP_CMD;
   93         io7_csr rsvd3;
   94 
   95         /* I/O Port Monitor Registers */
   96         io7_csr POx_MONCTL;             /* 0x0500 */
   97         io7_csr POx_CTRA;
   98         io7_csr POx_CTRB;
   99         io7_csr POx_CTR56;
  100         io7_csr POx_SCRATCH;            /* 0x0600 */
  101         io7_csr POx_XTRA_A;
  102         io7_csr POx_XTRA_TS;
  103         io7_csr POx_XTRA_Z;
  104         io7_csr rsvd4;                  /* 0x0700 */
  105         io7_csr POx_THRESHA;
  106         io7_csr POx_THRESHB;
  107         io7_csr rsvd5[33];
  108 
  109         /* System Address Space Window Control Registers */
  110 
  111         io7_csr POx_WBASE[4];           /* 0x1000 */
  112         io7_csr POx_WMASK[4];
  113         io7_csr POx_TBASE[4];
  114         io7_csr POx_SG_TBIA;
  115         io7_csr POx_MSI_WBASE;
  116         io7_csr rsvd6[50];
  117 
  118         /* I/O Port Error Registers */
  119         io7_csr POx_ERR_SUM;
  120         io7_csr POx_FIRST_ERR;
  121         io7_csr POx_MSK_HEI;
  122         io7_csr POx_TLB_ERR;
  123         io7_csr POx_SPL_COMPLT;
  124         io7_csr POx_TRANS_SUM;
  125         io7_csr POx_FRC_PCI_ERR;
  126         io7_csr POx_MULT_ERR;
  127         io7_csr rsvd7[8];
  128 
  129         /* I/O Port End of Interrupt Registers */
  130         io7_csr EOI_DAT;
  131         io7_csr rsvd8[7];
  132         io7_csr POx_IACK_SPECIAL;
  133         io7_csr rsvd9[103];
  134 } io7_ioport_csrs;
  135 
  136 typedef struct {
  137         io7_csr IO_ASIC_REV;            /* 0x30.0000 */
  138         io7_csr IO_SYS_REV;
  139         io7_csr SER_CHAIN3;
  140         io7_csr PO7_RST1;
  141         io7_csr PO7_RST2;               /* 0x30.0100 */
  142         io7_csr POx_RST[4];
  143         io7_csr IO7_DWNH;
  144         io7_csr IO7_MAF;
  145         io7_csr IO7_MAF_TO;
  146         io7_csr IO7_ACC_CLUMP;          /* 0x30.0300 */
  147         io7_csr IO7_PMASK;
  148         io7_csr IO7_IOMASK;
  149         io7_csr IO7_UPH;
  150         io7_csr IO7_UPH_TO;             /* 0x30.0400 */
  151         io7_csr RBX_IREQ_OFF;
  152         io7_csr RBX_INTA_OFF;
  153         io7_csr INT_RTY;
  154         io7_csr PO7_MONCTL;             /* 0x30.0500 */
  155         io7_csr PO7_CTRA;
  156         io7_csr PO7_CTRB;
  157         io7_csr PO7_CTR56;
  158         io7_csr PO7_SCRATCH;            /* 0x30.0600 */
  159         io7_csr PO7_XTRA_A;
  160         io7_csr PO7_XTRA_TS;
  161         io7_csr PO7_XTRA_Z;
  162         io7_csr PO7_PMASK;              /* 0x30.0700 */
  163         io7_csr PO7_THRESHA;
  164         io7_csr PO7_THRESHB;
  165         io7_csr rsvd1[97];
  166         io7_csr PO7_ERROR_SUM;          /* 0x30.2000 */
  167         io7_csr PO7_BHOLE_MASK;
  168         io7_csr PO7_HEI_MSK;
  169         io7_csr PO7_CRD_MSK;
  170         io7_csr PO7_UNCRR_SYM;          /* 0x30.2100 */
  171         io7_csr PO7_CRRCT_SYM;
  172         io7_csr PO7_ERR_PKT[2];
  173         io7_csr PO7_UGBGE_SYM;          /* 0x30.2200 */
  174         io7_csr rsbv2[887];
  175         io7_csr PO7_LSI_CTL[128];       /* 0x31.0000 */
  176         io7_csr rsvd3[123];
  177         io7_csr HLT_CTL;                /* 0x31.3ec0 */
  178         io7_csr HPI_CTL;                /* 0x31.3f00 */
  179         io7_csr CRD_CTL;
  180         io7_csr STV_CTL;
  181         io7_csr HEI_CTL;
  182         io7_csr PO7_MSI_CTL[16];        /* 0x31.4000 */
  183         io7_csr rsvd4[240];
  184 
  185         /*
  186          * Interrupt Diagnostic / Test
  187          */
  188         struct {
  189                 io7_csr INT_PND;
  190                 io7_csr INT_CLR;
  191                 io7_csr INT_EOI;
  192                 io7_csr rsvd[29];
  193         } INT_DIAG[4];
  194         io7_csr rsvd5[125];             /* 0x31.a000 */
  195         io7_csr MISC_PND;               /* 0x31.b800 */
  196         io7_csr rsvd6[31];
  197         io7_csr MSI_PND[16];            /* 0x31.c000 */
  198         io7_csr rsvd7[16];
  199         io7_csr MSI_CLR[16];            /* 0x31.c800 */
  200 } io7_port7_csrs;
  201 
  202 /* 
  203  * IO7 DMA Window Base register (POx_WBASEx)
  204  */
  205 #define wbase_m_ena  0x1
  206 #define wbase_m_sg   0x2
  207 #define wbase_m_dac  0x4
  208 #define wbase_m_addr 0xFFF00000
  209 union IO7_POx_WBASE {
  210         struct {
  211                 unsigned ena : 1;       /* <0>                  */
  212                 unsigned sg : 1;        /* <1>                  */
  213                 unsigned dac : 1;       /* <2> -- window 3 only */
  214                 unsigned rsvd1 : 17; 
  215                 unsigned addr : 12;     /* <31:20>              */
  216                 unsigned rsvd2 : 32;
  217         } bits;
  218         unsigned as_long[2];
  219         unsigned as_quad;
  220 };
  221 
  222 /*
  223  * IO7 IID (Interrupt IDentifier) format
  224  *
  225  * For level-sensitive interrupts, int_num is encoded as:
  226  *
  227  *      bus/port        slot/device     INTx
  228  *      <7:5>           <4:2>           <1:0>
  229  */
  230 union IO7_IID {
  231         struct {
  232                 unsigned int_num : 9;           /* <8:0>        */
  233                 unsigned tpu_mask : 4;          /* <12:9> rsvd  */
  234                 unsigned msi : 1;               /* 13           */
  235                 unsigned ipe : 10;              /* <23:14>      */
  236                 unsigned long rsvd : 40;                
  237         } bits;
  238         unsigned int as_long[2];
  239         unsigned long as_quad;
  240 };
  241 
  242 /*
  243  * IO7 addressing macros
  244  */
  245 #define IO7_KERN_ADDR(addr)     (EV7_KERN_ADDR(addr))
  246 
  247 #define IO7_PORT_MASK           0x07UL  /* 3 bits of port          */
  248 
  249 #define IO7_IPE(pe)             (EV7_IPE(pe))
  250 #define IO7_IPORT(port)         ((~((long)(port)) & IO7_PORT_MASK) << 32)
  251 
  252 #define IO7_HOSE(pe, port)      (IO7_IPE(pe) | IO7_IPORT(port))
  253 
  254 #define IO7_MEM_PHYS(pe, port)  (IO7_HOSE(pe, port) | 0x00000000UL)
  255 #define IO7_CONF_PHYS(pe, port) (IO7_HOSE(pe, port) | 0xFE000000UL)
  256 #define IO7_IO_PHYS(pe, port)   (IO7_HOSE(pe, port) | 0xFF000000UL)
  257 #define IO7_CSR_PHYS(pe, port, off) \
  258                                 (IO7_HOSE(pe, port) | 0xFF800000UL | (off))
  259 #define IO7_CSRS_PHYS(pe, port) (IO7_CSR_PHYS(pe, port, 0UL))
  260 #define IO7_PORT7_CSRS_PHYS(pe) (IO7_CSR_PHYS(pe, 7, 0x300000UL))
  261 
  262 #define IO7_MEM_KERN(pe, port)      (IO7_KERN_ADDR(IO7_MEM_PHYS(pe, port)))
  263 #define IO7_CONF_KERN(pe, port)     (IO7_KERN_ADDR(IO7_CONF_PHYS(pe, port)))
  264 #define IO7_IO_KERN(pe, port)       (IO7_KERN_ADDR(IO7_IO_PHYS(pe, port)))
  265 #define IO7_CSR_KERN(pe, port, off) (IO7_KERN_ADDR(IO7_CSR_PHYS(pe,port,off)))
  266 #define IO7_CSRS_KERN(pe, port)     (IO7_KERN_ADDR(IO7_CSRS_PHYS(pe, port)))
  267 #define IO7_PORT7_CSRS_KERN(pe)     (IO7_KERN_ADDR(IO7_PORT7_CSRS_PHYS(pe)))
  268 
  269 #define IO7_PLL_RNGA(pll)       (((pll) >> 3) & 0x7)
  270 #define IO7_PLL_RNGB(pll)       (((pll) >> 6) & 0x7)
  271 
  272 #define IO7_MEM_SPACE           (2UL * 1024 * 1024 * 1024)      /* 2GB MEM */
  273 #define IO7_IO_SPACE            (8UL * 1024 * 1024)             /* 8MB I/O */
  274 
  275  
  276 /* 
  277  * Offset between ram physical addresses and pci64 DAC addresses
  278  */
  279 #define IO7_DAC_OFFSET          (1UL << 49)
  280 
  281 /*
  282  * This is needed to satisify the IO() macro used in initializing the machvec
  283  */
  284 #define MARVEL_IACK_SC                                                  \
  285         ((unsigned long)                                                \
  286          (&(((io7_ioport_csrs *)IO7_CSRS_KERN(0, 0))->POx_IACK_SPECIAL)))
  287 
  288 #ifdef __KERNEL__
  289 
  290 /*
  291  * IO7 structs
  292  */
  293 #define IO7_NUM_PORTS 4
  294 #define IO7_AGP_PORT  3
  295 
  296 struct io7_port {
  297         struct io7 *io7;
  298         struct pci_controller *hose;
  299 
  300         int enabled;
  301         unsigned int port;
  302         io7_ioport_csrs *csrs;
  303 
  304         unsigned long saved_wbase[4];
  305         unsigned long saved_wmask[4];
  306         unsigned long saved_tbase[4];
  307 };
  308 
  309 struct io7 {
  310         struct io7 *next;
  311 
  312         unsigned int pe;
  313         io7_port7_csrs *csrs;
  314         struct io7_port ports[IO7_NUM_PORTS];
  315 
  316         spinlock_t irq_lock;
  317 };
  318 
  319 #ifndef __EXTERN_INLINE
  320 # define __EXTERN_INLINE extern inline
  321 # define __IO_EXTERN_INLINE
  322 #endif
  323 
  324 /*
  325  * I/O functions. All access through linear space.
  326  */
  327 
  328 #define vucp    volatile unsigned char *
  329 #define vusp    volatile unsigned short *
  330 #define vuip    volatile unsigned int *
  331 #define vulp    volatile unsigned long *
  332 
  333 #ifdef CONFIG_VGA_HOSE
  334 extern struct pci_controller *pci_vga_hose;
  335 
  336 # define __marvel_is_port_vga(a)        \
  337         (((a) >= 0x3b0) && ((a) < 0x3e0) && ((a) != 0x3b3) && ((a) != 0x3d3))
  338 # define __marvel_is_mem_vga(a) (((a) >= 0xa0000) && ((a) <= 0xc0000))
  339 # define FIXUP_IOADDR_VGA(a) do {                       \
  340         if (pci_vga_hose && __marvel_is_port_vga(a))    \
  341                 a += pci_vga_hose->io_space->start;     \
  342     } while(0)
  343 #else
  344 # define FIXUP_IOADDR_VGA(a)
  345 #endif 
  346 
  347 #define __marvel_is_port_kbd(a) (((a) == 0x60) || ((a) == 0x64))
  348 #define __marvel_is_port_rtc(a) (((a) == 0x70) || ((a) == 0x71))
  349 
  350 #define FIXUP_IOADDR_LEGACY(a)
  351 
  352 #define FIXUP_IOADDR(a) do {                            \
  353         FIXUP_IOADDR_VGA(a);                            \
  354         FIXUP_IOADDR_LEGACY(a);                         \
  355     } while(0)
  356 
  357 #if 0
  358 # define IOBUG(x) printk x
  359 # define IOBUG_FILTER_IOADDR(a, x)      \
  360     if (!__marvel_is_port_kbd(a) && !__marvel_is_port_rtc(a)) IOBUG(x)
  361 #else
  362 # define IOBUG(x)
  363 # define IOBUG_FILTER_IOADDR(a, x)
  364 #endif
  365 
  366 extern u8 __marvel_rtc_io(int write, u8 b, unsigned long addr);
  367 #define __marvel_rtc_inb(a)     __marvel_rtc_io(0, 0, (a))
  368 #define __marvel_rtc_outb(b, a) __marvel_rtc_io(1, (b), (a))
  369 
  370 __EXTERN_INLINE int marvel_is_ioaddr(unsigned long addr)
  371 {
  372         return (addr & (1UL << 40)) != 0; /*FIXME - hardwire*/
  373 }
  374 
  375 __EXTERN_INLINE u8 marvel_inb(unsigned long addr)
  376 {
  377         FIXUP_IOADDR(addr);
  378         if (!marvel_is_ioaddr(addr)) {
  379                 if (__marvel_is_port_kbd(addr))
  380                         return (u8)0;
  381                 if (__marvel_is_port_rtc(addr))
  382                         return __marvel_rtc_inb(addr);
  383                 IOBUG_FILTER_IOADDR(addr, 
  384                                     ("Bad IO addr %lx - reading -1\n", addr));
  385                 return (u8)-1;
  386         }
  387         return __kernel_ldbu(*(vucp)addr);
  388 }
  389 
  390 __EXTERN_INLINE void marvel_outb(u8 b, unsigned long addr)
  391 {
  392         FIXUP_IOADDR(addr);
  393         if (!marvel_is_ioaddr(addr)) {
  394                 if (__marvel_is_port_rtc(addr)) 
  395                         return (void)__marvel_rtc_outb(b, addr);
  396                 IOBUG_FILTER_IOADDR(addr, 
  397                                     ("Bad IO addr %lx - reading -1\n", addr));
  398                 return;
  399         }
  400         __kernel_stb(b, *(vucp)addr);
  401         mb();
  402 }
  403 
  404 __EXTERN_INLINE u16 marvel_inw(unsigned long addr)
  405 {
  406         FIXUP_IOADDR(addr);
  407         if (!marvel_is_ioaddr(addr)) {
  408                 IOBUG_FILTER_IOADDR(addr, 
  409                                     ("Bad IO addr %lx - reading -1\n", addr));
  410                 return (u16)-1;
  411         }
  412         return __kernel_ldwu(*(vusp)addr);
  413 }
  414 
  415 __EXTERN_INLINE void marvel_outw(u16 w, unsigned long addr)
  416 {
  417         FIXUP_IOADDR(addr);
  418         if (!marvel_is_ioaddr(addr)) {
  419                 IOBUG_FILTER_IOADDR(addr, 
  420                                     ("Bad IO addr %lx - reading -1\n", addr));
  421                 return;
  422         }
  423         __kernel_stw(w, *(vusp)addr);
  424         mb();
  425 }
  426 
  427 __EXTERN_INLINE u32 marvel_inl(unsigned long addr)
  428 {
  429         FIXUP_IOADDR(addr);
  430         if (!marvel_is_ioaddr(addr)) {
  431                 IOBUG_FILTER_IOADDR(addr, 
  432                                     ("Bad IO addr %lx - reading -1\n", addr));
  433                 return (u32)-1;
  434         }
  435         return *(vuip)addr;
  436 }
  437 
  438 __EXTERN_INLINE void marvel_outl(u32 l, unsigned long addr)
  439 {
  440         FIXUP_IOADDR(addr);
  441         if (!marvel_is_ioaddr(addr)) {
  442                 IOBUG_FILTER_IOADDR(addr, 
  443                                     ("Bad IO addr %lx - reading -1\n", addr));
  444                 return;
  445         }
  446         *(vuip)addr = l;
  447         mb();
  448 }
  449 
  450 /*
  451  * Memory functions.  All accesses through linear space.
  452  */
  453 
  454 extern unsigned long marvel_ioremap(unsigned long addr, unsigned long size);
  455 extern void marvel_iounmap(unsigned long addr);
  456 
  457 __EXTERN_INLINE u8 marvel_readb(unsigned long addr)
  458 {
  459         if (!marvel_is_ioaddr(addr)) {
  460                 IOBUG(("Bad MEM addr %lx - reading -1\n", addr));
  461                 return (u8)-1;
  462         }
  463         return __kernel_ldbu(*(vucp)addr);
  464 }
  465 
  466 __EXTERN_INLINE u16 marvel_readw(unsigned long addr)
  467 {
  468         if (!marvel_is_ioaddr(addr)) {
  469                 IOBUG(("Bad MEM addr %lx - reading -1\n", addr));
  470                 return (u16)-1;
  471         }
  472         return __kernel_ldwu(*(vusp)addr);
  473 }
  474 
  475 __EXTERN_INLINE u32 marvel_readl(unsigned long addr)
  476 {
  477         if (!marvel_is_ioaddr(addr)) {
  478                 IOBUG(("Bad MEM addr %lx - reading -1\n", addr));
  479                 return (u32)-1;
  480         }
  481         return *(vuip)addr;
  482 }
  483 
  484 __EXTERN_INLINE u64 marvel_readq(unsigned long addr)
  485 {
  486         if (!marvel_is_ioaddr(addr)) {
  487                 IOBUG(("Bad MEM addr %lx - reading -1\n", addr));
  488                 return (u64)-1;
  489         }
  490         return *(vulp)addr;
  491 }
  492 
  493 __EXTERN_INLINE void marvel_writeb(u8 b, unsigned long addr)
  494 {
  495         if (!marvel_is_ioaddr(addr)) {
  496                 IOBUG(("Bad MEM addr %lx - dropping store\n", addr));
  497                 return;
  498         }
  499         __kernel_stb(b, *(vucp)addr);
  500 }
  501 
  502 __EXTERN_INLINE void marvel_writew(u16 w, unsigned long addr)
  503 {
  504         if (!marvel_is_ioaddr(addr)) {
  505                 IOBUG(("Bad MEM addr %lx - dropping store\n", addr));
  506                 return;
  507         }
  508         __kernel_stw(w, *(vusp)addr);
  509 }
  510 
  511 __EXTERN_INLINE void marvel_writel(u32 l, unsigned long addr)
  512 {
  513         if (!marvel_is_ioaddr(addr)) {
  514                 IOBUG(("Bad MEM addr %lx - dropping store\n", addr));
  515                 return;
  516         }
  517         *(vuip)addr = l;
  518 }
  519 
  520 __EXTERN_INLINE void marvel_writeq(u64 q, unsigned long addr)
  521 {
  522         if (!marvel_is_ioaddr(addr)) {
  523                 IOBUG(("Bad MEM addr %lx - dropping store\n", addr));
  524                 return;
  525         }
  526         *(vulp)addr = q;
  527 }
  528 
  529 #undef FIXUP_IOADDR
  530 #undef FIXUP_IOADDR_LEGACY
  531 #undef FIXUP_IOADDR_VGA
  532 
  533 #undef vucp
  534 #undef vusp
  535 #undef vuip
  536 #undef vulp
  537 
  538 #ifdef __WANT_IO_DEF
  539 
  540 #define __inb(p)                marvel_inb((unsigned long)(p))
  541 #define __inw(p)                marvel_inw((unsigned long)(p))
  542 #define __inl(p)                marvel_inl((unsigned long)(p))
  543 #define __outb(x,p)             marvel_outb((x),(unsigned long)(p))
  544 #define __outw(x,p)             marvel_outw((x),(unsigned long)(p))
  545 #define __outl(x,p)             marvel_outl((x),(unsigned long)(p))
  546 #define __readb(a)              marvel_readb((unsigned long)(a))
  547 #define __readw(a)              marvel_readw((unsigned long)(a))
  548 #define __readl(a)              marvel_readl((unsigned long)(a))
  549 #define __readq(a)              marvel_readq((unsigned long)(a))
  550 #define __writeb(x,a)           marvel_writeb((x),(unsigned long)(a))
  551 #define __writew(x,a)           marvel_writew((x),(unsigned long)(a))
  552 #define __writel(x,a)           marvel_writel((x),(unsigned long)(a))
  553 #define __writeq(x,a)           marvel_writeq((x),(unsigned long)(a))
  554 #define __ioremap(a,s)          marvel_ioremap((unsigned long)(a),(s))
  555 #define __iounmap(a)            marvel_iounmap((unsigned long)(a))
  556 #define __is_ioaddr(a)          marvel_is_ioaddr((unsigned long)(a))
  557 
  558 /* Disable direct inlining of these calls with the debug checks present.  */
  559 #if 0
  560 #define __raw_readb(a)          __readb(a)
  561 #define __raw_readw(a)          __readw(a)
  562 #define __raw_readl(a)          __readl(a)
  563 #define __raw_readq(a)          __readq(a)
  564 #define __raw_writeb(v,a)       __writeb(v,a)
  565 #define __raw_writew(v,a)       __writew(v,a)
  566 #define __raw_writel(v,a)       __writel(v,a)
  567 #define __raw_writeq(v,a)       __writeq(v,a)
  568 #endif
  569 
  570 #endif /* __WANT_IO_DEF */
  571 
  572 #ifdef __IO_EXTERN_INLINE
  573 # undef __EXTERN_INLINE
  574 # undef __IO_EXTERN_INLINE
  575 #endif
  576 
  577 #endif /* __KERNEL__ */
  578 
  579 #endif /* __ALPHA_MARVEL__H__ */
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FreeBSD/Linux Kernel Cross Reference sys/include/asm-alpha/core_marvel.h

FreeBSD/Linux Kernel Cross Reference
sys/include/asm-alpha/core_marvel.h
