1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 Waldorf GMBH
7 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
8 * Copyright (C) 1996 Paul M. Antoine
9 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
10 */
11 #ifndef _ASM_PROCESSOR_H
12 #define _ASM_PROCESSOR_H
13
14 #include <linux/config.h>
15 #include <linux/cache.h>
16
17 /*
18 * Return current * instruction pointer ("program counter").
19 */
20 #define current_text_addr() \
21 ({ \
22 void *_a; \
23 \
24 __asm__ ("bal\t1f\t\t\t# current_text_addr\n" \
25 "1:\tmove\t%0, $31" \
26 : "=r" (_a) \
27 : \
28 : "$31"); \
29 \
30 _a; \
31 })
32
33 #ifndef __ASSEMBLY__
34 #include <linux/smp.h>
35
36 #include <asm/cachectl.h>
37 #include <asm/mipsregs.h>
38 #include <asm/reg.h>
39 #include <asm/system.h>
40
41 #if defined(CONFIG_SGI_IP27)
42 #include <asm/sn/types.h>
43 #include <asm/sn/intr_public.h>
44 #endif
45
46 /*
47 * Descriptor for a cache
48 */
49 struct cache_desc {
50 unsigned short linesz; /* Size of line in bytes */
51 unsigned short ways; /* Number of ways */
52 unsigned short sets; /* Number of lines per set */
53 unsigned int waysize; /* Bytes per way */
54 unsigned int waybit; /* Bits to select in a cache set */
55 unsigned int flags; /* Flags describing cache properties */
56 };
57
58 /*
59 * Flag definitions
60 */
61 #define MIPS_CACHE_NOT_PRESENT 0x00000001
62 #define MIPS_CACHE_VTAG 0x00000002 /* Virtually tagged cache */
63 #define MIPS_CACHE_ALIASES 0x00000004 /* Cache could have aliases */
64 #define MIPS_CACHE_IC_F_DC 0x00000008 /* Ic can refill from D-cache */
65
66 struct cpuinfo_mips {
67 unsigned long udelay_val;
68 unsigned long *pgd_quick;
69 unsigned long *pmd_quick;
70 unsigned long *pte_quick;
71 unsigned long pgtable_cache_sz;
72 unsigned long asid_cache;
73 #if defined(CONFIG_SGI_IP27)
74 cpuid_t p_cpuid; /* PROM assigned cpuid */
75 cnodeid_t p_nodeid; /* my node ID in compact-id-space */
76 nasid_t p_nasid; /* my node ID in numa-as-id-space */
77 unsigned char p_slice; /* Physical position on node board */
78 hub_intmasks_t p_intmasks; /* SN0 per-CPU interrupt masks */
79 #endif
80 #if 0
81 unsigned long loops_per_sec;
82 unsigned long pgtable_cache_sz;
83 unsigned long ipi_count;
84 unsigned long irq_attempt[NR_IRQS];
85 unsigned long smp_local_irq_count;
86 unsigned long prof_multiplier;
87 unsigned long prof_counter;
88 #endif
89
90 /*
91 * Capability and feature descriptor structure for MIPS CPU
92 */
93 unsigned long options;
94 unsigned int processor_id;
95 unsigned int fpu_id;
96 unsigned int cputype;
97 int isa_level;
98 int tlbsize;
99 struct cache_desc icache; /* Primary I-cache */
100 struct cache_desc dcache; /* Primary D or combined I/D cache */
101 struct cache_desc scache; /* Secondary cache */
102 struct cache_desc tcache; /* Tertiary/split secondary cache */
103 } __attribute__((aligned(SMP_CACHE_BYTES)));
104
105 /*
106 * Assumption: Options of CPU 0 are a superset of all processors.
107 * This is true for all known MIPS systems.
108 */
109 #define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB)
110 #define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX)
111 #define cpu_has_4ktlb (cpu_data[0].options & MIPS_CPU_4KTLB)
112 #define cpu_has_fpu (cpu_data[0].options & MIPS_CPU_FPU)
113 #define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR)
114 #define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER)
115 #define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH)
116 #define cpu_has_mips16 (cpu_data[0].options & MIPS_CPU_MIPS16)
117 #define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC)
118 #define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE)
119 #define cpu_has_cache_cdex (cpu_data[0].options & MIPS_CPU_CACHE_CDEX)
120 #define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK)
121 #define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG)
122 #define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX)
123 #define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC)
124 #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
125 #define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
126 #define cpu_has_ic_fills_f_dc (cpu_data[0].dcache.flags & MIPS_CACHE_IC_F_DC)
127 #define cpu_has_64bits 1
128 #define cpu_has_subset_pcaches (cpu_data[0].options & MIPS_CPU_SUBSET_CACHES)
129
130 extern struct cpuinfo_mips cpu_data[];
131 #define current_cpu_data cpu_data[smp_processor_id()]
132
133 extern void cpu_probe(void);
134 extern void cpu_report(void);
135
136 /*
137 * System setup and hardware flags..
138 */
139 extern void (*cpu_wait)(void);
140
141 extern unsigned int vced_count, vcei_count;
142
143 /*
144 * Bus types (default is ISA, but people can check others with these..)
145 */
146 #ifdef CONFIG_EISA
147 extern int EISA_bus;
148 #else
149 #define EISA_bus (0)
150 #endif
151
152 #define MCA_bus 0
153 #define MCA_bus__is_a_macro /* for versions in ksyms.c */
154
155 /*
156 * User space process size: 1TB. This is hardcoded into a few places,
157 * so don't change it unless you know what you are doing. TASK_SIZE
158 * is limited to 1TB by the R4000 architecture; R10000 and better can
159 * support 16TB.
160 */
161 #define TASK_SIZE32 0x7fff8000UL
162 #define TASK_SIZE 0x10000000000UL
163
164 /* This decides where the kernel will search for a free chunk of vm
165 * space during mmap's.
166 */
167 #define TASK_UNMAPPED_BASE ((current->thread.mflags & MF_32BIT_ADDR) ? \
168 (TASK_SIZE32 / 3) : (TASK_SIZE / 3))
169
170 /*
171 * Size of io_bitmap in longwords: 32 is ports 0-0x3ff.
172 */
173 #define IO_BITMAP_SIZE 32
174
175 #define NUM_FPU_REGS 32
176
177 struct mips_fpu_hard_struct {
178 unsigned long fp_regs[NUM_FPU_REGS];
179 unsigned int control;
180 };
181
182 /*
183 * It would be nice to add some more fields for emulator statistics, but there
184 * are a number of fixed offsets in offset.h and elsewhere that would have to
185 * be recalculated by hand. So the additional information will be private to
186 * the FPU emulator for now. See asm-mips/fpu_emulator.h.
187 */
188 typedef u64 fpureg_t;
189 struct mips_fpu_soft_struct {
190 fpureg_t regs[NUM_FPU_REGS];
191 unsigned int sr;
192 };
193
194 union mips_fpu_union {
195 struct mips_fpu_hard_struct hard;
196 struct mips_fpu_soft_struct soft;
197 };
198
199 #define INIT_FPU { \
200 {{0,},} \
201 }
202
203 typedef struct {
204 unsigned long seg;
205 } mm_segment_t;
206
207 /*
208 * If you change thread_struct remember to change the #defines below too!
209 */
210 struct thread_struct {
211 /* Saved main processor registers. */
212 unsigned long reg16;
213 unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23;
214 unsigned long reg29, reg30, reg31;
215
216 /* Saved cp0 stuff. */
217 unsigned long cp0_status;
218
219 /* Saved fpu/fpu emulator stuff. */
220 union mips_fpu_union fpu;
221
222 /* Other stuff associated with the thread. */
223 unsigned long cp0_badvaddr; /* Last user fault */
224 unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */
225 unsigned long error_code;
226 unsigned long trap_no;
227 #define MF_FIXADE 1 /* Fix address errors in software */
228 #define MF_LOGADE 2 /* Log address errors to syslog */
229 #define MF_32BIT_REGS 4 /* also implies 16/32 fprs */
230 #define MF_32BIT_ADDR 8 /* 32-bit address space (o32/n32) */
231 unsigned long mflags;
232 mm_segment_t current_ds;
233 unsigned long irix_trampoline; /* Wheee... */
234 unsigned long irix_oldctx;
235 };
236
237 #define MF_ABI_MASK (MF_32BIT_REGS | MF_32BIT_ADDR)
238 #define MF_O32 (MF_32BIT_REGS | MF_32BIT_ADDR)
239 #define MF_N32 MF_32BIT_ADDR
240 #define MF_N64 0
241
242 #endif /* !__ASSEMBLY__ */
243
244 #define INIT_THREAD { \
245 /* \
246 * saved main processor registers \
247 */ \
248 0, 0, 0, 0, 0, 0, 0, 0, \
249 0, 0, 0, \
250 /* \
251 * saved cp0 stuff \
252 */ \
253 0, \
254 /* \
255 * saved fpu/fpu emulator stuff \
256 */ \
257 INIT_FPU, \
258 /* \
259 * Other stuff associated with the process \
260 */ \
261 0, 0, 0, 0, \
262 /* \
263 * For now the default is to fix address errors \
264 */ \
265 MF_FIXADE, KERNEL_DS, 0, 0 \
266 }
267
268 #ifdef __KERNEL__
269
270 #define KERNEL_STACK_SIZE 0x4000
271
272 #ifndef __ASSEMBLY__
273
274 /* Free all resources held by a thread. */
275 #define release_thread(thread) do { } while(0)
276
277 extern int arch_kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
278
279 /* Copy and release all segment info associated with a VM */
280 #define copy_segments(p, mm) do { } while(0)
281 #define release_segments(mm) do { } while(0)
282
283 struct mips_frame_info {
284 int frame_offset;
285 int pc_offset;
286 };
287 extern struct mips_frame_info schedule_frame;
288 /*
289 * Return saved PC of a blocked thread.
290 */
291 static inline unsigned long thread_saved_pc(struct thread_struct *t)
292 {
293 extern void ret_from_sys_call(void);
294
295 /* New born processes are a special case */
296 if (t->reg31 == (unsigned long) ret_from_sys_call)
297 return t->reg31;
298
299 if (schedule_frame.pc_offset < 0)
300 return 0;
301 return ((unsigned long *)t->reg29)[schedule_frame.pc_offset];
302 }
303
304 #define user_mode(regs) (((regs)->cp0_status & ST0_KSU) == KSU_USER)
305
306 /*
307 * Do necessary setup to start up a newly executed thread.
308 */
309 extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp);
310
311 struct task_struct;
312 unsigned long get_wchan(struct task_struct *p);
313
314 #define __PT_REG(reg) ((long)&((struct pt_regs *)0)->reg - sizeof(struct pt_regs))
315 #define __KSTK_TOS(tsk) ((unsigned long)(tsk) + KERNEL_STACK_SIZE - 32)
316 #define KSTK_EIP(tsk) (*(unsigned long *)(__KSTK_TOS(tsk) + __PT_REG(cp0_epc)))
317 #define KSTK_ESP(tsk) (*(unsigned long *)(__KSTK_TOS(tsk) + __PT_REG(regs[29])))
318 #define KSTK_STATUS(tsk) (*(unsigned long *)(__KSTK_TOS(tsk) + __PT_REG(cp0_status)))
319
320 /* Allocation and freeing of basic task resources. */
321 /*
322 * NOTE! The task struct and the stack go together
323 */
324 #define THREAD_SIZE (2*PAGE_SIZE)
325 #define alloc_task_struct() \
326 ((struct task_struct *) __get_free_pages(GFP_KERNEL, 2))
327 #define free_task_struct(p) free_pages((unsigned long)(p), 2)
328 #define get_task_struct(tsk) atomic_inc(&virt_to_page(tsk)->count)
329
330 #define init_task (init_task_union.task)
331 #define init_stack (init_task_union.stack)
332
333 #define cpu_relax() barrier()
334
335 #endif /* !__ASSEMBLY__ */
336 #endif /* __KERNEL__ */
337
338 /*
339 * Return_address is a replacement for __builtin_return_address(count)
340 * which on certain architectures cannot reasonably be implemented in GCC
341 * (MIPS, Alpha) or is unuseable with -fomit-frame-pointer (i386).
342 * Note that __builtin_return_address(x>=1) is forbidden because GCC
343 * aborts compilation on some CPUs. It's simply not possible to unwind
344 * some CPU's stackframes.
345 *
346 * __builtin_return_address works only for non-leaf functions. We avoid the
347 * overhead of a function call by forcing the compiler to save the return
348 * address register on the stack.
349 */
350 #define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
351
352 #endif /* _ASM_PROCESSOR_H */
Cache object: 27df5a96e93dd68211bfe6646722a700
|