The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/include/asm-x86_64/cpufeature.h

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    1 /*
    2  * cpufeature.h
    3  *
    4  * Defines x86 CPU feature bits
    5  */
    6 
    7 #ifndef __ASM_X8664_CPUFEATURE_H
    8 #define __ASM_X8664_CPUFEATURE_H
    9 
   10 #define NCAPINTS        7       /* N 32-bit words worth of info */
   11 
   12 /* Intel-defined CPU features, CPUID level 0x00000001, word 0 */
   13 #define X86_FEATURE_FPU         (0*32+ 0) /* Onboard FPU */
   14 #define X86_FEATURE_VME         (0*32+ 1) /* Virtual Mode Extensions */
   15 #define X86_FEATURE_DE          (0*32+ 2) /* Debugging Extensions */
   16 #define X86_FEATURE_PSE         (0*32+ 3) /* Page Size Extensions */
   17 #define X86_FEATURE_TSC         (0*32+ 4) /* Time Stamp Counter */
   18 #define X86_FEATURE_MSR         (0*32+ 5) /* Model-Specific Registers, RDMSR, WRMSR */
   19 #define X86_FEATURE_PAE         (0*32+ 6) /* Physical Address Extensions */
   20 #define X86_FEATURE_MCE         (0*32+ 7) /* Machine Check Architecture */
   21 #define X86_FEATURE_CX8         (0*32+ 8) /* CMPXCHG8 instruction */
   22 #define X86_FEATURE_APIC        (0*32+ 9) /* Onboard APIC */
   23 #define X86_FEATURE_SEP         (0*32+11) /* SYSENTER/SYSEXIT */
   24 #define X86_FEATURE_MTRR        (0*32+12) /* Memory Type Range Registers */
   25 #define X86_FEATURE_PGE         (0*32+13) /* Page Global Enable */
   26 #define X86_FEATURE_MCA         (0*32+14) /* Machine Check Architecture */
   27 #define X86_FEATURE_CMOV        (0*32+15) /* CMOV instruction (FCMOVCC and FCOMI too if FPU present) */
   28 #define X86_FEATURE_PAT         (0*32+16) /* Page Attribute Table */
   29 #define X86_FEATURE_PSE36       (0*32+17) /* 36-bit PSEs */
   30 #define X86_FEATURE_PN          (0*32+18) /* Processor serial number */
   31 #define X86_FEATURE_CLFLSH      (0*32+19) /* Supports the CLFLUSH instruction */
   32 #define X86_FEATURE_DS          (0*32+21) /* Debug Store */
   33 #define X86_FEATURE_ACPI        (0*32+22) /* ACPI via MSR */
   34 #define X86_FEATURE_MMX         (0*32+23) /* Multimedia Extensions */
   35 #define X86_FEATURE_FXSR        (0*32+24) /* FXSAVE and FXRSTOR instructions (fast save and restore */
   36                                           /* of FPU context), and CR4.OSFXSR available */
   37 #define X86_FEATURE_XMM         (0*32+25) /* Streaming SIMD Extensions */
   38 #define X86_FEATURE_XMM2        (0*32+26) /* Streaming SIMD Extensions-2 */
   39 #define X86_FEATURE_SELFSNOOP   (0*32+27) /* CPU self snoop */
   40 #define X86_FEATURE_HT          (0*32+28) /* Hyper-Threading */
   41 #define X86_FEATURE_ACC         (0*32+29) /* Automatic clock control */
   42 #define X86_FEATURE_IA64        (0*32+30) /* IA-64 processor */
   43 
   44 /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
   45 /* Don't duplicate feature flags which are redundant with Intel! */
   46 #define X86_FEATURE_SYSCALL     (1*32+11) /* SYSCALL/SYSRET */
   47 #define X86_FEATURE_MMXEXT      (1*32+22) /* AMD MMX extensions */
   48 #define X86_FEATURE_FXSR_OPT    (1*32+25) /* FXSR optimizations */
   49 #define X86_FEATURE_RDTSCP      (1*32+27) /* RDTSCP */
   50 #define X86_FEATURE_LM          (1*32+29) /* Long Mode (x86-64) */
   51 #define X86_FEATURE_3DNOWEXT    (1*32+30) /* AMD 3DNow! extensions */
   52 #define X86_FEATURE_3DNOW       (1*32+31) /* 3DNow! */
   53 
   54 /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
   55 #define X86_FEATURE_RECOVERY    (2*32+ 0) /* CPU in recovery mode */
   56 #define X86_FEATURE_LONGRUN     (2*32+ 1) /* Longrun power control */
   57 #define X86_FEATURE_LRTI        (2*32+ 3) /* LongRun table interface */
   58 
   59 /* Other features, Linux-defined mapping, word 3 */
   60 /* This range is used for feature bits which conflict or are synthesized */
   61 #define X86_FEATURE_CXMMX       (3*32+ 0) /* Cyrix MMX extensions */
   62 #define X86_FEATURE_K6_MTRR     (3*32+ 1) /* AMD K6 nonstandard MTRRs */
   63 #define X86_FEATURE_CYRIX_ARR   (3*32+ 2) /* Cyrix ARRs (= MTRRs) */
   64 #define X86_FEATURE_CENTAUR_MCR (3*32+ 3) /* Centaur MCRs (= MTRRs) */
   65 #define X86_FEATURE_REP_GOOD    (3*32+ 4) /* rep microcode works well on this CPU */
   66 #define X86_FEATURE_CONSTANT_TSC (3*32+5) /* TSC runs at constant rate */
   67 #define X86_FEATURE_SYNC_RDTSC  (3*32+6)  /* RDTSC syncs CPU core */
   68 #define X86_FEATURE_FXSAVE_LEAK (3*32+7)  /* FIP/FOP/FDP leaks through FXSAVE */
   69 #define X86_FEATURE_UP          (3*32+8) /* SMP kernel running on UP */
   70 #define X86_FEATURE_ARCH_PERFMON (3*32+9) /* Intel Architectural PerfMon */
   71 #define X86_FEATURE_PEBS        (3*32+10) /* Precise-Event Based Sampling */
   72 #define X86_FEATURE_BTS         (3*32+11) /* Branch Trace Store */
   73 
   74 /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
   75 #define X86_FEATURE_XMM3        (4*32+ 0) /* Streaming SIMD Extensions-3 */
   76 #define X86_FEATURE_MWAIT       (4*32+ 3) /* Monitor/Mwait support */
   77 #define X86_FEATURE_DSCPL       (4*32+ 4) /* CPL Qualified Debug Store */
   78 #define X86_FEATURE_EST         (4*32+ 7) /* Enhanced SpeedStep */
   79 #define X86_FEATURE_TM2         (4*32+ 8) /* Thermal Monitor 2 */
   80 #define X86_FEATURE_CID         (4*32+10) /* Context ID */
   81 #define X86_FEATURE_CX16        (4*32+13) /* CMPXCHG16B */
   82 #define X86_FEATURE_XTPR        (4*32+14) /* Send Task Priority Messages */
   83 
   84 /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
   85 #define X86_FEATURE_XSTORE      (5*32+ 2) /* on-CPU RNG present (xstore insn) */
   86 #define X86_FEATURE_XSTORE_EN   (5*32+ 3) /* on-CPU RNG enabled */
   87 #define X86_FEATURE_XCRYPT      (5*32+ 6) /* on-CPU crypto (xcrypt insn) */
   88 #define X86_FEATURE_XCRYPT_EN   (5*32+ 7) /* on-CPU crypto enabled */
   89 
   90 /* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */
   91 #define X86_FEATURE_LAHF_LM     (6*32+ 0) /* LAHF/SAHF in long mode */
   92 #define X86_FEATURE_CMP_LEGACY  (6*32+ 1) /* If yes HyperThreading not valid */
   93 
   94 #define cpu_has(c, bit)                test_bit(bit, (c)->x86_capability)
   95 #define boot_cpu_has(bit)      test_bit(bit, boot_cpu_data.x86_capability)
   96 
   97 #define cpu_has_fpu            1
   98 #define cpu_has_vme            0
   99 #define cpu_has_de             1
  100 #define cpu_has_pse            1
  101 #define cpu_has_tsc            1
  102 #define cpu_has_pae            ___BUG___
  103 #define cpu_has_pge            1
  104 #define cpu_has_apic           boot_cpu_has(X86_FEATURE_APIC)
  105 #define cpu_has_mtrr           1
  106 #define cpu_has_mmx            1
  107 #define cpu_has_fxsr           1
  108 #define cpu_has_xmm            1
  109 #define cpu_has_xmm2           1
  110 #define cpu_has_xmm3           boot_cpu_has(X86_FEATURE_XMM3)
  111 #define cpu_has_ht             boot_cpu_has(X86_FEATURE_HT)
  112 #define cpu_has_mp             1 /* XXX */
  113 #define cpu_has_k6_mtrr        0
  114 #define cpu_has_cyrix_arr      0
  115 #define cpu_has_centaur_mcr    0
  116 #define cpu_has_clflush        boot_cpu_has(X86_FEATURE_CLFLSH)
  117 #define cpu_has_ds             boot_cpu_has(X86_FEATURE_DS)
  118 #define cpu_has_pebs           boot_cpu_has(X86_FEATURE_PEBS)
  119 #define cpu_has_bts            boot_cpu_has(X86_FEATURE_BTS)
  120 
  121 #endif /* __ASM_X8664_CPUFEATURE_H */

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