cisreg.h

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    1 /*
    2  * cisreg.h 1.17 2000/06/12 21:55:41
    3  *
    4  * The contents of this file are subject to the Mozilla Public License
    5  * Version 1.1 (the "License"); you may not use this file except in
    6  * compliance with the License. You may obtain a copy of the License
    7  * at http://www.mozilla.org/MPL/
    8  *
    9  * Software distributed under the License is distributed on an "AS IS"
   10  * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
   11  * the License for the specific language governing rights and
   12  * limitations under the License. 
   13  *
   14  * The initial developer of the original code is David A. Hinds
   15  * <dahinds@users.sourceforge.net>.  Portions created by David A. Hinds
   16  * are Copyright (C) 1999 David A. Hinds.  All Rights Reserved.
   17  *
   18  * Alternatively, the contents of this file may be used under the
   19  * terms of the GNU General Public License version 2 (the "GPL"), in which
   20  * case the provisions of the GPL are applicable instead of the
   21  * above.  If you wish to allow the use of your version of this file
   22  * only under the terms of the GPL and not to allow others to use
   23  * your version of this file under the MPL, indicate your decision by
   24  * deleting the provisions above and replace them with the notice and
   25  * other provisions required by the GPL.  If you do not delete the
   26  * provisions above, a recipient may use your version of this file
   27  * under either the MPL or the GPL.
   28  */
   29 
   30 #ifndef _LINUX_CISREG_H
   31 #define _LINUX_CISREG_H
   32 
   33 /*
   34  * Offsets from ConfigBase for CIS registers
   35  */
   36 #define CISREG_COR              0x00
   37 #define CISREG_CCSR             0x02
   38 #define CISREG_PRR              0x04
   39 #define CISREG_SCR              0x06
   40 #define CISREG_ESR              0x08
   41 #define CISREG_IOBASE_0         0x0a
   42 #define CISREG_IOBASE_1         0x0c
   43 #define CISREG_IOBASE_2         0x0e
   44 #define CISREG_IOBASE_3         0x10
   45 #define CISREG_IOSIZE           0x12
   46 
   47 /*
   48  * Configuration Option Register
   49  */
   50 #define COR_CONFIG_MASK         0x3f
   51 #define COR_MFC_CONFIG_MASK     0x38
   52 #define COR_FUNC_ENA            0x01
   53 #define COR_ADDR_DECODE         0x02
   54 #define COR_IREQ_ENA            0x04
   55 #define COR_LEVEL_REQ           0x40
   56 #define COR_SOFT_RESET          0x80
   57 
   58 /*
   59  * Card Configuration and Status Register
   60  */
   61 #define CCSR_INTR_ACK           0x01
   62 #define CCSR_INTR_PENDING       0x02
   63 #define CCSR_POWER_DOWN         0x04
   64 #define CCSR_AUDIO_ENA          0x08
   65 #define CCSR_IOIS8              0x20
   66 #define CCSR_SIGCHG_ENA         0x40
   67 #define CCSR_CHANGED            0x80
   68 
   69 /*
   70  * Pin Replacement Register
   71  */
   72 #define PRR_WP_STATUS           0x01
   73 #define PRR_READY_STATUS        0x02
   74 #define PRR_BVD2_STATUS         0x04
   75 #define PRR_BVD1_STATUS         0x08
   76 #define PRR_WP_EVENT            0x10
   77 #define PRR_READY_EVENT         0x20
   78 #define PRR_BVD2_EVENT          0x40
   79 #define PRR_BVD1_EVENT          0x80
   80 
   81 /*
   82  * Socket and Copy Register
   83  */
   84 #define SCR_SOCKET_NUM          0x0f
   85 #define SCR_COPY_NUM            0x70
   86 
   87 /*
   88  * Extended Status Register
   89  */
   90 #define ESR_REQ_ATTN_ENA        0x01
   91 #define ESR_REQ_ATTN            0x10
   92 
   93 /*
   94  * CardBus Function Status Registers
   95  */
   96 #define CBFN_EVENT              0x00
   97 #define CBFN_MASK               0x04
   98 #define CBFN_STATE              0x08
   99 #define CBFN_FORCE              0x0c
  100 
  101 /*
  102  * These apply to all the CardBus function registers
  103  */
  104 #define CBFN_WP                 0x0001
  105 #define CBFN_READY              0x0002
  106 #define CBFN_BVD2               0x0004
  107 #define CBFN_BVD1               0x0008
  108 #define CBFN_GWAKE              0x0010
  109 #define CBFN_INTR               0x8000
  110 
  111 /*
  112  * Extra bits in the Function Event Mask Register
  113  */
  114 #define FEMR_BAM_ENA            0x0020
  115 #define FEMR_PWM_ENA            0x0040
  116 #define FEMR_WKUP_MASK          0x4000
  117 
  118 /*
  119  * Indirect Addressing Registers for Zoomed Video: these are addresses
  120  * in common memory space
  121  */
  122 #define CISREG_ICTRL0           0x02    /* control registers */
  123 #define CISREG_ICTRL1           0x03
  124 #define CISREG_IADDR0           0x04    /* address registers */
  125 #define CISREG_IADDR1           0x05
  126 #define CISREG_IADDR2           0x06
  127 #define CISREG_IADDR3           0x07
  128 #define CISREG_IDATA0           0x08    /* data registers */
  129 #define CISREG_IDATA1           0x09
  130 
  131 #define ICTRL0_COMMON           0x01
  132 #define ICTRL0_AUTOINC          0x02
  133 #define ICTRL0_BYTEGRAN         0x04
  134 
  135 #endif /* _LINUX_CISREG_H */

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FreeBSD/Linux Kernel Cross Reference sys/include/pcmcia/cisreg.h

FreeBSD/Linux Kernel Cross Reference
sys/include/pcmcia/cisreg.h