FreeBSD/Linux Kernel Cross Reference
sys/isa/sioreg.h
1 /*-
2 * Copyright (c) 1991 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by the University of
16 * California, Berkeley and its contributors.
17 * 4. Neither the name of the University nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 *
33 * from: @(#)comreg.h 7.2 (Berkeley) 5/9/91
34 * $FreeBSD$
35 */
36
37 /* Receiver clock frequency for "standard" pc serial ports. */
38 #define DEFAULT_RCLK 1843200
39
40 /* interrupt enable register */
41 #define IER_ERXRDY 0x1
42 #define IER_ETXRDY 0x2
43 #define IER_ERLS 0x4
44 #define IER_EMSC 0x8
45
46 /* interrupt identification register */
47 #define IIR_IMASK 0xf
48 #define IIR_RXTOUT 0xc
49 #define IIR_RLS 0x6
50 #define IIR_RXRDY 0x4
51 #define IIR_TXRDY 0x2
52 #define IIR_NOPEND 0x1
53 #define IIR_MLSC 0x0
54 #define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */
55
56 /* fifo control register */
57 #define FIFO_ENABLE 0x01
58 #define FIFO_RCV_RST 0x02
59 #define FIFO_XMT_RST 0x04
60 #define FIFO_DMA_MODE 0x08
61 #define FIFO_RX_LOW 0x00
62 #define FIFO_RX_MEDL 0x40
63 #define FIFO_RX_MEDH 0x80
64 #define FIFO_RX_HIGH 0xc0
65
66 /* character format control register (aka line control register) */
67 #define CFCR_DLAB 0x80
68 #define CFCR_SBREAK 0x40
69 #define CFCR_PZERO 0x30
70 #define CFCR_PONE 0x20
71 #define CFCR_PEVEN 0x10
72 #define CFCR_PODD 0x00
73 #define CFCR_PENAB 0x08
74 #define CFCR_STOPB 0x04
75 #define CFCR_8BITS 0x03
76 #define CFCR_7BITS 0x02
77 #define CFCR_6BITS 0x01
78 #define CFCR_5BITS 0x00
79 #define CFCR_EFR_ENABLE 0xbf /* magic to enable EFR on 16650 up */
80
81 /* modem control register */
82 #define MCR_PRESCALE 0x80 /* only available on 16650 up */
83 #define MCR_LOOPBACK 0x10
84 #define MCR_IENABLE 0x08
85 #define MCR_DRS 0x04
86 #define MCR_RTS 0x02
87 #define MCR_DTR 0x01
88
89 /* line status register */
90 #define LSR_RCV_FIFO 0x80
91 #define LSR_TSRE 0x40
92 #define LSR_TXRDY 0x20
93 #define LSR_BI 0x10
94 #define LSR_FE 0x08
95 #define LSR_PE 0x04
96 #define LSR_OE 0x02
97 #define LSR_RXRDY 0x01
98 #define LSR_RCV_MASK 0x1f
99
100 /* modem status register */
101 #define MSR_DCD 0x80
102 #define MSR_RI 0x40
103 #define MSR_DSR 0x20
104 #define MSR_CTS 0x10
105 #define MSR_DDCD 0x08
106 #define MSR_TERI 0x04
107 #define MSR_DDSR 0x02
108 #define MSR_DCTS 0x01
109
110 /* enhanced feature register (only available on 16650 up) */
111 #define com_efr com_fifo
112 #define EFR_EFE 0x10 /* enhanced functions enable */
113
114 #ifdef PC98
115 /* Hardware extension mode register for RSB-2000/3000. */
116 #define EMR_EXBUFF 0x04
117 #define EMR_CTSFLW 0x08
118 #define EMR_DSRFLW 0x10
119 #define EMR_RTSFLW 0x20
120 #define EMR_DTRFLW 0x40
121 #define EMR_EFMODE 0x80
122 #endif
123
124 /* speed to initialize to during chip tests */
125 #define SIO_TEST_SPEED 9600
126
127 /* default serial console speed if not set with sysctl or probed from boot */
128 #ifndef CONSPEED
129 #define CONSPEED 9600
130 #endif
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