The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]

FreeBSD/Linux Kernel Cross Reference
sys/mips/atheros/ar71xx_chip.c

Version: -  FREEBSD  -  FREEBSD-13-STABLE  -  FREEBSD-13-0  -  FREEBSD-12-STABLE  -  FREEBSD-12-0  -  FREEBSD-11-STABLE  -  FREEBSD-11-0  -  FREEBSD-10-STABLE  -  FREEBSD-10-0  -  FREEBSD-9-STABLE  -  FREEBSD-9-0  -  FREEBSD-8-STABLE  -  FREEBSD-8-0  -  FREEBSD-7-STABLE  -  FREEBSD-7-0  -  FREEBSD-6-STABLE  -  FREEBSD-6-0  -  FREEBSD-5-STABLE  -  FREEBSD-5-0  -  FREEBSD-4-STABLE  -  FREEBSD-3-STABLE  -  FREEBSD22  -  l41  -  OPENBSD  -  linux-2.6  -  MK84  -  PLAN9  -  xnu-8792 
SearchContext: -  none  -  3  -  10 

    1 /*-
    2  * Copyright (c) 2010 Adrian Chadd
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  */
   26 
   27 #include <sys/cdefs.h>
   28 __FBSDID("$FreeBSD$");
   29 
   30 #include "opt_ddb.h"
   31 
   32 #include <sys/param.h>
   33 #include <sys/conf.h>
   34 #include <sys/kernel.h>
   35 #include <sys/systm.h>
   36 #include <sys/bus.h>
   37 #include <sys/cons.h>
   38 #include <sys/kdb.h>
   39 #include <sys/reboot.h>
   40 
   41 #include <vm/vm.h>
   42 #include <vm/vm_page.h>
   43 
   44 #include <net/ethernet.h>
   45 
   46 #include <machine/clock.h>
   47 #include <machine/cpu.h>
   48 #include <machine/cpuregs.h>
   49 #include <machine/hwfunc.h>
   50 #include <machine/md_var.h>
   51 #include <machine/trap.h>
   52 #include <machine/vmparam.h>
   53 
   54 #include <mips/atheros/ar71xxreg.h>
   55 #include <mips/atheros/ar71xx_chip.h>
   56 #include <mips/atheros/ar71xx_cpudef.h>
   57 
   58 #include <mips/sentry5/s5reg.h>
   59 
   60 /* XXX these should replace the current definitions in ar71xxreg.h */
   61 /* XXX perhaps an ar71xx_chip.h header file? */
   62 #define AR71XX_PLL_REG_CPU_CONFIG       AR71XX_PLL_CPU_BASE + 0x00
   63 #define AR71XX_PLL_REG_SEC_CONFIG       AR71XX_PLL_CPU_BASE + 0x04
   64 #define AR71XX_PLL_REG_ETH0_INT_CLOCK   AR71XX_PLL_CPU_BASE + 0x10
   65 #define AR71XX_PLL_REG_ETH1_INT_CLOCK   AR71XX_PLL_CPU_BASE + 0x14
   66 
   67 #define AR71XX_PLL_DIV_SHIFT            3
   68 #define AR71XX_PLL_DIV_MASK             0x1f
   69 #define AR71XX_CPU_DIV_SHIFT            16
   70 #define AR71XX_CPU_DIV_MASK             0x3
   71 #define AR71XX_DDR_DIV_SHIFT            18
   72 #define AR71XX_DDR_DIV_MASK             0x3
   73 #define AR71XX_AHB_DIV_SHIFT            20
   74 #define AR71XX_AHB_DIV_MASK             0x7
   75 
   76 /* XXX these shouldn't be in here - this file is a per-chip file */
   77 /* XXX these should be in the top-level ar71xx type, not ar71xx -chip */
   78 uint32_t u_ar71xx_cpu_freq;
   79 uint32_t u_ar71xx_ahb_freq;
   80 uint32_t u_ar71xx_ddr_freq;
   81 uint32_t u_ar71xx_uart_freq;
   82 uint32_t u_ar71xx_wdt_freq;
   83 uint32_t u_ar71xx_refclk;
   84 
   85 static void
   86 ar71xx_chip_detect_mem_size(void)
   87 {
   88 }
   89 
   90 static void
   91 ar71xx_chip_detect_sys_frequency(void)
   92 {
   93         uint32_t pll;
   94         uint32_t freq;
   95         uint32_t div;
   96 
   97         u_ar71xx_refclk = AR71XX_BASE_FREQ;
   98 
   99         pll = ATH_READ_REG(AR71XX_PLL_REG_CPU_CONFIG);
  100 
  101         div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
  102         freq = div * AR71XX_BASE_FREQ;
  103 
  104         div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
  105         u_ar71xx_cpu_freq = freq / div;
  106 
  107         div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
  108         u_ar71xx_ddr_freq = freq / div;
  109 
  110         div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
  111         u_ar71xx_ahb_freq = u_ar71xx_cpu_freq / div;
  112         u_ar71xx_wdt_freq = u_ar71xx_cpu_freq / div;
  113         u_ar71xx_uart_freq = u_ar71xx_cpu_freq / div;
  114 }
  115 
  116 /*
  117  * This does not lock the CPU whilst doing the work!
  118  */
  119 static void
  120 ar71xx_chip_device_stop(uint32_t mask)
  121 {
  122         uint32_t reg;
  123 
  124         reg = ATH_READ_REG(AR71XX_RST_RESET);
  125         ATH_WRITE_REG(AR71XX_RST_RESET, reg | mask);
  126 }
  127 
  128 static void
  129 ar71xx_chip_device_start(uint32_t mask)
  130 {
  131         uint32_t reg;
  132 
  133         reg = ATH_READ_REG(AR71XX_RST_RESET);
  134         ATH_WRITE_REG(AR71XX_RST_RESET, reg & ~mask);
  135 }
  136 
  137 static int
  138 ar71xx_chip_device_stopped(uint32_t mask)
  139 {
  140         uint32_t reg;
  141 
  142         reg = ATH_READ_REG(AR71XX_RST_RESET);
  143         return ((reg & mask) == mask);
  144 }
  145 
  146 void
  147 ar71xx_chip_set_mii_speed(uint32_t unit, uint32_t speed)
  148 {
  149         uint32_t val, reg, ctrl;
  150 
  151         switch (unit) {
  152         case 0:
  153                 reg = AR71XX_MII0_CTRL;
  154                 break;
  155         case 1:
  156                 reg = AR71XX_MII1_CTRL;
  157                 break;
  158         default:
  159                 printf("%s: invalid MII unit set for arge unit: %d\n",
  160                     __func__, unit);
  161                 return;
  162         }
  163 
  164         switch (speed) {
  165         case 10:
  166                 ctrl = MII_CTRL_SPEED_10;
  167                 break;
  168         case 100:
  169                 ctrl = MII_CTRL_SPEED_100;
  170                 break;
  171         case 1000:
  172                 ctrl = MII_CTRL_SPEED_1000;
  173                 break;
  174         default:
  175                 printf("%s: invalid MII speed (%d) set for arge unit: %d\n",
  176                     __func__, speed, unit);
  177                 return;
  178         }
  179 
  180         val = ATH_READ_REG(reg);
  181         val &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT);
  182         val |= (ctrl & MII_CTRL_SPEED_MASK) << MII_CTRL_SPEED_SHIFT;
  183         ATH_WRITE_REG(reg, val);
  184 }
  185 
  186 void
  187 ar71xx_chip_set_mii_if(uint32_t unit, uint32_t mii_mode)
  188 {
  189         uint32_t val, reg, mii_if;
  190 
  191         switch (unit) {
  192         case 0:
  193                 reg = AR71XX_MII0_CTRL;
  194                 if (mii_mode == AR71XX_MII_MODE_GMII)
  195                         mii_if = MII0_CTRL_IF_GMII;
  196                 else if (mii_mode == AR71XX_MII_MODE_MII)
  197                         mii_if = MII0_CTRL_IF_MII;
  198                 else if (mii_mode == AR71XX_MII_MODE_RGMII)
  199                         mii_if = MII0_CTRL_IF_RGMII;
  200                 else if (mii_mode == AR71XX_MII_MODE_RMII)
  201                         mii_if = MII0_CTRL_IF_RMII;
  202                 else {
  203                         printf("%s: invalid MII mode (%d) for unit %d\n",
  204                             __func__, mii_mode, unit);
  205                         return;
  206                 }
  207                 break;
  208         case 1:
  209                 reg = AR71XX_MII1_CTRL;
  210                 if (mii_mode == AR71XX_MII_MODE_RGMII)
  211                         mii_if = MII1_CTRL_IF_RGMII;
  212                 else if (mii_mode == AR71XX_MII_MODE_RMII)
  213                         mii_if = MII1_CTRL_IF_RMII;
  214                 else {
  215                         printf("%s: invalid MII mode (%d) for unit %d\n",
  216                             __func__, mii_mode, unit);
  217                         return;
  218                 }
  219                 break;
  220         default:
  221                 printf("%s: invalid MII unit set for arge unit: %d\n",
  222                     __func__, unit);
  223                 return;
  224         }
  225 
  226         val = ATH_READ_REG(reg);
  227         val &= ~(MII_CTRL_IF_MASK << MII_CTRL_IF_SHIFT);
  228         val |= (mii_if & MII_CTRL_IF_MASK) << MII_CTRL_IF_SHIFT;
  229         ATH_WRITE_REG(reg, val);
  230 }
  231 
  232 /* Speed is either 10, 100 or 1000 */
  233 static void
  234 ar71xx_chip_set_pll_ge(int unit, int speed, uint32_t pll)
  235 {
  236 
  237         switch (unit) {
  238         case 0:
  239                 ar71xx_write_pll(AR71XX_PLL_SEC_CONFIG,
  240                     AR71XX_PLL_ETH_INT0_CLK, pll,
  241                     AR71XX_PLL_ETH0_SHIFT);
  242                 break;
  243         case 1:
  244                 ar71xx_write_pll(AR71XX_PLL_SEC_CONFIG,
  245                     AR71XX_PLL_ETH_INT1_CLK, pll,
  246                     AR71XX_PLL_ETH1_SHIFT);
  247                 break;
  248         default:
  249                 printf("%s: invalid PLL set for arge unit: %d\n",
  250                     __func__, unit);
  251                 return;
  252         }
  253 }
  254 
  255 static void
  256 ar71xx_chip_ddr_flush_ge(int unit)
  257 {
  258 
  259         switch (unit) {
  260         case 0:
  261                 ar71xx_ddr_flush(AR71XX_WB_FLUSH_GE0);
  262                 break;
  263         case 1:
  264                 ar71xx_ddr_flush(AR71XX_WB_FLUSH_GE1);
  265                 break;
  266         default:
  267                 printf("%s: invalid DDR flush for arge unit: %d\n",
  268                     __func__, unit);
  269                 return;
  270         }
  271 }
  272 
  273 static void
  274 ar71xx_chip_ddr_flush_ip2(void)
  275 {
  276         ar71xx_ddr_flush(AR71XX_WB_FLUSH_PCI);
  277 }
  278 
  279 static uint32_t
  280 ar71xx_chip_get_eth_pll(unsigned int mac, int speed)
  281 {
  282         uint32_t pll;
  283 
  284         switch (speed) {
  285         case 10:
  286                 pll = PLL_ETH_INT_CLK_10;
  287                 break;
  288         case 100:
  289                 pll = PLL_ETH_INT_CLK_100;
  290                 break;
  291         case 1000:
  292                 pll = PLL_ETH_INT_CLK_1000;
  293                 break;
  294         default:
  295                 printf("%s%d: invalid speed %d\n", __func__, mac, speed);
  296                 pll = 0;
  297         }
  298 
  299         return (pll);
  300 }
  301 
  302 static void
  303 ar71xx_chip_init_usb_peripheral(void)
  304 {
  305 
  306         ar71xx_device_stop(RST_RESET_USB_OHCI_DLL |
  307             RST_RESET_USB_HOST | RST_RESET_USB_PHY);
  308         DELAY(1000);
  309 
  310         ar71xx_device_start(RST_RESET_USB_OHCI_DLL |
  311             RST_RESET_USB_HOST | RST_RESET_USB_PHY);
  312         DELAY(1000);
  313 
  314         ATH_WRITE_REG(AR71XX_USB_CTRL_CONFIG,
  315             USB_CTRL_CONFIG_OHCI_DES_SWAP |
  316             USB_CTRL_CONFIG_OHCI_BUF_SWAP |
  317             USB_CTRL_CONFIG_EHCI_DES_SWAP |
  318             USB_CTRL_CONFIG_EHCI_BUF_SWAP);
  319 
  320         ATH_WRITE_REG(AR71XX_USB_CTRL_FLADJ,
  321             (32 << USB_CTRL_FLADJ_HOST_SHIFT) |
  322             (3 << USB_CTRL_FLADJ_A5_SHIFT));
  323 
  324         DELAY(1000);
  325 }
  326 
  327 struct ar71xx_cpu_def ar71xx_chip_def = {
  328         &ar71xx_chip_detect_mem_size,
  329         &ar71xx_chip_detect_sys_frequency,
  330         &ar71xx_chip_device_stop,
  331         &ar71xx_chip_device_start,
  332         &ar71xx_chip_device_stopped,
  333         &ar71xx_chip_set_pll_ge,
  334         &ar71xx_chip_set_mii_speed,
  335         &ar71xx_chip_set_mii_if,
  336         &ar71xx_chip_ddr_flush_ge,
  337         &ar71xx_chip_get_eth_pll,
  338         &ar71xx_chip_ddr_flush_ip2,
  339         &ar71xx_chip_init_usb_peripheral,
  340 };

Cache object: 169b859c836b82e855e79a5390767dff


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]


This page is part of the FreeBSD/Linux Linux Kernel Cross-Reference, and was automatically generated using a modified version of the LXR engine.