The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/mips/atheros/ar71xx_ehci.c

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
    3  *
    4  * Copyright (c) 2008 Sam Leffler.  All rights reserved.
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions
    8  * are met:
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  *
   15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   25  */
   26 
   27 /*
   28  * AR71XX attachment driver for the USB Enhanced Host Controller.
   29  */
   30 
   31 #include <sys/cdefs.h>
   32 __FBSDID("$FreeBSD: stable/12/sys/mips/atheros/ar71xx_ehci.c 326259 2017-11-27 15:07:26Z pfg $");
   33 
   34 #include "opt_bus.h"
   35 
   36 #include <sys/param.h>
   37 #include <sys/systm.h>
   38 #include <sys/bus.h>
   39 #include <sys/rman.h>
   40 #include <sys/condvar.h>
   41 #include <sys/kernel.h>
   42 #include <sys/module.h>
   43 
   44 #include <machine/bus.h>
   45 
   46 #include <dev/usb/usb.h>
   47 #include <dev/usb/usbdi.h>
   48 
   49 #include <dev/usb/usb_core.h>
   50 #include <dev/usb/usb_busdma.h>
   51 #include <dev/usb/usb_process.h>
   52 #include <dev/usb/usb_util.h>
   53 
   54 #include <dev/usb/usb_controller.h>
   55 #include <dev/usb/usb_bus.h>
   56 #include <dev/usb/controller/ehci.h>
   57 #include <dev/usb/controller/ehcireg.h>
   58 
   59 #include <mips/atheros/ar71xx_setup.h>
   60 #include <mips/atheros/ar71xxreg.h> /* for stuff in ar71xx_cpudef.h */
   61 #include <mips/atheros/ar71xx_cpudef.h>
   62 #include <mips/atheros/ar71xx_bus_space_reversed.h>
   63 
   64 #define EHCI_HC_DEVSTR          "AR71XX Integrated USB 2.0 controller"
   65 
   66 #define EHCI_USBMODE            0x68    /* USB Device mode register */
   67 #define EHCI_UM_CM              0x00000003      /* R/WO Controller Mode */
   68 #define EHCI_UM_CM_HOST         0x3     /* Host Controller */
   69 
   70 struct ar71xx_ehci_softc {
   71         ehci_softc_t            base;   /* storage for EHCI code */
   72 };
   73 
   74 static device_attach_t ar71xx_ehci_attach;
   75 static device_detach_t ar71xx_ehci_detach;
   76 
   77 bs_r_1_proto(reversed);
   78 bs_w_1_proto(reversed);
   79 
   80 static void
   81 ar71xx_ehci_post_reset(struct ehci_softc *ehci_softc)
   82 {
   83         uint32_t usbmode;
   84 
   85         /* Force HOST mode */
   86         usbmode = EOREAD4(ehci_softc, EHCI_USBMODE_NOLPM);
   87         usbmode &= ~EHCI_UM_CM;
   88         usbmode |= EHCI_UM_CM_HOST;
   89         EOWRITE4(ehci_softc, EHCI_USBMODE_NOLPM, usbmode);
   90 }
   91 
   92 static int
   93 ar71xx_ehci_probe(device_t self)
   94 {
   95 
   96         device_set_desc(self, EHCI_HC_DEVSTR);
   97 
   98         return (BUS_PROBE_NOWILDCARD);
   99 }
  100 
  101 static void
  102 ar71xx_ehci_intr(void *arg)
  103 {
  104 
  105         /* XXX TODO: should really see if this was our interrupt.. */
  106         ar71xx_device_flush_ddr(AR71XX_CPU_DDR_FLUSH_USB);
  107         ehci_interrupt(arg);
  108 }
  109 
  110 static int
  111 ar71xx_ehci_attach(device_t self)
  112 {
  113         struct ar71xx_ehci_softc *isc = device_get_softc(self);
  114         ehci_softc_t *sc = &isc->base;
  115         int err;
  116         int rid;
  117 
  118         /* initialise some bus fields */
  119         sc->sc_bus.parent = self;
  120         sc->sc_bus.devices = sc->sc_devices;
  121         sc->sc_bus.devices_max = EHCI_MAX_DEVICES;
  122         sc->sc_bus.dma_bits = 32;
  123 
  124         /* get all DMA memory */
  125         if (usb_bus_mem_alloc_all(&sc->sc_bus,
  126             USB_GET_DMA_TAG(self), &ehci_iterate_hw_softc)) {
  127                 return (ENOMEM);
  128         }
  129 
  130         sc->sc_bus.usbrev = USB_REV_2_0;
  131 
  132         /* NB: hints fix the memory location and irq */
  133 
  134         rid = 0;
  135         sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
  136         if (!sc->sc_io_res) {
  137                 device_printf(self, "Could not map memory\n");
  138                 goto error;
  139         }
  140 
  141         /*
  142          * Craft special resource for bus space ops that handle
  143          * byte-alignment of non-word addresses.  
  144          */
  145         sc->sc_io_tag = ar71xx_bus_space_reversed;
  146         sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res);
  147         sc->sc_io_size = rman_get_size(sc->sc_io_res);
  148 
  149         rid = 0;
  150         sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid,
  151             RF_ACTIVE | RF_SHAREABLE);
  152         if (sc->sc_irq_res == NULL) {
  153                 device_printf(self, "Could not allocate irq\n");
  154                 goto error;
  155         }
  156         sc->sc_bus.bdev = device_add_child(self, "usbus", -1);
  157         if (!sc->sc_bus.bdev) {
  158                 device_printf(self, "Could not add USB device\n");
  159                 goto error;
  160         }
  161         device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
  162         device_set_desc(sc->sc_bus.bdev, EHCI_HC_DEVSTR);
  163 
  164         sprintf(sc->sc_vendor, "Atheros");
  165 
  166         err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
  167             NULL, ar71xx_ehci_intr, sc, &sc->sc_intr_hdl);
  168         if (err) {
  169                 device_printf(self, "Could not setup irq, %d\n", err);
  170                 sc->sc_intr_hdl = NULL;
  171                 goto error;
  172         }
  173 
  174         /*
  175          * Arrange to force Host mode, select big-endian byte alignment,
  176          * and arrange to not terminate reset operations (the adapter
  177          * will ignore it if we do but might as well save a reg write).
  178          * Also, the controller has an embedded Transaction Translator
  179          * which means port speed must be read from the Port Status
  180          * register following a port enable.
  181          */
  182         sc->sc_flags = 0;
  183         sc->sc_vendor_post_reset = ar71xx_ehci_post_reset;
  184 
  185         switch (ar71xx_soc) {
  186                 case AR71XX_SOC_AR7241:
  187                 case AR71XX_SOC_AR7242:
  188                 case AR71XX_SOC_AR9130:
  189                 case AR71XX_SOC_AR9132:
  190                 case AR71XX_SOC_AR9330:
  191                 case AR71XX_SOC_AR9331:
  192                 case AR71XX_SOC_AR9341:
  193                 case AR71XX_SOC_AR9342:
  194                 case AR71XX_SOC_AR9344:
  195                 case AR71XX_SOC_QCA9533:
  196                 case AR71XX_SOC_QCA9533_V2:
  197                 case AR71XX_SOC_QCA9556:
  198                 case AR71XX_SOC_QCA9558:
  199                         sc->sc_flags |= EHCI_SCFLG_TT | EHCI_SCFLG_NORESTERM;
  200                         sc->sc_vendor_get_port_speed =
  201                             ehci_get_port_speed_portsc;
  202                         break;
  203                 default:
  204                         /* fallthrough */
  205                         break;
  206         }
  207 
  208         /*
  209          * ehci_reset() needs the correct offset to access the host controller
  210          * registers. The AR724x/AR913x offsets aren't 0.
  211         */
  212         sc->sc_offs = EHCI_CAPLENGTH(EREAD4(sc, EHCI_CAPLEN_HCIVERSION));
  213 
  214         (void) ehci_reset(sc);
  215 
  216         err = ehci_init(sc);
  217         if (!err) {
  218                 err = device_probe_and_attach(sc->sc_bus.bdev);
  219         }
  220         if (err) {
  221                 device_printf(self, "USB init failed err=%d\n", err);
  222                 goto error;
  223         }
  224         return (0);
  225 
  226 error:
  227         ar71xx_ehci_detach(self);
  228         return (ENXIO);
  229 }
  230 
  231 static int
  232 ar71xx_ehci_detach(device_t self)
  233 {
  234         struct ar71xx_ehci_softc *isc = device_get_softc(self);
  235         ehci_softc_t *sc = &isc->base;
  236         int err;
  237 
  238         /* during module unload there are lots of children leftover */
  239         device_delete_children(self);
  240 
  241         if (sc->sc_irq_res && sc->sc_intr_hdl) {
  242                 /*
  243                  * only call ehci_detach() after ehci_init()
  244                  */
  245                 ehci_detach(sc);
  246 
  247                 err = bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl);
  248 
  249                 if (err)
  250                         /* XXX or should we panic? */
  251                         device_printf(self, "Could not tear down irq, %d\n",
  252                             err);
  253                 sc->sc_intr_hdl = NULL;
  254         }
  255 
  256         if (sc->sc_irq_res) {
  257                 bus_release_resource(self, SYS_RES_IRQ, 0, sc->sc_irq_res);
  258                 sc->sc_irq_res = NULL;
  259         }
  260         if (sc->sc_io_res) {
  261                 bus_release_resource(self, SYS_RES_MEMORY, 0,
  262                     sc->sc_io_res);
  263                 sc->sc_io_res = NULL;
  264         }
  265         usb_bus_mem_free_all(&sc->sc_bus, &ehci_iterate_hw_softc);
  266 
  267         return (0);
  268 }
  269 
  270 static device_method_t ehci_methods[] = {
  271         /* Device interface */
  272         DEVMETHOD(device_probe, ar71xx_ehci_probe),
  273         DEVMETHOD(device_attach, ar71xx_ehci_attach),
  274         DEVMETHOD(device_detach, ar71xx_ehci_detach),
  275         DEVMETHOD(device_suspend, bus_generic_suspend),
  276         DEVMETHOD(device_resume, bus_generic_resume),
  277         DEVMETHOD(device_shutdown, bus_generic_shutdown),
  278 
  279         DEVMETHOD_END
  280 };
  281 
  282 static driver_t ehci_driver = {
  283         .name = "ehci",
  284         .methods = ehci_methods,
  285         .size = sizeof(struct ar71xx_ehci_softc),
  286 };
  287 
  288 static devclass_t ehci_devclass;
  289 
  290 DRIVER_MODULE(ehci, nexus, ehci_driver, ehci_devclass, 0, 0);
  291 DRIVER_MODULE(ehci, apb, ehci_driver, ehci_devclass, 0, 0);
  292 
  293 MODULE_DEPEND(ehci, usb, 1, 1, 1);

Cache object: 03ec6ffa639c2c40818366e5c5b6f399


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