The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/mips/atheros/ar71xx_gpio.c

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
    3  *
    4  * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo@FreeBSD.org>
    5  * Copyright (c) 2009, Luiz Otavio O Souza. 
    6  * All rights reserved.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice unmodified, this list of conditions, and the following
   13  *    disclaimer.
   14  * 2. Redistributions in binary form must reproduce the above copyright
   15  *    notice, this list of conditions and the following disclaimer in the
   16  *    documentation and/or other materials provided with the distribution.
   17  *
   18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   28  * SUCH DAMAGE.
   29  */
   30 
   31 /*
   32  * GPIO driver for AR71xx 
   33  */
   34 
   35 #include <sys/cdefs.h>
   36 __FBSDID("$FreeBSD: stable/12/sys/mips/atheros/ar71xx_gpio.c 326259 2017-11-27 15:07:26Z pfg $");
   37 
   38 #include <sys/param.h>
   39 #include <sys/systm.h>
   40 #include <sys/bus.h>
   41 
   42 #include <sys/kernel.h>
   43 #include <sys/module.h>
   44 #include <sys/rman.h>
   45 #include <sys/lock.h>
   46 #include <sys/malloc.h>
   47 #include <sys/mutex.h>
   48 #include <sys/gpio.h>
   49 
   50 #include <machine/bus.h>
   51 #include <machine/resource.h>
   52 #include <mips/atheros/ar71xxreg.h>
   53 #include <mips/atheros/ar71xx_setup.h>
   54 #include <mips/atheros/ar71xx_cpudef.h>
   55 #include <mips/atheros/ar71xx_gpiovar.h>
   56 #include <dev/gpio/gpiobusvar.h>
   57 #include <mips/atheros/ar933xreg.h>
   58 #include <mips/atheros/ar934xreg.h>
   59 #include <mips/atheros/qca953xreg.h>
   60 #include <mips/atheros/qca955xreg.h>
   61 
   62 #include "gpio_if.h"
   63 
   64 #define DEFAULT_CAPS    (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)
   65 
   66 /*
   67  * Helpers
   68  */
   69 static void ar71xx_gpio_function_enable(struct ar71xx_gpio_softc *sc, 
   70     uint32_t mask);
   71 static void ar71xx_gpio_function_disable(struct ar71xx_gpio_softc *sc, 
   72     uint32_t mask);
   73 static void ar71xx_gpio_pin_configure(struct ar71xx_gpio_softc *sc, 
   74     struct gpio_pin *pin, uint32_t flags);
   75 
   76 /*
   77  * Driver stuff
   78  */
   79 static int ar71xx_gpio_probe(device_t dev);
   80 static int ar71xx_gpio_attach(device_t dev);
   81 static int ar71xx_gpio_detach(device_t dev);
   82 static int ar71xx_gpio_filter(void *arg);
   83 static void ar71xx_gpio_intr(void *arg);
   84 
   85 /*
   86  * GPIO interface
   87  */
   88 static device_t ar71xx_gpio_get_bus(device_t);
   89 static int ar71xx_gpio_pin_max(device_t dev, int *maxpin);
   90 static int ar71xx_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps);
   91 static int ar71xx_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t
   92     *flags);
   93 static int ar71xx_gpio_pin_getname(device_t dev, uint32_t pin, char *name);
   94 static int ar71xx_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags);
   95 static int ar71xx_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value);
   96 static int ar71xx_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val);
   97 static int ar71xx_gpio_pin_toggle(device_t dev, uint32_t pin);
   98 
   99 /*
  100  * Enable/disable the GPIO function control space.
  101  *
  102  * This is primarily for the AR71xx, which has SPI CS1/CS2, UART, SLIC, I2S
  103  * as GPIO pin options.
  104  */
  105 static void
  106 ar71xx_gpio_function_enable(struct ar71xx_gpio_softc *sc, uint32_t mask)
  107 {
  108 
  109         /*
  110          * XXX TODO: refactor this out into a per-chipset method.
  111          */
  112         if (ar71xx_soc == AR71XX_SOC_AR9341 ||
  113             ar71xx_soc == AR71XX_SOC_AR9342 ||
  114             ar71xx_soc == AR71XX_SOC_AR9344 ||
  115             ar71xx_soc == AR71XX_SOC_QCA9533 ||
  116             ar71xx_soc == AR71XX_SOC_QCA9533_V2 ||
  117             ar71xx_soc == AR71XX_SOC_QCA9556 ||
  118             ar71xx_soc == AR71XX_SOC_QCA9558)
  119                 GPIO_SET_BITS(sc, AR934X_GPIO_REG_FUNC, mask);
  120         else
  121                 GPIO_SET_BITS(sc, AR71XX_GPIO_FUNCTION, mask);
  122 }
  123 
  124 static void
  125 ar71xx_gpio_function_disable(struct ar71xx_gpio_softc *sc, uint32_t mask)
  126 {
  127 
  128         /*
  129          * XXX TODO: refactor this out into a per-chipset method.
  130          */
  131         if (ar71xx_soc == AR71XX_SOC_AR9341 ||
  132             ar71xx_soc == AR71XX_SOC_AR9342 ||
  133             ar71xx_soc == AR71XX_SOC_AR9344 ||
  134             ar71xx_soc == AR71XX_SOC_QCA9533 ||
  135             ar71xx_soc == AR71XX_SOC_QCA9533_V2 ||
  136             ar71xx_soc == AR71XX_SOC_QCA9556 ||
  137             ar71xx_soc == AR71XX_SOC_QCA9558)
  138                 GPIO_CLEAR_BITS(sc, AR934X_GPIO_REG_FUNC, mask);
  139         else
  140                 GPIO_CLEAR_BITS(sc, AR71XX_GPIO_FUNCTION, mask);
  141 }
  142 
  143 /*
  144  * On most platforms, GPIO_OE is a bitmap where the bit set
  145  * means "enable output."
  146  *
  147  * On AR934x and QCA953x, it's the opposite - the bit set means
  148  * "input enable".
  149  */
  150 static int
  151 ar71xx_gpio_oe_is_high(void)
  152 {
  153         switch (ar71xx_soc) {
  154         case AR71XX_SOC_AR9344:
  155         case AR71XX_SOC_QCA9533:
  156         case AR71XX_SOC_QCA9533_V2:
  157                 return 0;
  158         default:
  159                 return 1;
  160         }
  161 }
  162 
  163 static void
  164 ar71xx_gpio_oe_set_output(struct ar71xx_gpio_softc *sc, int b)
  165 {
  166         uint32_t mask;
  167 
  168         mask = 1 << b;
  169 
  170         if (ar71xx_gpio_oe_is_high())
  171                 GPIO_SET_BITS(sc, AR71XX_GPIO_OE, mask);
  172         else
  173                 GPIO_CLEAR_BITS(sc, AR71XX_GPIO_OE, mask);
  174 }
  175 
  176 static void
  177 ar71xx_gpio_oe_set_input(struct ar71xx_gpio_softc *sc, int b)
  178 {
  179         uint32_t mask;
  180 
  181         mask = 1 << b;
  182 
  183         if (ar71xx_gpio_oe_is_high())
  184                 GPIO_CLEAR_BITS(sc, AR71XX_GPIO_OE, mask);
  185         else
  186                 GPIO_SET_BITS(sc, AR71XX_GPIO_OE, mask);
  187 }
  188 
  189 static void
  190 ar71xx_gpio_pin_configure(struct ar71xx_gpio_softc *sc, struct gpio_pin *pin,
  191     unsigned int flags)
  192 {
  193 
  194         /*
  195          * Manage input/output
  196          */
  197         if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
  198                 pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT);
  199                 if (flags & GPIO_PIN_OUTPUT) {
  200                         pin->gp_flags |= GPIO_PIN_OUTPUT;
  201                         ar71xx_gpio_oe_set_output(sc, pin->gp_pin);
  202                 } else {
  203                         pin->gp_flags |= GPIO_PIN_INPUT;
  204                         ar71xx_gpio_oe_set_input(sc, pin->gp_pin);
  205                 }
  206         }
  207 }
  208 
  209 static device_t
  210 ar71xx_gpio_get_bus(device_t dev)
  211 {
  212         struct ar71xx_gpio_softc *sc;
  213 
  214         sc = device_get_softc(dev);
  215 
  216         return (sc->busdev);
  217 }
  218 
  219 static int
  220 ar71xx_gpio_pin_max(device_t dev, int *maxpin)
  221 {
  222 
  223         switch (ar71xx_soc) {
  224                 case AR71XX_SOC_AR9130:
  225                 case AR71XX_SOC_AR9132:
  226                         *maxpin = AR91XX_GPIO_PINS - 1;
  227                         break;
  228                 case AR71XX_SOC_AR7240:
  229                 case AR71XX_SOC_AR7241:
  230                 case AR71XX_SOC_AR7242:
  231                         *maxpin = AR724X_GPIO_PINS - 1;
  232                         break;
  233                 case AR71XX_SOC_AR9330:
  234                 case AR71XX_SOC_AR9331:
  235                         *maxpin = AR933X_GPIO_COUNT - 1;
  236                         break;
  237                 case AR71XX_SOC_AR9341:
  238                 case AR71XX_SOC_AR9342:
  239                 case AR71XX_SOC_AR9344:
  240                         *maxpin = AR934X_GPIO_COUNT - 1;
  241                         break;
  242                 case AR71XX_SOC_QCA9533:
  243                 case AR71XX_SOC_QCA9533_V2:
  244                         *maxpin = QCA953X_GPIO_COUNT - 1;
  245                         break;
  246                 case AR71XX_SOC_QCA9556:
  247                 case AR71XX_SOC_QCA9558:
  248                         *maxpin = QCA955X_GPIO_COUNT - 1;
  249                         break;
  250                 default:
  251                         *maxpin = AR71XX_GPIO_PINS - 1;
  252         }
  253         return (0);
  254 }
  255 
  256 static int
  257 ar71xx_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
  258 {
  259         struct ar71xx_gpio_softc *sc = device_get_softc(dev);
  260         int i;
  261 
  262         for (i = 0; i < sc->gpio_npins; i++) {
  263                 if (sc->gpio_pins[i].gp_pin == pin)
  264                         break;
  265         }
  266 
  267         if (i >= sc->gpio_npins)
  268                 return (EINVAL);
  269 
  270         GPIO_LOCK(sc);
  271         *caps = sc->gpio_pins[i].gp_caps;
  272         GPIO_UNLOCK(sc);
  273 
  274         return (0);
  275 }
  276 
  277 static int
  278 ar71xx_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
  279 {
  280         struct ar71xx_gpio_softc *sc = device_get_softc(dev);
  281         int i;
  282 
  283         for (i = 0; i < sc->gpio_npins; i++) {
  284                 if (sc->gpio_pins[i].gp_pin == pin)
  285                         break;
  286         }
  287 
  288         if (i >= sc->gpio_npins)
  289                 return (EINVAL);
  290 
  291         GPIO_LOCK(sc);
  292         *flags = sc->gpio_pins[i].gp_flags;
  293         GPIO_UNLOCK(sc);
  294 
  295         return (0);
  296 }
  297 
  298 static int
  299 ar71xx_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
  300 {
  301         struct ar71xx_gpio_softc *sc = device_get_softc(dev);
  302         int i;
  303 
  304         for (i = 0; i < sc->gpio_npins; i++) {
  305                 if (sc->gpio_pins[i].gp_pin == pin)
  306                         break;
  307         }
  308 
  309         if (i >= sc->gpio_npins)
  310                 return (EINVAL);
  311 
  312         GPIO_LOCK(sc);
  313         memcpy(name, sc->gpio_pins[i].gp_name, GPIOMAXNAME);
  314         GPIO_UNLOCK(sc);
  315 
  316         return (0);
  317 }
  318 
  319 static int
  320 ar71xx_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
  321 {
  322         int i;
  323         struct ar71xx_gpio_softc *sc = device_get_softc(dev);
  324 
  325         for (i = 0; i < sc->gpio_npins; i++) {
  326                 if (sc->gpio_pins[i].gp_pin == pin)
  327                         break;
  328         }
  329 
  330         if (i >= sc->gpio_npins)
  331                 return (EINVAL);
  332 
  333         ar71xx_gpio_pin_configure(sc, &sc->gpio_pins[i], flags);
  334 
  335         return (0);
  336 }
  337 
  338 static int
  339 ar71xx_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
  340 {
  341         struct ar71xx_gpio_softc *sc = device_get_softc(dev);
  342         int i;
  343 
  344         for (i = 0; i < sc->gpio_npins; i++) {
  345                 if (sc->gpio_pins[i].gp_pin == pin)
  346                         break;
  347         }
  348 
  349         if (i >= sc->gpio_npins)
  350                 return (EINVAL);
  351 
  352         if (value)
  353                 GPIO_WRITE(sc, AR71XX_GPIO_SET, (1 << pin));
  354         else
  355                 GPIO_WRITE(sc, AR71XX_GPIO_CLEAR, (1 << pin));
  356 
  357         return (0);
  358 }
  359 
  360 static int
  361 ar71xx_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
  362 {
  363         struct ar71xx_gpio_softc *sc = device_get_softc(dev);
  364         int i;
  365 
  366         for (i = 0; i < sc->gpio_npins; i++) {
  367                 if (sc->gpio_pins[i].gp_pin == pin)
  368                         break;
  369         }
  370 
  371         if (i >= sc->gpio_npins)
  372                 return (EINVAL);
  373 
  374         *val = (GPIO_READ(sc, AR71XX_GPIO_IN) & (1 << pin)) ? 1 : 0;
  375 
  376         return (0);
  377 }
  378 
  379 static int
  380 ar71xx_gpio_pin_toggle(device_t dev, uint32_t pin)
  381 {
  382         int res, i;
  383         struct ar71xx_gpio_softc *sc = device_get_softc(dev);
  384 
  385         for (i = 0; i < sc->gpio_npins; i++) {
  386                 if (sc->gpio_pins[i].gp_pin == pin)
  387                         break;
  388         }
  389 
  390         if (i >= sc->gpio_npins)
  391                 return (EINVAL);
  392 
  393         res = (GPIO_READ(sc, AR71XX_GPIO_IN) & (1 << pin)) ? 1 : 0;
  394         if (res)
  395                 GPIO_WRITE(sc, AR71XX_GPIO_CLEAR, (1 << pin));
  396         else
  397                 GPIO_WRITE(sc, AR71XX_GPIO_SET, (1 << pin));
  398 
  399         return (0);
  400 }
  401 
  402 static int
  403 ar71xx_gpio_filter(void *arg)
  404 {
  405 
  406         /* TODO: something useful */
  407         return (FILTER_STRAY);
  408 }
  409 
  410 
  411 
  412 static void
  413 ar71xx_gpio_intr(void *arg)
  414 {
  415         struct ar71xx_gpio_softc *sc = arg;
  416         GPIO_LOCK(sc);
  417         /* TODO: something useful */
  418         GPIO_UNLOCK(sc);
  419 }
  420 
  421 static int
  422 ar71xx_gpio_probe(device_t dev)
  423 {
  424 
  425         device_set_desc(dev, "Atheros AR71XX GPIO driver");
  426         return (0);
  427 }
  428 
  429 static int
  430 ar71xx_gpio_attach(device_t dev)
  431 {
  432         struct ar71xx_gpio_softc *sc = device_get_softc(dev);
  433         int i, j, maxpin;
  434         int mask, pinon;
  435         uint32_t oe;
  436 
  437         KASSERT((device_get_unit(dev) == 0),
  438             ("ar71xx_gpio: Only one gpio module supported"));
  439 
  440         mtx_init(&sc->gpio_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
  441 
  442         /* Map control/status registers. */
  443         sc->gpio_mem_rid = 0;
  444         sc->gpio_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
  445             &sc->gpio_mem_rid, RF_ACTIVE);
  446 
  447         if (sc->gpio_mem_res == NULL) {
  448                 device_printf(dev, "couldn't map memory\n");
  449                 ar71xx_gpio_detach(dev);
  450                 return (ENXIO);
  451         }
  452 
  453         if ((sc->gpio_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 
  454             &sc->gpio_irq_rid, RF_SHAREABLE | RF_ACTIVE)) == NULL) {
  455                 device_printf(dev, "unable to allocate IRQ resource\n");
  456                 ar71xx_gpio_detach(dev);
  457                 return (ENXIO);
  458         }
  459 
  460         if ((bus_setup_intr(dev, sc->gpio_irq_res, INTR_TYPE_MISC, 
  461             ar71xx_gpio_filter, ar71xx_gpio_intr, sc, &sc->gpio_ih))) {
  462                 device_printf(dev,
  463                     "WARNING: unable to register interrupt handler\n");
  464                 ar71xx_gpio_detach(dev);
  465                 return (ENXIO);
  466         }
  467 
  468         sc->dev = dev;
  469 
  470         /* Enable function bits that are required */
  471         if (resource_int_value(device_get_name(dev), device_get_unit(dev),
  472             "function_set", &mask) == 0) {
  473                 device_printf(dev, "function_set: 0x%x\n", mask);
  474                 ar71xx_gpio_function_enable(sc, mask);
  475         }
  476         /* Disable function bits that are required */
  477         if (resource_int_value(device_get_name(dev), device_get_unit(dev),
  478             "function_clear", &mask) == 0) {
  479                 device_printf(dev, "function_clear: 0x%x\n", mask);
  480                 ar71xx_gpio_function_disable(sc, mask);
  481         }
  482 
  483         /* Disable interrupts for all pins. */
  484         GPIO_WRITE(sc, AR71XX_GPIO_INT_MASK, 0);
  485 
  486         /* Initialise all pins specified in the mask, up to the pin count */
  487         (void) ar71xx_gpio_pin_max(dev, &maxpin);
  488         if (resource_int_value(device_get_name(dev), device_get_unit(dev),
  489             "pinmask", &mask) != 0)
  490                 mask = 0;
  491         if (resource_int_value(device_get_name(dev), device_get_unit(dev),
  492             "pinon", &pinon) != 0)
  493                 pinon = 0;
  494         device_printf(dev, "gpio pinmask=0x%x\n", mask);
  495         for (j = 0; j <= maxpin; j++) {
  496                 if ((mask & (1 << j)) == 0)
  497                         continue;
  498                 sc->gpio_npins++;
  499         }
  500         /* Iniatilize the GPIO pins, keep the loader settings. */
  501         oe = GPIO_READ(sc, AR71XX_GPIO_OE);
  502         /*
  503          * For AR934x and QCA953x, the meaning of oe is inverted;
  504          * so flip it the right way around so we can parse the GPIO
  505          * state.
  506          */
  507         if (!ar71xx_gpio_oe_is_high())
  508                 oe = ~oe;
  509 
  510         sc->gpio_pins = malloc(sizeof(*sc->gpio_pins) * sc->gpio_npins,
  511             M_DEVBUF, M_WAITOK | M_ZERO);
  512         for (i = 0, j = 0; j <= maxpin; j++) {
  513                 if ((mask & (1 << j)) == 0)
  514                         continue;
  515                 snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME,
  516                     "pin %d", j);
  517                 sc->gpio_pins[i].gp_pin = j;
  518                 sc->gpio_pins[i].gp_caps = DEFAULT_CAPS;
  519                 if (oe & (1 << j))
  520                         sc->gpio_pins[i].gp_flags = GPIO_PIN_OUTPUT;
  521                 else
  522                         sc->gpio_pins[i].gp_flags = GPIO_PIN_INPUT;
  523                 i++;
  524         }
  525 
  526         /* Turn on the hinted pins. */
  527         for (i = 0; i < sc->gpio_npins; i++) {
  528                 j = sc->gpio_pins[i].gp_pin;
  529                 if ((pinon & (1 << j)) != 0) {
  530                         ar71xx_gpio_pin_setflags(dev, j, GPIO_PIN_OUTPUT);
  531                         ar71xx_gpio_pin_set(dev, j, 1);
  532                 }
  533         }
  534 
  535         /*
  536          * Search through the function hints, in case there's some
  537          * overrides such as LNA control.
  538          *
  539          * hint.gpio.X.func.<pin>.gpiofunc=<func value>
  540          * hint.gpio.X.func.<pin>.gpiomode=1 (for output, default low)
  541          */
  542         for (i = 0; i <= maxpin; i++) {
  543                 char buf[32];
  544                 int gpiofunc, gpiomode;
  545 
  546                 snprintf(buf, 32, "func.%d.gpiofunc", i);
  547                 if (resource_int_value(device_get_name(dev),
  548                     device_get_unit(dev),
  549                     buf,
  550                     &gpiofunc) != 0)
  551                         continue;
  552                 /* Get the mode too */
  553                 snprintf(buf, 32, "func.%d.gpiomode", i);
  554                 if (resource_int_value(device_get_name(dev),
  555                     device_get_unit(dev),
  556                     buf,
  557                     &gpiomode) != 0)
  558                         continue;
  559 
  560                 /* We only handle mode=1 for now */
  561                 if (gpiomode != 1)
  562                         continue;
  563 
  564                 device_printf(dev, "%s: GPIO %d: func=%d, mode=%d\n",
  565                     __func__,
  566                     i,
  567                     gpiofunc,
  568                     gpiomode);
  569 
  570                 /* Set pin value = 0, so it stays low by default */
  571                 oe = GPIO_READ(sc, AR71XX_GPIO_OUT);
  572                 oe &= ~ (1 << i);
  573                 GPIO_WRITE(sc, AR71XX_GPIO_OUT, oe);
  574 
  575                 /* Set output */
  576                 ar71xx_gpio_oe_set_output(sc, i);
  577 
  578                 /* Finally: Set the output config */
  579                 ar71xx_gpio_ouput_configure(i, gpiofunc);
  580         }
  581 
  582         sc->busdev = gpiobus_attach_bus(dev);
  583         if (sc->busdev == NULL) {
  584                 ar71xx_gpio_detach(dev);
  585                 return (ENXIO);
  586         }
  587 
  588         return (0);
  589 }
  590 
  591 static int
  592 ar71xx_gpio_detach(device_t dev)
  593 {
  594         struct ar71xx_gpio_softc *sc = device_get_softc(dev);
  595 
  596         KASSERT(mtx_initialized(&sc->gpio_mtx), ("gpio mutex not initialized"));
  597 
  598         gpiobus_detach_bus(dev);
  599         if (sc->gpio_ih)
  600                 bus_teardown_intr(dev, sc->gpio_irq_res, sc->gpio_ih);
  601         if (sc->gpio_irq_res)
  602                 bus_release_resource(dev, SYS_RES_IRQ, sc->gpio_irq_rid,
  603                     sc->gpio_irq_res);
  604         if (sc->gpio_mem_res)
  605                 bus_release_resource(dev, SYS_RES_MEMORY, sc->gpio_mem_rid,
  606                     sc->gpio_mem_res);
  607         if (sc->gpio_pins)
  608                 free(sc->gpio_pins, M_DEVBUF);
  609         mtx_destroy(&sc->gpio_mtx);
  610 
  611         return(0);
  612 }
  613 
  614 static device_method_t ar71xx_gpio_methods[] = {
  615         DEVMETHOD(device_probe, ar71xx_gpio_probe),
  616         DEVMETHOD(device_attach, ar71xx_gpio_attach),
  617         DEVMETHOD(device_detach, ar71xx_gpio_detach),
  618 
  619         /* GPIO protocol */
  620         DEVMETHOD(gpio_get_bus, ar71xx_gpio_get_bus),
  621         DEVMETHOD(gpio_pin_max, ar71xx_gpio_pin_max),
  622         DEVMETHOD(gpio_pin_getname, ar71xx_gpio_pin_getname),
  623         DEVMETHOD(gpio_pin_getflags, ar71xx_gpio_pin_getflags),
  624         DEVMETHOD(gpio_pin_getcaps, ar71xx_gpio_pin_getcaps),
  625         DEVMETHOD(gpio_pin_setflags, ar71xx_gpio_pin_setflags),
  626         DEVMETHOD(gpio_pin_get, ar71xx_gpio_pin_get),
  627         DEVMETHOD(gpio_pin_set, ar71xx_gpio_pin_set),
  628         DEVMETHOD(gpio_pin_toggle, ar71xx_gpio_pin_toggle),
  629         {0, 0},
  630 };
  631 
  632 static driver_t ar71xx_gpio_driver = {
  633         "gpio",
  634         ar71xx_gpio_methods,
  635         sizeof(struct ar71xx_gpio_softc),
  636 };
  637 static devclass_t ar71xx_gpio_devclass;
  638 
  639 DRIVER_MODULE(ar71xx_gpio, apb, ar71xx_gpio_driver, ar71xx_gpio_devclass, 0, 0);

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