The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/mips/atheros/ar71xx_gpiovar.h

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
    3  *
    4  * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo@FreeBSD.org>
    5  * Copyright (c) 2009, Luiz Otavio O Souza.
    6  * All rights reserved.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice unmodified, this list of conditions, and the following
   13  *    disclaimer.
   14  * 2. Redistributions in binary form must reproduce the above copyright
   15  *    notice, this list of conditions and the following disclaimer in the
   16  *    documentation and/or other materials provided with the distribution.
   17  *
   18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   28  * SUCH DAMAGE.
   29  *
   30  * $FreeBSD: stable/12/sys/mips/atheros/ar71xx_gpiovar.h 326259 2017-11-27 15:07:26Z pfg $
   31  *
   32  */
   33 
   34 #ifndef __AR71XX_GPIOVAR_H__
   35 #define __AR71XX_GPIOVAR_H__
   36 
   37 #define GPIO_LOCK(_sc)          mtx_lock(&(_sc)->gpio_mtx)
   38 #define GPIO_UNLOCK(_sc)        mtx_unlock(&(_sc)->gpio_mtx)
   39 #define GPIO_LOCK_ASSERT(_sc)   mtx_assert(&(_sc)->gpio_mtx, MA_OWNED)
   40 
   41 /*
   42  * register space access macros
   43  */
   44 #define GPIO_WRITE(sc, reg, val)        do {    \
   45                 bus_write_4(sc->gpio_mem_res, (reg), (val)); \
   46         } while (0)
   47 
   48 #define GPIO_READ(sc, reg)       bus_read_4(sc->gpio_mem_res, (reg))
   49 
   50 #define GPIO_SET_BITS(sc, reg, bits)    \
   51         GPIO_WRITE(sc, reg, GPIO_READ(sc, (reg)) | (bits))
   52 
   53 #define GPIO_CLEAR_BITS(sc, reg, bits)  \
   54         GPIO_WRITE(sc, reg, GPIO_READ(sc, (reg)) & ~(bits))
   55 
   56 #define AR71XX_GPIO_PINS        12
   57 #define AR724X_GPIO_PINS        18
   58 #define AR91XX_GPIO_PINS        22
   59 
   60 struct ar71xx_gpio_softc {
   61         device_t                dev;
   62         device_t                busdev;
   63         struct mtx              gpio_mtx;
   64         struct resource         *gpio_mem_res;
   65         int                     gpio_mem_rid;
   66         struct resource         *gpio_irq_res;
   67         int                     gpio_irq_rid;
   68         void                    *gpio_ih;
   69         int                     gpio_npins;
   70         struct gpio_pin         *gpio_pins;
   71 };
   72 
   73 #endif  /* __AR71XX_GPIOVAR_H__ */

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