ar71xx_pci.c

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    1 /*-
    2  * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo@FreeBSD.org>
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice unmodified, this list of conditions, and the following
   10  *    disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  *
   15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   25  * SUCH DAMAGE.
   26  */
   27 
   28 #include <sys/cdefs.h>
   29 __FBSDID("$FreeBSD$");
   30 
   31 #include "opt_ar71xx.h"
   32 
   33 #include <sys/param.h>
   34 #include <sys/systm.h>
   35 
   36 #include <sys/bus.h>
   37 #include <sys/interrupt.h>
   38 #include <sys/malloc.h>
   39 #include <sys/kernel.h>
   40 #include <sys/module.h>
   41 #include <sys/rman.h>
   42 #include <sys/lock.h>
   43 #include <sys/mutex.h>
   44 
   45 #include <vm/vm.h>
   46 #include <vm/pmap.h>
   47 #include <vm/vm_extern.h>
   48 
   49 #include <machine/bus.h>
   50 #include <machine/cpu.h>
   51 #include <machine/intr_machdep.h>
   52 
   53 #include <dev/pci/pcivar.h>
   54 #include <dev/pci/pcireg.h>
   55 
   56 #include <dev/pci/pcib_private.h>
   57 #include "pcib_if.h"
   58 
   59 #include <mips/atheros/ar71xxreg.h>
   60 #include <mips/atheros/ar71xx_pci_bus_space.h>
   61 
   62 #include <mips/atheros/ar71xx_cpudef.h>
   63 
   64 #ifdef  AR71XX_ATH_EEPROM
   65 #include <mips/atheros/ar71xx_fixup.h>
   66 #endif  /* AR71XX_ATH_EEPROM */
   67 
   68 #undef  AR71XX_PCI_DEBUG
   69 #ifdef  AR71XX_PCI_DEBUG
   70 #define dprintf printf
   71 #else
   72 #define dprintf(x, arg...)
   73 #endif
   74 
   75 struct mtx ar71xx_pci_mtx;
   76 MTX_SYSINIT(ar71xx_pci_mtx, &ar71xx_pci_mtx, "ar71xx PCI space mutex",
   77     MTX_SPIN);
   78 
   79 struct ar71xx_pci_softc {
   80         device_t                sc_dev;
   81 
   82         int                     sc_busno;
   83         int                     sc_baseslot;
   84         struct rman             sc_mem_rman;
   85         struct rman             sc_irq_rman;
   86 
   87         struct intr_event       *sc_eventstab[AR71XX_PCI_NIRQS];        
   88         mips_intrcnt_t          sc_intr_counter[AR71XX_PCI_NIRQS];      
   89         struct resource         *sc_irq;
   90         void                    *sc_ih;
   91 };
   92 
   93 static int ar71xx_pci_setup_intr(device_t, device_t, struct resource *, int, 
   94                     driver_filter_t *, driver_intr_t *, void *, void **);
   95 static int ar71xx_pci_teardown_intr(device_t, device_t, struct resource *,
   96                     void *);
   97 static int ar71xx_pci_intr(void *);
   98 
   99 static void
  100 ar71xx_pci_mask_irq(void *source)
  101 {
  102         uint32_t reg;
  103         unsigned int irq = (unsigned int)source;
  104 
  105         /* XXX is the PCI lock required here? */
  106         reg = ATH_READ_REG(AR71XX_PCI_INTR_MASK);
  107         /* flush */
  108         reg = ATH_READ_REG(AR71XX_PCI_INTR_MASK);
  109         ATH_WRITE_REG(AR71XX_PCI_INTR_MASK, reg & ~(1 << irq));
  110 }
  111 
  112 static void
  113 ar71xx_pci_unmask_irq(void *source)
  114 {
  115         uint32_t reg;
  116         unsigned int irq = (unsigned int)source;
  117 
  118         /* XXX is the PCI lock required here? */
  119         reg = ATH_READ_REG(AR71XX_PCI_INTR_MASK);
  120         ATH_WRITE_REG(AR71XX_PCI_INTR_MASK, reg | (1 << irq));
  121         /* flush */
  122         reg = ATH_READ_REG(AR71XX_PCI_INTR_MASK);
  123 }
  124 
  125 /*
  126  * get bitmask for bytes of interest:
  127  *   0 - we want this byte, 1 - ignore it. e.g: we read 1 byte
  128  *   from register 7. Bitmask would be: 0111
  129  */
  130 static uint32_t
  131 ar71xx_get_bytes_to_read(int reg, int bytes)
  132 {
  133         uint32_t bytes_to_read = 0;
  134 
  135         if ((bytes % 4) == 0)
  136                 bytes_to_read = 0;
  137         else if ((bytes % 4) == 1)
  138                 bytes_to_read = (~(1 << (reg % 4))) & 0xf;
  139         else if ((bytes % 4) == 2)
  140                 bytes_to_read = (~(3 << (reg % 4))) & 0xf;
  141         else
  142                 panic("%s: wrong combination", __func__);
  143 
  144         return (bytes_to_read);
  145 }
  146 
  147 static int
  148 ar71xx_pci_check_bus_error(void)
  149 {
  150         uint32_t error, addr, has_errors = 0;
  151 
  152         mtx_assert(&ar71xx_pci_mtx, MA_OWNED);
  153 
  154         error = ATH_READ_REG(AR71XX_PCI_ERROR) & 0x3;
  155         dprintf("%s: PCI error = %02x\n", __func__, error);
  156         if (error) {
  157                 addr = ATH_READ_REG(AR71XX_PCI_ERROR_ADDR);
  158 
  159                 /* Do not report it yet */
  160 #if 0
  161                 printf("PCI bus error %d at addr 0x%08x\n", error, addr);
  162 #endif
  163                 ATH_WRITE_REG(AR71XX_PCI_ERROR, error);
  164                 has_errors = 1;
  165         }
  166 
  167         error = ATH_READ_REG(AR71XX_PCI_AHB_ERROR) & 0x1;
  168         dprintf("%s: AHB error = %02x\n", __func__, error);
  169         if (error) {
  170                 addr = ATH_READ_REG(AR71XX_PCI_AHB_ERROR_ADDR);
  171                 /* Do not report it yet */
  172 #if 0
  173                 printf("AHB bus error %d at addr 0x%08x\n", error, addr);
  174 #endif
  175                 ATH_WRITE_REG(AR71XX_PCI_AHB_ERROR, error);
  176                 has_errors = 1;
  177         }
  178 
  179         return (has_errors);
  180 }
  181 
  182 static uint32_t
  183 ar71xx_pci_make_addr(int bus, int slot, int func, int reg)
  184 {
  185         if (bus == 0) {
  186                 return ((1 << slot) | (func << 8) | (reg & ~3));
  187         } else {
  188                 return ((bus << 16) | (slot << 11) | (func << 8)
  189                     | (reg  & ~3) | 1);
  190         }
  191 }
  192 
  193 static int
  194 ar71xx_pci_conf_setup(int bus, int slot, int func, int reg, int bytes,
  195     uint32_t cmd)
  196 {
  197         uint32_t addr = ar71xx_pci_make_addr(bus, slot, func, (reg & ~3));
  198 
  199         mtx_assert(&ar71xx_pci_mtx, MA_OWNED);
  200 
  201         cmd |= (ar71xx_get_bytes_to_read(reg, bytes) << 4);
  202         ATH_WRITE_REG(AR71XX_PCI_CONF_ADDR, addr);
  203         ATH_WRITE_REG(AR71XX_PCI_CONF_CMD, cmd);
  204 
  205         dprintf("%s: tag (%x, %x, %x) %d/%d addr=%08x, cmd=%08x\n", __func__, 
  206             bus, slot, func, reg, bytes, addr, cmd);
  207 
  208         return ar71xx_pci_check_bus_error();
  209 }
  210 
  211 static uint32_t
  212 ar71xx_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func,
  213     u_int reg, int bytes)
  214 {
  215         uint32_t data;
  216         uint32_t shift, mask;
  217 
  218         /* register access is 32-bit aligned */
  219         shift = (reg & 3) * 8;
  220 
  221         /* Create a mask based on the width, post-shift */
  222         if (bytes == 2)
  223                 mask = 0xffff;
  224         else if (bytes == 1)
  225                 mask = 0xff;
  226         else
  227                 mask = 0xffffffff;
  228 
  229         dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot, 
  230             func, reg, bytes);
  231 
  232         mtx_lock_spin(&ar71xx_pci_mtx);
  233          if (ar71xx_pci_conf_setup(bus, slot, func, reg, bytes, 
  234              PCI_CONF_CMD_READ) == 0)
  235                  data = ATH_READ_REG(AR71XX_PCI_CONF_READ_DATA);
  236          else
  237                  data = -1;
  238         mtx_unlock_spin(&ar71xx_pci_mtx);
  239 
  240         /* get request bytes from 32-bit word */
  241         data = (data >> shift) & mask;
  242 
  243         dprintf("%s: read 0x%x\n", __func__, data);
  244 
  245         return (data);
  246 }
  247 
  248 static void
  249 ar71xx_pci_local_write(device_t dev, uint32_t reg, uint32_t data, int bytes)
  250 {
  251         uint32_t cmd;
  252 
  253         dprintf("%s: local write reg %d(%d)\n", __func__, reg, bytes);
  254 
  255         data = data << (8*(reg % 4));
  256         cmd = PCI_LCONF_CMD_WRITE | (reg & ~3);
  257         cmd |= (ar71xx_get_bytes_to_read(reg, bytes) << 20);
  258         mtx_lock_spin(&ar71xx_pci_mtx);
  259         ATH_WRITE_REG(AR71XX_PCI_LCONF_CMD, cmd);
  260         ATH_WRITE_REG(AR71XX_PCI_LCONF_WRITE_DATA, data);
  261         mtx_unlock_spin(&ar71xx_pci_mtx);
  262 }
  263 
  264 static void
  265 ar71xx_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func,
  266     u_int reg, uint32_t data, int bytes)
  267 {
  268 
  269         dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot,
  270             func, reg, bytes);
  271 
  272         data = data << (8*(reg % 4));
  273         mtx_lock_spin(&ar71xx_pci_mtx);
  274          if (ar71xx_pci_conf_setup(bus, slot, func, reg, bytes,
  275              PCI_CONF_CMD_WRITE) == 0)
  276                  ATH_WRITE_REG(AR71XX_PCI_CONF_WRITE_DATA, data);
  277         mtx_unlock_spin(&ar71xx_pci_mtx);
  278 }
  279 
  280 #ifdef  AR71XX_ATH_EEPROM
  281 /*
  282  * Some embedded boards (eg AP94) have the MAC attached via PCI but they
  283  * don't have the MAC-attached EEPROM.  The register initialisation
  284  * values and calibration data are stored in the on-board flash.
  285  * This routine initialises the NIC via the EEPROM register contents
  286  * before the probe/attach routines get a go at things.
  287  */
  288 static void
  289 ar71xx_pci_fixup(device_t dev, u_int bus, u_int slot, u_int func,
  290     long flash_addr, int len)
  291 {
  292         uint16_t *cal_data = (uint16_t *) MIPS_PHYS_TO_KSEG1(flash_addr);
  293         uint32_t reg, val, bar0;
  294 
  295         if (bootverbose)
  296                 device_printf(dev, "%s: flash_addr=%lx, cal_data=%p\n",
  297                     __func__, flash_addr, cal_data);
  298 
  299         /* XXX check 0xa55a */
  300         /* Save bar(0) address - just to flush bar(0) (SoC WAR) ? */
  301         bar0 = ar71xx_pci_read_config(dev, bus, slot, func, PCIR_BAR(0), 4);
  302         ar71xx_pci_write_config(dev, bus, slot, func, PCIR_BAR(0),
  303             AR71XX_PCI_MEM_BASE, 4);
  304 
  305         val = ar71xx_pci_read_config(dev, bus, slot, func, PCIR_COMMAND, 2);
  306         val |= (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN);
  307         ar71xx_pci_write_config(dev, bus, slot, func, PCIR_COMMAND, val, 2); 
  308 
  309         cal_data += 3;
  310         while (*cal_data != 0xffff) {
  311                 reg = *cal_data++;
  312                 val = *cal_data++;
  313                 val |= (*cal_data++) << 16;
  314                 if (bootverbose)
  315                         printf("  reg: %x, val=%x\n", reg, val);
  316 
  317                 /* Write eeprom fixup data to device memory */
  318                 ATH_WRITE_REG(AR71XX_PCI_MEM_BASE + reg, val);
  319                 DELAY(100);
  320         }
  321 
  322         val = ar71xx_pci_read_config(dev, bus, slot, func, PCIR_COMMAND, 2);
  323         val &= ~(PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN);
  324         ar71xx_pci_write_config(dev, bus, slot, func, PCIR_COMMAND, val, 2);
  325 
  326         /* Write the saved bar(0) address */
  327         ar71xx_pci_write_config(dev, bus, slot, func, PCIR_BAR(0), bar0, 4);
  328 }
  329 
  330 static void
  331 ar71xx_pci_slot_fixup(device_t dev, u_int bus, u_int slot, u_int func)
  332 {
  333         long int flash_addr;
  334         char buf[64];
  335         int size;
  336 
  337         /*
  338          * Check whether the given slot has a hint to poke.
  339          */
  340         if (bootverbose)
  341         device_printf(dev, "%s: checking dev %s, %d/%d/%d\n",
  342             __func__, device_get_nameunit(dev), bus, slot, func);
  343 
  344         snprintf(buf, sizeof(buf), "bus.%d.%d.%d.ath_fixup_addr",
  345             bus, slot, func);
  346 
  347         if (resource_long_value(device_get_name(dev), device_get_unit(dev),
  348             buf, &flash_addr) == 0) {
  349                 snprintf(buf, sizeof(buf), "bus.%d.%d.%d.ath_fixup_size",
  350                     bus, slot, func);
  351                 if (resource_int_value(device_get_name(dev),
  352                     device_get_unit(dev), buf, &size) != 0) {
  353                         device_printf(dev,
  354                             "%s: missing hint '%s', aborting EEPROM\n",
  355                             __func__, buf);
  356                         return;
  357                 }
  358 
  359 
  360                 device_printf(dev, "found EEPROM at 0x%lx on %d.%d.%d\n",
  361                     flash_addr, bus, slot, func);
  362                 ar71xx_pci_fixup(dev, bus, slot, func, flash_addr, size);
  363                 ar71xx_pci_slot_create_eeprom_firmware(dev, bus, slot, func,
  364                     flash_addr, size);
  365         }
  366 }
  367 #endif  /* AR71XX_ATH_EEPROM */
  368 
  369 static int
  370 ar71xx_pci_probe(device_t dev)
  371 {
  372 
  373         return (BUS_PROBE_NOWILDCARD);
  374 }
  375 
  376 static int
  377 ar71xx_pci_attach(device_t dev)
  378 {
  379         int rid = 0;
  380         struct ar71xx_pci_softc *sc = device_get_softc(dev);
  381 
  382         sc->sc_mem_rman.rm_type = RMAN_ARRAY;
  383         sc->sc_mem_rman.rm_descr = "ar71xx PCI memory window";
  384         if (rman_init(&sc->sc_mem_rman) != 0 || 
  385             rman_manage_region(&sc->sc_mem_rman, AR71XX_PCI_MEM_BASE, 
  386                 AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1) != 0) {
  387                 panic("ar71xx_pci_attach: failed to set up I/O rman");
  388         }
  389 
  390         sc->sc_irq_rman.rm_type = RMAN_ARRAY;
  391         sc->sc_irq_rman.rm_descr = "ar71xx PCI IRQs";
  392         if (rman_init(&sc->sc_irq_rman) != 0 ||
  393             rman_manage_region(&sc->sc_irq_rman, AR71XX_PCI_IRQ_START, 
  394                 AR71XX_PCI_IRQ_END) != 0)
  395                 panic("ar71xx_pci_attach: failed to set up IRQ rman");
  396 
  397         /*
  398          * Check if there is a base slot hint. Otherwise use default value.
  399          */
  400         if (resource_int_value(device_get_name(dev),
  401             device_get_unit(dev), "baseslot", &sc->sc_baseslot) != 0) {
  402                 device_printf(dev,
  403                     "%s: missing hint '%s', default to AR71XX_PCI_BASE_SLOT\n",
  404                     __func__, "baseslot");
  405                 sc->sc_baseslot = AR71XX_PCI_BASE_SLOT;
  406         }
  407 
  408         ATH_WRITE_REG(AR71XX_PCI_INTR_STATUS, 0);
  409         ATH_WRITE_REG(AR71XX_PCI_INTR_MASK, 0);
  410 
  411         /* Hook up our interrupt handler. */
  412         if ((sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
  413             RF_SHAREABLE | RF_ACTIVE)) == NULL) {
  414                 device_printf(dev, "unable to allocate IRQ resource\n");
  415                 return ENXIO;
  416         }
  417 
  418         if ((bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_MISC,
  419                             ar71xx_pci_intr, NULL, sc, &sc->sc_ih))) {
  420                 device_printf(dev,
  421                     "WARNING: unable to register interrupt handler\n");
  422                 return ENXIO;
  423         }
  424 
  425         /* reset PCI core and PCI bus */
  426         ar71xx_device_stop(RST_RESET_PCI_CORE | RST_RESET_PCI_BUS);
  427         DELAY(100000);
  428 
  429         ar71xx_device_start(RST_RESET_PCI_CORE | RST_RESET_PCI_BUS);
  430         DELAY(100000);
  431 
  432         /* Init PCI windows */
  433         ATH_WRITE_REG(AR71XX_PCI_WINDOW0, PCI_WINDOW0_ADDR);
  434         ATH_WRITE_REG(AR71XX_PCI_WINDOW1, PCI_WINDOW1_ADDR);
  435         ATH_WRITE_REG(AR71XX_PCI_WINDOW2, PCI_WINDOW2_ADDR);
  436         ATH_WRITE_REG(AR71XX_PCI_WINDOW3, PCI_WINDOW3_ADDR);
  437         ATH_WRITE_REG(AR71XX_PCI_WINDOW4, PCI_WINDOW4_ADDR);
  438         ATH_WRITE_REG(AR71XX_PCI_WINDOW5, PCI_WINDOW5_ADDR);
  439         ATH_WRITE_REG(AR71XX_PCI_WINDOW6, PCI_WINDOW6_ADDR);
  440         ATH_WRITE_REG(AR71XX_PCI_WINDOW7, PCI_WINDOW7_CONF_ADDR);
  441         DELAY(100000);
  442 
  443         mtx_lock_spin(&ar71xx_pci_mtx);
  444         ar71xx_pci_check_bus_error();
  445         mtx_unlock_spin(&ar71xx_pci_mtx);
  446 
  447         /* Fixup internal PCI bridge */
  448         ar71xx_pci_local_write(dev, PCIR_COMMAND,
  449             PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN
  450             | PCIM_CMD_SERRESPEN | PCIM_CMD_BACKTOBACK
  451             | PCIM_CMD_PERRESPEN | PCIM_CMD_MWRICEN, 4);
  452 
  453 #ifdef  AR71XX_ATH_EEPROM
  454         /*
  455          * Hard-code a check for slot 17 and 18 - these are
  456          * the two PCI slots which may have a PCI device that
  457          * requires "fixing".
  458          */
  459         ar71xx_pci_slot_fixup(dev, 0, 17, 0);
  460         ar71xx_pci_slot_fixup(dev, 0, 18, 0);
  461 #endif  /* AR71XX_ATH_EEPROM */
  462 
  463         device_add_child(dev, "pci", -1);
  464         return (bus_generic_attach(dev));
  465 }
  466 
  467 static int
  468 ar71xx_pci_read_ivar(device_t dev, device_t child, int which,
  469     uintptr_t *result)
  470 {
  471         struct ar71xx_pci_softc *sc = device_get_softc(dev);
  472 
  473         switch (which) {
  474         case PCIB_IVAR_DOMAIN:
  475                 *result = 0;
  476                 return (0);
  477         case PCIB_IVAR_BUS:
  478                 *result = sc->sc_busno;
  479                 return (0);
  480         }
  481 
  482         return (ENOENT);
  483 }
  484 
  485 static int
  486 ar71xx_pci_write_ivar(device_t dev, device_t child, int which,
  487     uintptr_t result)
  488 {
  489         struct ar71xx_pci_softc * sc = device_get_softc(dev);
  490 
  491         switch (which) {
  492         case PCIB_IVAR_BUS:
  493                 sc->sc_busno = result;
  494                 return (0);
  495         }
  496 
  497         return (ENOENT);
  498 }
  499 
  500 static struct resource *
  501 ar71xx_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
  502     rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
  503 {
  504 
  505         struct ar71xx_pci_softc *sc = device_get_softc(bus);
  506         struct resource *rv;
  507         struct rman *rm;
  508 
  509         switch (type) {
  510         case SYS_RES_IRQ:
  511                 rm = &sc->sc_irq_rman;
  512                 break;
  513         case SYS_RES_MEMORY:
  514                 rm = &sc->sc_mem_rman;
  515                 break;
  516         default:
  517                 return (NULL);
  518         }
  519 
  520         rv = rman_reserve_resource(rm, start, end, count, flags, child);
  521 
  522         if (rv == NULL)
  523                 return (NULL);
  524 
  525         rman_set_rid(rv, *rid);
  526 
  527         if (flags & RF_ACTIVE) {
  528                 if (bus_activate_resource(child, type, *rid, rv)) {
  529                         rman_release_resource(rv);
  530                         return (NULL);
  531                 }
  532         }
  533         return (rv);
  534 }
  535 
  536 static int
  537 ar71xx_pci_activate_resource(device_t bus, device_t child, int type, int rid,
  538     struct resource *r)
  539 {
  540         int res = (BUS_ACTIVATE_RESOURCE(device_get_parent(bus),
  541             child, type, rid, r));
  542 
  543         if (!res) {
  544                 switch(type) {
  545                 case SYS_RES_MEMORY:
  546                 case SYS_RES_IOPORT:
  547                         rman_set_bustag(r, ar71xx_bus_space_pcimem);
  548                         break;
  549                 }
  550         }
  551         return (res);
  552 }
  553 
  554 static int
  555 ar71xx_pci_setup_intr(device_t bus, device_t child, struct resource *ires,
  556             int flags, driver_filter_t *filt, driver_intr_t *handler,
  557             void *arg, void **cookiep)
  558 {
  559         struct ar71xx_pci_softc *sc = device_get_softc(bus);
  560         struct intr_event *event;
  561         int irq, error;
  562 
  563         irq = rman_get_start(ires);
  564 
  565         if (irq > AR71XX_PCI_IRQ_END)
  566                 panic("%s: bad irq %d", __func__, irq);
  567 
  568         event = sc->sc_eventstab[irq];
  569         if (event == NULL) {
  570                 error = intr_event_create(&event, (void *)irq, 0, irq, 
  571                     ar71xx_pci_mask_irq, ar71xx_pci_unmask_irq, NULL, NULL,
  572                     "pci intr%d:", irq);
  573 
  574                 if (error == 0) {
  575                         sc->sc_eventstab[irq] = event;
  576                         sc->sc_intr_counter[irq] =
  577                             mips_intrcnt_create(event->ie_name);
  578                 }
  579                 else
  580                         return (error);
  581         }
  582 
  583         intr_event_add_handler(event, device_get_nameunit(child), filt,
  584             handler, arg, intr_priority(flags), flags, cookiep);
  585         mips_intrcnt_setname(sc->sc_intr_counter[irq], event->ie_fullname);
  586 
  587         ar71xx_pci_unmask_irq((void*)irq);
  588 
  589         return (0);
  590 }
  591 
  592 static int
  593 ar71xx_pci_teardown_intr(device_t dev, device_t child, struct resource *ires,
  594     void *cookie)
  595 {
  596         struct ar71xx_pci_softc *sc = device_get_softc(dev);
  597         int irq, result;
  598 
  599         irq = rman_get_start(ires);
  600         if (irq > AR71XX_PCI_IRQ_END)
  601                 panic("%s: bad irq %d", __func__, irq);
  602 
  603         if (sc->sc_eventstab[irq] == NULL)
  604                 panic("Trying to teardown unoccupied IRQ");
  605 
  606         ar71xx_pci_mask_irq((void*)irq);
  607 
  608         result = intr_event_remove_handler(cookie);
  609         if (!result)
  610                 sc->sc_eventstab[irq] = NULL;
  611 
  612         return (result);
  613 }
  614 
  615 static int
  616 ar71xx_pci_intr(void *arg)
  617 {
  618         struct ar71xx_pci_softc *sc = arg;
  619         struct intr_event *event;
  620         uint32_t reg, irq, mask;
  621 
  622         reg = ATH_READ_REG(AR71XX_PCI_INTR_STATUS);
  623         mask = ATH_READ_REG(AR71XX_PCI_INTR_MASK);
  624         /*
  625          * Handle only unmasked interrupts
  626          */
  627         reg &= mask;
  628         for (irq = AR71XX_PCI_IRQ_START; irq <= AR71XX_PCI_IRQ_END; irq++) {
  629                 if (reg & (1 << irq)) {
  630                         event = sc->sc_eventstab[irq];
  631                         if (!event || TAILQ_EMPTY(&event->ie_handlers)) {
  632                                 /* Ignore timer interrupts */
  633                                 if (irq != 0)
  634                                         printf("Stray IRQ %d\n", irq);
  635                                 continue;
  636                         }
  637 
  638                         /* Flush DDR FIFO for PCI/PCIe */
  639                         ar71xx_device_flush_ddr(AR71XX_CPU_DDR_FLUSH_PCIE);
  640 
  641                         /* TODO: frame instead of NULL? */
  642                         intr_event_handle(event, NULL);
  643                         mips_intrcnt_inc(sc->sc_intr_counter[irq]);
  644                 }
  645         }
  646 
  647         return (FILTER_HANDLED);
  648 }
  649 
  650 static int
  651 ar71xx_pci_maxslots(device_t dev)
  652 {
  653 
  654         return (PCI_SLOTMAX);
  655 }
  656 
  657 static int
  658 ar71xx_pci_route_interrupt(device_t pcib, device_t device, int pin)
  659 {
  660         struct ar71xx_pci_softc *sc = device_get_softc(pcib);
  661         
  662         if (pci_get_slot(device) < sc->sc_baseslot)
  663                 panic("%s: PCI slot %d is less then AR71XX_PCI_BASE_SLOT",
  664                     __func__, pci_get_slot(device));
  665 
  666         return (pci_get_slot(device) - sc->sc_baseslot);
  667 }
  668 
  669 static device_method_t ar71xx_pci_methods[] = {
  670         /* Device interface */
  671         DEVMETHOD(device_probe,         ar71xx_pci_probe),
  672         DEVMETHOD(device_attach,        ar71xx_pci_attach),
  673         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
  674         DEVMETHOD(device_suspend,       bus_generic_suspend),
  675         DEVMETHOD(device_resume,        bus_generic_resume),
  676 
  677         /* Bus interface */
  678         DEVMETHOD(bus_read_ivar,        ar71xx_pci_read_ivar),
  679         DEVMETHOD(bus_write_ivar,       ar71xx_pci_write_ivar),
  680         DEVMETHOD(bus_alloc_resource,   ar71xx_pci_alloc_resource),
  681         DEVMETHOD(bus_release_resource, bus_generic_release_resource),
  682         DEVMETHOD(bus_activate_resource, ar71xx_pci_activate_resource),
  683         DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
  684         DEVMETHOD(bus_setup_intr,       ar71xx_pci_setup_intr),
  685         DEVMETHOD(bus_teardown_intr,    ar71xx_pci_teardown_intr),
  686 
  687         /* pcib interface */
  688         DEVMETHOD(pcib_maxslots,        ar71xx_pci_maxslots),
  689         DEVMETHOD(pcib_read_config,     ar71xx_pci_read_config),
  690         DEVMETHOD(pcib_write_config,    ar71xx_pci_write_config),
  691         DEVMETHOD(pcib_route_interrupt, ar71xx_pci_route_interrupt),
  692 
  693         DEVMETHOD_END
  694 };
  695 
  696 static driver_t ar71xx_pci_driver = {
  697         "pcib",
  698         ar71xx_pci_methods,
  699         sizeof(struct ar71xx_pci_softc),
  700 };
  701 
  702 static devclass_t ar71xx_pci_devclass;
  703 
  704 DRIVER_MODULE(ar71xx_pci, nexus, ar71xx_pci_driver, ar71xx_pci_devclass, 0, 0);
Cache object: 9fc0fb8f04d0910e2744d6af08763b20
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FreeBSD/Linux Kernel Cross Reference sys/mips/atheros/ar71xx_pci.c

FreeBSD/Linux Kernel Cross Reference
sys/mips/atheros/ar71xx_pci.c
