The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/mips/atheros/ar71xxreg.h

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
    3  *
    4  * Copyright (c) 2009 Oleksandr Tymoshenko
    5  * All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  *
   16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   26  * SUCH DAMAGE.
   27  */
   28 
   29 /* $FreeBSD: stable/12/sys/mips/atheros/ar71xxreg.h 326259 2017-11-27 15:07:26Z pfg $ */
   30 
   31 #ifndef _AR71XX_REG_H_
   32 #define _AR71XX_REG_H_
   33 
   34 /* PCI region */
   35 #define AR71XX_PCI_MEM_BASE             0x10000000
   36 /* 
   37  * PCI mem windows is 0x08000000 bytes long but we exclude control 
   38  * region from the resource manager
   39  */
   40 #define AR71XX_PCI_MEM_SIZE             0x07000000
   41 #define AR71XX_PCI_IRQ_START            0
   42 #define AR71XX_PCI_IRQ_END              2
   43 #define AR71XX_PCI_NIRQS                3
   44 /*
   45  * PCI devices slots are starting from this number
   46  */
   47 #define AR71XX_PCI_BASE_SLOT            17
   48 
   49 /* PCI config registers */
   50 #define AR71XX_PCI_LCONF_CMD            0x17010000
   51 #define                 PCI_LCONF_CMD_READ      0x00000000
   52 #define                 PCI_LCONF_CMD_WRITE     0x00010000
   53 #define AR71XX_PCI_LCONF_WRITE_DATA     0x17010004
   54 #define AR71XX_PCI_LCONF_READ_DATA      0x17010008
   55 #define AR71XX_PCI_CONF_ADDR            0x1701000C
   56 #define AR71XX_PCI_CONF_CMD             0x17010010
   57 #define                 PCI_CONF_CMD_READ       0x0000000A
   58 #define                 PCI_CONF_CMD_WRITE      0x0000000B
   59 #define AR71XX_PCI_CONF_WRITE_DATA      0x17010014
   60 #define AR71XX_PCI_CONF_READ_DATA       0x17010018
   61 #define AR71XX_PCI_ERROR                0x1701001C
   62 #define AR71XX_PCI_ERROR_ADDR           0x17010020
   63 #define AR71XX_PCI_AHB_ERROR            0x17010024
   64 #define AR71XX_PCI_AHB_ERROR_ADDR       0x17010028
   65 
   66 /* APB region */
   67 /*
   68  * Size is not really true actual APB window size is 
   69  * 0x01000000 but it should handle OHCI memory as well
   70  * because this controller's interrupt is routed through 
   71  * APB. 
   72  */
   73 #define AR71XX_APB_BASE         0x18000000
   74 #define AR71XX_APB_SIZE         0x06000000
   75 
   76 /* DDR registers */
   77 #define AR71XX_DDR_CONFIG               0x18000000
   78 #define AR71XX_DDR_CONFIG2              0x18000004
   79 #define AR71XX_DDR_MODE_REGISTER        0x18000008
   80 #define AR71XX_DDR_EXT_MODE_REGISTER    0x1800000C
   81 #define AR71XX_DDR_CONTROL              0x18000010
   82 #define AR71XX_DDR_REFRESH              0x18000014
   83 #define AR71XX_DDR_RD_DATA_THIS_CYCLE   0x18000018
   84 #define AR71XX_TAP_CONTROL0             0x1800001C
   85 #define AR71XX_TAP_CONTROL1             0x18000020
   86 #define AR71XX_TAP_CONTROL2             0x18000024
   87 #define AR71XX_TAP_CONTROL3             0x18000028
   88 #define AR71XX_PCI_WINDOW0              0x1800007C
   89 #define AR71XX_PCI_WINDOW1              0x18000080
   90 #define AR71XX_PCI_WINDOW2              0x18000084
   91 #define AR71XX_PCI_WINDOW3              0x18000088
   92 #define AR71XX_PCI_WINDOW4              0x1800008C
   93 #define AR71XX_PCI_WINDOW5              0x18000090
   94 #define AR71XX_PCI_WINDOW6              0x18000094
   95 #define AR71XX_PCI_WINDOW7              0x18000098
   96 #define AR71XX_WB_FLUSH_GE0             0x1800009C
   97 #define AR71XX_WB_FLUSH_GE1             0x180000A0
   98 #define AR71XX_WB_FLUSH_USB             0x180000A4
   99 #define AR71XX_WB_FLUSH_PCI             0x180000A8
  100 
  101 /*
  102  * Values for PCI_WINDOW_X registers 
  103  */
  104 #define PCI_WINDOW0_ADDR                0x10000000
  105 #define PCI_WINDOW1_ADDR                0x11000000
  106 #define PCI_WINDOW2_ADDR                0x12000000
  107 #define PCI_WINDOW3_ADDR                0x13000000
  108 #define PCI_WINDOW4_ADDR                0x14000000
  109 #define PCI_WINDOW5_ADDR                0x15000000
  110 #define PCI_WINDOW6_ADDR                0x16000000
  111 #define PCI_WINDOW7_ADDR                0x17000000
  112 /* This value enables acces to PCI config registers */
  113 #define PCI_WINDOW7_CONF_ADDR           0x07000000
  114 
  115 #define AR71XX_UART_ADDR                0x18020000
  116 #define         AR71XX_UART_THR         0x0
  117 #define         AR71XX_UART_LSR         0x14
  118 #define         AR71XX_UART_LSR_THRE    (1 << 5)
  119 #define         AR71XX_UART_LSR_TEMT    (1 << 6)
  120 
  121 #define AR71XX_USB_CTRL_FLADJ           0x18030000
  122 #define         USB_CTRL_FLADJ_HOST_SHIFT       12
  123 #define         USB_CTRL_FLADJ_A5_SHIFT         10
  124 #define         USB_CTRL_FLADJ_A4_SHIFT         8
  125 #define         USB_CTRL_FLADJ_A3_SHIFT         6
  126 #define         USB_CTRL_FLADJ_A2_SHIFT         4
  127 #define         USB_CTRL_FLADJ_A1_SHIFT         2
  128 #define         USB_CTRL_FLADJ_A0_SHIFT         0
  129 #define AR71XX_USB_CTRL_CONFIG          0x18030004
  130 #define         USB_CTRL_CONFIG_OHCI_DES_SWAP   (1 << 19)
  131 #define         USB_CTRL_CONFIG_OHCI_BUF_SWAP   (1 << 18)
  132 #define         USB_CTRL_CONFIG_EHCI_DES_SWAP   (1 << 17)
  133 #define         USB_CTRL_CONFIG_EHCI_BUF_SWAP   (1 << 16)
  134 #define         USB_CTRL_CONFIG_DISABLE_XTL     (1 << 13)
  135 #define         USB_CTRL_CONFIG_OVERRIDE_XTL    (1 << 12)
  136 #define         USB_CTRL_CONFIG_CLK_SEL_SHIFT   4
  137 #define         USB_CTRL_CONFIG_CLK_SEL_MASK    3
  138 #define         USB_CTRL_CONFIG_CLK_SEL_12      0
  139 #define         USB_CTRL_CONFIG_CLK_SEL_24      1
  140 #define         USB_CTRL_CONFIG_CLK_SEL_48      2
  141 #define         USB_CTRL_CONFIG_OVER_CURRENT_AS_GPIO    (1 << 8)
  142 #define         USB_CTRL_CONFIG_SS_SIMULATION_MODE      (1 << 2)
  143 #define         USB_CTRL_CONFIG_RESUME_UTMI_PLS_DIS     (1 << 1)
  144 #define         USB_CTRL_CONFIG_UTMI_BACKWARD_ENB       (1 << 0)
  145 
  146 #define AR71XX_GPIO_BASE                0x18040000
  147 #define         AR71XX_GPIO_OE                  0x00
  148 #define         AR71XX_GPIO_IN                  0x04
  149 #define         AR71XX_GPIO_OUT                 0x08
  150 #define         AR71XX_GPIO_SET                 0x0c
  151 #define         AR71XX_GPIO_CLEAR               0x10
  152 #define         AR71XX_GPIO_INT                 0x14
  153 #define         AR71XX_GPIO_INT_TYPE            0x18
  154 #define         AR71XX_GPIO_INT_POLARITY        0x1c
  155 #define         AR71XX_GPIO_INT_PENDING         0x20
  156 #define         AR71XX_GPIO_INT_MASK            0x24
  157 #define         AR71XX_GPIO_FUNCTION            0x28
  158 #define                 GPIO_FUNC_STEREO_EN     (1 << 17)
  159 #define                 GPIO_FUNC_SLIC_EN       (1 << 16)
  160 #define                 GPIO_FUNC_SPI_CS2_EN    (1 << 13)
  161                                 /* CS2 is shared with GPIO_1 */
  162 #define                 GPIO_FUNC_SPI_CS1_EN    (1 << 12)
  163                                 /* CS1 is shared with GPIO_0 */
  164 #define                 GPIO_FUNC_UART_EN       (1 << 8)
  165 #define                 GPIO_FUNC_USB_OC_EN     (1 << 4)
  166 #define                 GPIO_FUNC_USB_CLK_EN    (0)
  167 
  168 #define AR71XX_BASE_FREQ                40000000
  169 #define AR71XX_PLL_CPU_BASE             0x18050000
  170 #define AR71XX_PLL_CPU_CONFIG           0x18050000
  171 #define         PLL_SW_UPDATE                   (1U << 31)
  172 #define         PLL_LOCKED                      (1 << 30)
  173 #define         PLL_AHB_DIV_SHIFT               20
  174 #define         PLL_AHB_DIV_MASK                7
  175 #define         PLL_DDR_DIV_SEL_SHIFT           18
  176 #define         PLL_DDR_DIV_SEL_MASK            3
  177 #define         PLL_CPU_DIV_SEL_SHIFT           16
  178 #define         PLL_CPU_DIV_SEL_MASK            3
  179 #define         PLL_LOOP_BW_SHIFT               12
  180 #define         PLL_LOOP_BW_MASK                0xf
  181 #define         PLL_DIV_IN_SHIFT                10
  182 #define         PLL_DIV_IN_MASK                 3
  183 #define         PLL_DIV_OUT_SHIFT               8
  184 #define         PLL_DIV_OUT_MASK                3
  185 #define         PLL_FB_SHIFT                    3
  186 #define         PLL_FB_MASK                     0x1f
  187 #define         PLL_BYPASS                      (1 << 1)
  188 #define         PLL_POWER_DOWN                  (1 << 0)
  189 #define AR71XX_PLL_SEC_CONFIG           0x18050004
  190 #define         AR71XX_PLL_ETH0_SHIFT           17
  191 #define         AR71XX_PLL_ETH1_SHIFT           19
  192 #define AR71XX_PLL_CPU_CLK_CTRL         0x18050008
  193 #define AR71XX_PLL_ETH_INT0_CLK         0x18050010
  194 #define AR71XX_PLL_ETH_INT1_CLK         0x18050014
  195 #define         XPLL_ETH_INT_CLK_10             0x00991099
  196 #define         XPLL_ETH_INT_CLK_100            0x00441011
  197 #define         XPLL_ETH_INT_CLK_1000           0x13110000
  198 #define         XPLL_ETH_INT_CLK_1000_GMII      0x14110000
  199 #define         PLL_ETH_INT_CLK_10              0x00991099
  200 #define         PLL_ETH_INT_CLK_100             0x00001099
  201 #define         PLL_ETH_INT_CLK_1000            0x00110000
  202 #define AR71XX_PLL_ETH_EXT_CLK          0x18050018
  203 #define AR71XX_PLL_PCI_CLK              0x1805001C
  204 
  205 /* Reset block */
  206 #define AR71XX_RST_BLOCK_BASE   0x18060000
  207 
  208 #define AR71XX_RST_WDOG_CONTROL 0x18060008
  209 #define         RST_WDOG_LAST                   (1U << 31)
  210 #define         RST_WDOG_ACTION_MASK            3
  211 #define         RST_WDOG_ACTION_RESET           3
  212 #define         RST_WDOG_ACTION_NMI             2
  213 #define         RST_WDOG_ACTION_GP_INTR         1
  214 #define         RST_WDOG_ACTION_NOACTION        0
  215 
  216 #define AR71XX_RST_WDOG_TIMER   0x1806000C
  217 /* 
  218  * APB interrupt status and mask register and interrupt bit numbers for 
  219  */
  220 #define AR71XX_MISC_INTR_STATUS 0x18060010
  221 #define AR71XX_MISC_INTR_MASK   0x18060014
  222 #define         MISC_INTR_TIMER         0
  223 #define         MISC_INTR_ERROR         1
  224 #define         MISC_INTR_GPIO          2
  225 #define         MISC_INTR_UART          3
  226 #define         MISC_INTR_WATCHDOG      4
  227 #define         MISC_INTR_PERF          5
  228 #define         MISC_INTR_OHCI          6
  229 #define         MISC_INTR_DMA           7
  230 
  231 #define AR71XX_PCI_INTR_STATUS  0x18060018
  232 #define AR71XX_PCI_INTR_MASK    0x1806001C
  233 #define         PCI_INTR_CORE           (1 << 4)
  234 
  235 #define AR71XX_RST_RESET        0x18060024
  236 #define         RST_RESET_FULL_CHIP     (1 << 24) /* Same as pulling
  237                                                              the reset pin */
  238 #define         RST_RESET_CPU_COLD      (1 << 20) /* Cold reset */
  239 #define         RST_RESET_GE1_MAC       (1 << 13)
  240 #define         RST_RESET_GE1_PHY       (1 << 12)
  241 #define         RST_RESET_GE0_MAC       (1 <<  9)
  242 #define         RST_RESET_GE0_PHY       (1 <<  8)
  243 #define         RST_RESET_USB_OHCI_DLL  (1 <<  6)
  244 #define         RST_RESET_USB_HOST      (1 <<  5)
  245 #define         RST_RESET_USB_PHY       (1 <<  4)
  246 #define         RST_RESET_PCI_BUS       (1 <<  1)
  247 #define         RST_RESET_PCI_CORE      (1 <<  0)
  248 
  249 /* Chipset revision details */
  250 #define AR71XX_RST_RESET_REG_REV_ID     0x18060090
  251 #define         REV_ID_MAJOR_MASK       0xfff0
  252 #define         REV_ID_MAJOR_AR71XX     0x00a0
  253 #define         REV_ID_MAJOR_AR913X     0x00b0
  254 #define         REV_ID_MAJOR_AR7240     0x00c0
  255 #define         REV_ID_MAJOR_AR7241     0x0100
  256 #define         REV_ID_MAJOR_AR7242     0x1100
  257 
  258 /* AR71XX chipset revision details */
  259 #define         AR71XX_REV_ID_MINOR_MASK        0x3
  260 #define         AR71XX_REV_ID_MINOR_AR7130      0x0
  261 #define         AR71XX_REV_ID_MINOR_AR7141      0x1
  262 #define         AR71XX_REV_ID_MINOR_AR7161      0x2
  263 #define         AR71XX_REV_ID_REVISION_MASK     0x3
  264 #define         AR71XX_REV_ID_REVISION_SHIFT    2
  265 
  266 /* AR724X chipset revision details */
  267 #define         AR724X_REV_ID_REVISION_MASK     0x3
  268 
  269 /* AR91XX chipset revision details */
  270 #define         AR91XX_REV_ID_MINOR_MASK        0x3
  271 #define         AR91XX_REV_ID_MINOR_AR9130      0x0
  272 #define         AR91XX_REV_ID_MINOR_AR9132      0x1
  273 #define         AR91XX_REV_ID_REVISION_MASK     0x3
  274 #define         AR91XX_REV_ID_REVISION_SHIFT    2
  275 
  276 typedef enum {
  277         AR71XX_MII_MODE_NONE = 0,
  278         AR71XX_MII_MODE_GMII,
  279         AR71XX_MII_MODE_MII,
  280         AR71XX_MII_MODE_RGMII,
  281         AR71XX_MII_MODE_RMII,
  282         AR71XX_MII_MODE_SGMII   /* not hardware defined, though! */
  283 } ar71xx_mii_mode;
  284 
  285 /*
  286  * AR71xx MII control region
  287  */
  288 #define AR71XX_MII0_CTRL        0x18070000
  289 #define                 MII_CTRL_SPEED_SHIFT    4
  290 #define                 MII_CTRL_SPEED_MASK     3
  291 #define                         MII_CTRL_SPEED_10       0
  292 #define                         MII_CTRL_SPEED_100      1
  293 #define                         MII_CTRL_SPEED_1000     2
  294 #define                 MII_CTRL_IF_MASK        3
  295 #define                 MII_CTRL_IF_SHIFT       0
  296 #define                         MII0_CTRL_IF_GMII       0
  297 #define                         MII0_CTRL_IF_MII        1
  298 #define                         MII0_CTRL_IF_RGMII      2
  299 #define                         MII0_CTRL_IF_RMII       3
  300 
  301 #define AR71XX_MII1_CTRL        0x18070004
  302 
  303 #define                         MII1_CTRL_IF_RGMII      0
  304 #define                         MII1_CTRL_IF_RMII       1
  305 
  306 /*
  307  * GigE adapters region
  308  */
  309 #define AR71XX_MAC0_BASE        0x19000000
  310 #define AR71XX_MAC1_BASE        0x1A000000
  311 
  312 #define         AR71XX_MAC_CFG1                 0x00
  313 #define                 MAC_CFG1_SOFT_RESET             (1U << 31)
  314 #define                 MAC_CFG1_SIMUL_RESET            (1 << 30)
  315 #define                 MAC_CFG1_MAC_RX_BLOCK_RESET     (1 << 19)
  316 #define                 MAC_CFG1_MAC_TX_BLOCK_RESET     (1 << 18)
  317 #define                 MAC_CFG1_RX_FUNC_RESET          (1 << 17)
  318 #define                 MAC_CFG1_TX_FUNC_RESET          (1 << 16)
  319 #define                 MAC_CFG1_LOOPBACK               (1 <<  8)
  320 #define                 MAC_CFG1_RXFLOW_CTRL            (1 <<  5)
  321 #define                 MAC_CFG1_TXFLOW_CTRL            (1 <<  4)
  322 #define                 MAC_CFG1_SYNC_RX                (1 <<  3)
  323 #define                 MAC_CFG1_RX_ENABLE              (1 <<  2)
  324 #define                 MAC_CFG1_SYNC_TX                (1 <<  1)
  325 #define                 MAC_CFG1_TX_ENABLE              (1 <<  0)
  326 #define         AR71XX_MAC_CFG2                 0x04
  327 #define                 MAC_CFG2_PREAMBLE_LEN_MASK      0xf
  328 #define                 MAC_CFG2_PREAMBLE_LEN_SHIFT     12
  329 #define                 MAC_CFG2_IFACE_MODE_1000        (2 << 8)
  330 #define                 MAC_CFG2_IFACE_MODE_10_100      (1 << 8)
  331 #define                 MAC_CFG2_IFACE_MODE_SHIFT       8
  332 #define                 MAC_CFG2_IFACE_MODE_MASK        3
  333 #define                 MAC_CFG2_HUGE_FRAME             (1 << 5)
  334 #define                 MAC_CFG2_LENGTH_FIELD           (1 << 4)
  335 #define                 MAC_CFG2_ENABLE_PADCRC          (1 << 2)
  336 #define                 MAC_CFG2_ENABLE_CRC             (1 << 1)
  337 #define                 MAC_CFG2_FULL_DUPLEX            (1 << 0)
  338 #define         AR71XX_MAC_IFG                  0x08
  339 #define         AR71XX_MAC_HDUPLEX              0x0C
  340 #define         AR71XX_MAC_MAX_FRAME_LEN        0x10
  341 #define         AR71XX_MAC_MII_CFG              0x20
  342 #define                 MAC_MII_CFG_RESET               (1U << 31)
  343 #define                 MAC_MII_CFG_SCAN_AUTO_INC       (1 <<  5)
  344 #define                 MAC_MII_CFG_PREAMBLE_SUP        (1 <<  4)
  345 #define                 MAC_MII_CFG_CLOCK_SELECT_MASK   0x7
  346 #define                 MAC_MII_CFG_CLOCK_SELECT_MASK_AR933X    0xf
  347 #define                 MAC_MII_CFG_CLOCK_DIV_4         0
  348 #define                 MAC_MII_CFG_CLOCK_DIV_6         2
  349 #define                 MAC_MII_CFG_CLOCK_DIV_8         3
  350 #define                 MAC_MII_CFG_CLOCK_DIV_10        4
  351 #define                 MAC_MII_CFG_CLOCK_DIV_14        5
  352 #define                 MAC_MII_CFG_CLOCK_DIV_20        6
  353 #define                 MAC_MII_CFG_CLOCK_DIV_28        7
  354 
  355 /* .. and the AR933x/AR934x extensions */
  356 #define                 MAC_MII_CFG_CLOCK_DIV_34        8
  357 #define                 MAC_MII_CFG_CLOCK_DIV_42        9
  358 #define                 MAC_MII_CFG_CLOCK_DIV_50        10
  359 #define                 MAC_MII_CFG_CLOCK_DIV_58        11
  360 #define                 MAC_MII_CFG_CLOCK_DIV_66        12
  361 #define                 MAC_MII_CFG_CLOCK_DIV_74        13
  362 #define                 MAC_MII_CFG_CLOCK_DIV_82        14
  363 #define                 MAC_MII_CFG_CLOCK_DIV_98        15
  364 
  365 #define         AR71XX_MAC_MII_CMD              0x24
  366 #define                 MAC_MII_CMD_SCAN_CYCLE          (1 << 1)
  367 #define                 MAC_MII_CMD_READ                1
  368 #define                 MAC_MII_CMD_WRITE               0
  369 #define         AR71XX_MAC_MII_ADDR             0x28
  370 #define                 MAC_MII_PHY_ADDR_SHIFT          8
  371 #define                 MAC_MII_PHY_ADDR_MASK           0xff
  372 #define                 MAC_MII_REG_MASK                0x1f
  373 #define         AR71XX_MAC_MII_CONTROL          0x2C
  374 #define                 MAC_MII_CONTROL_MASK            0xffff
  375 #define         AR71XX_MAC_MII_STATUS           0x30
  376 #define                 MAC_MII_STATUS_MASK             0xffff
  377 #define         AR71XX_MAC_MII_INDICATOR        0x34
  378 #define                 MAC_MII_INDICATOR_NOT_VALID     (1 << 2)
  379 #define                 MAC_MII_INDICATOR_SCANNING      (1 << 1)
  380 #define                 MAC_MII_INDICATOR_BUSY          (1 << 0)
  381 #define         AR71XX_MAC_IFCONTROL            0x38
  382 #define                 MAC_IFCONTROL_SPEED     (1 << 16)
  383 #define         AR71XX_MAC_STA_ADDR1            0x40
  384 #define         AR71XX_MAC_STA_ADDR2            0x44
  385 #define         AR71XX_MAC_FIFO_CFG0            0x48
  386 #define                 FIFO_CFG0_TX_FABRIC             (1 << 4)
  387 #define                 FIFO_CFG0_TX_SYSTEM             (1 << 3)
  388 #define                 FIFO_CFG0_RX_FABRIC             (1 << 2)
  389 #define                 FIFO_CFG0_RX_SYSTEM             (1 << 1)
  390 #define                 FIFO_CFG0_WATERMARK             (1 << 0)
  391 #define                 FIFO_CFG0_ALL                   ((1 << 5) - 1)
  392 #define                 FIFO_CFG0_ENABLE_SHIFT          8
  393 #define         AR71XX_MAC_FIFO_CFG1            0x4C
  394 #define         AR71XX_MAC_FIFO_CFG2            0x50
  395 #define         AR71XX_MAC_FIFO_TX_THRESHOLD    0x54
  396 #define         AR71XX_MAC_FIFO_RX_FILTMATCH    0x58
  397 /* 
  398  * These flags applicable both to AR71XX_MAC_FIFO_RX_FILTMASK and
  399  * to AR71XX_MAC_FIFO_RX_FILTMATCH
  400  */
  401 #define                 FIFO_RX_MATCH_UNICAST           (1 << 17)
  402 #define                 FIFO_RX_MATCH_TRUNC_FRAME       (1 << 16)
  403 #define                 FIFO_RX_MATCH_VLAN_TAG          (1 << 15)
  404 #define                 FIFO_RX_MATCH_UNSUP_OPCODE      (1 << 14)
  405 #define                 FIFO_RX_MATCH_PAUSE_FRAME       (1 << 13)
  406 #define                 FIFO_RX_MATCH_CTRL_FRAME        (1 << 12)
  407 #define                 FIFO_RX_MATCH_LONG_EVENT        (1 << 11)
  408 #define                 FIFO_RX_MATCH_DRIBBLE_NIBBLE    (1 << 10)
  409 #define                 FIFO_RX_MATCH_BCAST             (1 <<  9)
  410 #define                 FIFO_RX_MATCH_MCAST             (1 <<  8)
  411 #define                 FIFO_RX_MATCH_OK                (1 <<  7)
  412 #define                 FIFO_RX_MATCH_OORANGE           (1 <<  6)
  413 #define                 FIFO_RX_MATCH_LEN_MSMTCH        (1 <<  5)
  414 #define                 FIFO_RX_MATCH_CRC_ERROR         (1 <<  4)
  415 #define                 FIFO_RX_MATCH_CODE_ERROR        (1 <<  3)
  416 #define                 FIFO_RX_MATCH_FALSE_CARRIER     (1 <<  2)
  417 #define                 FIFO_RX_MATCH_RX_DV_EVENT       (1 <<  1)
  418 #define                 FIFO_RX_MATCH_DROP_EVENT        (1 <<  0)
  419 /*
  420  * Exclude unicast and truncated frames from matching
  421  */
  422 #define                 FIFO_RX_FILTMATCH_DEFAULT               \
  423                                 (FIFO_RX_MATCH_VLAN_TAG         | \
  424                                 FIFO_RX_MATCH_UNSUP_OPCODE      | \
  425                                 FIFO_RX_MATCH_PAUSE_FRAME       | \
  426                                 FIFO_RX_MATCH_CTRL_FRAME        | \
  427                                 FIFO_RX_MATCH_LONG_EVENT        | \
  428                                 FIFO_RX_MATCH_DRIBBLE_NIBBLE    | \
  429                                 FIFO_RX_MATCH_BCAST             | \
  430                                 FIFO_RX_MATCH_MCAST             | \
  431                                 FIFO_RX_MATCH_OK                | \
  432                                 FIFO_RX_MATCH_OORANGE           | \
  433                                 FIFO_RX_MATCH_LEN_MSMTCH        | \
  434                                 FIFO_RX_MATCH_CRC_ERROR         | \
  435                                 FIFO_RX_MATCH_CODE_ERROR        | \
  436                                 FIFO_RX_MATCH_FALSE_CARRIER     | \
  437                                 FIFO_RX_MATCH_RX_DV_EVENT       | \
  438                                 FIFO_RX_MATCH_DROP_EVENT)
  439 #define         AR71XX_MAC_FIFO_RX_FILTMASK     0x5C
  440 #define                 FIFO_RX_MASK_BYTE_MODE          (1 << 19)
  441 #define                 FIFO_RX_MASK_NO_SHORT_FRAME     (1 << 18)
  442 #define                 FIFO_RX_MASK_BIT17              (1 << 17)
  443 #define                 FIFO_RX_MASK_BIT16              (1 << 16)
  444 #define                 FIFO_RX_MASK_TRUNC_FRAME        (1 << 15)
  445 #define                 FIFO_RX_MASK_LONG_EVENT         (1 << 14)
  446 #define                 FIFO_RX_MASK_VLAN_TAG           (1 << 13)
  447 #define                 FIFO_RX_MASK_UNSUP_OPCODE       (1 << 12)
  448 #define                 FIFO_RX_MASK_PAUSE_FRAME        (1 << 11)
  449 #define                 FIFO_RX_MASK_CTRL_FRAME         (1 << 10)
  450 #define                 FIFO_RX_MASK_DRIBBLE_NIBBLE     (1 <<  9)
  451 #define                 FIFO_RX_MASK_BCAST              (1 <<  8)
  452 #define                 FIFO_RX_MASK_MCAST              (1 <<  7)
  453 #define                 FIFO_RX_MASK_OK                 (1 <<  6)
  454 #define                 FIFO_RX_MASK_OORANGE            (1 <<  5)
  455 #define                 FIFO_RX_MASK_LEN_MSMTCH         (1 <<  4)
  456 #define                 FIFO_RX_MASK_CODE_ERROR         (1 <<  3)
  457 #define                 FIFO_RX_MASK_FALSE_CARRIER      (1 <<  2)
  458 #define                 FIFO_RX_MASK_RX_DV_EVENT        (1 <<  1)
  459 #define                 FIFO_RX_MASK_DROP_EVENT         (1 <<  0)
  460 
  461 /*
  462  *  Len. mismatch, unsup. opcode and short frmae bits excluded
  463  */
  464 #define                 FIFO_RX_FILTMASK_DEFAULT \
  465                                 (FIFO_RX_MASK_NO_SHORT_FRAME    | \
  466                                 FIFO_RX_MASK_BIT17              | \
  467                                 FIFO_RX_MASK_BIT16              | \
  468                                 FIFO_RX_MASK_TRUNC_FRAME        | \
  469                                 FIFO_RX_MASK_LONG_EVENT         | \
  470                                 FIFO_RX_MASK_VLAN_TAG           | \
  471                                 FIFO_RX_MASK_PAUSE_FRAME        | \
  472                                 FIFO_RX_MASK_CTRL_FRAME         | \
  473                                 FIFO_RX_MASK_DRIBBLE_NIBBLE     | \
  474                                 FIFO_RX_MASK_BCAST              | \
  475                                 FIFO_RX_MASK_MCAST              | \
  476                                 FIFO_RX_MASK_OK                 | \
  477                                 FIFO_RX_MASK_OORANGE            | \
  478                                 FIFO_RX_MASK_CODE_ERROR         | \
  479                                 FIFO_RX_MASK_FALSE_CARRIER      | \
  480                                 FIFO_RX_MASK_RX_DV_EVENT        | \
  481                                 FIFO_RX_MASK_DROP_EVENT)
  482 
  483 #define         AR71XX_MAC_FIFO_RAM0            0x60
  484 #define         AR71XX_MAC_FIFO_RAM1            0x64
  485 #define         AR71XX_MAC_FIFO_RAM2            0x68
  486 #define         AR71XX_MAC_FIFO_RAM3            0x6C
  487 #define         AR71XX_MAC_FIFO_RAM4            0x70
  488 #define         AR71XX_MAC_FIFO_RAM5            0x74
  489 #define         AR71XX_MAC_FIFO_RAM6            0x78
  490 #define         AR71XX_DMA_TX_CONTROL           0x180
  491 #define                 DMA_TX_CONTROL_EN               (1 << 0)
  492 #define         AR71XX_DMA_TX_DESC              0x184
  493 #define         AR71XX_DMA_TX_STATUS            0x188
  494 #define                 DMA_TX_STATUS_PCOUNT_MASK       0xff
  495 #define                 DMA_TX_STATUS_PCOUNT_SHIFT      16
  496 #define                 DMA_TX_STATUS_BUS_ERROR         (1 << 3) 
  497 #define                 DMA_TX_STATUS_UNDERRUN          (1 << 1) 
  498 #define                 DMA_TX_STATUS_PKT_SENT          (1 << 0) 
  499 #define         AR71XX_DMA_RX_CONTROL           0x18C
  500 #define                 DMA_RX_CONTROL_EN               (1 << 0)
  501 #define         AR71XX_DMA_RX_DESC              0x190
  502 #define         AR71XX_DMA_RX_STATUS            0x194
  503 #define                 DMA_RX_STATUS_PCOUNT_MASK       0xff
  504 #define                 DMA_RX_STATUS_PCOUNT_SHIFT      16
  505 #define                 DMA_RX_STATUS_BUS_ERROR         (1 << 3)
  506 #define                 DMA_RX_STATUS_OVERFLOW          (1 << 2)
  507 #define                 DMA_RX_STATUS_PKT_RECVD         (1 << 0)
  508 #define         AR71XX_DMA_INTR                         0x198
  509 #define         AR71XX_DMA_INTR_STATUS                  0x19C
  510 #define                 DMA_INTR_ALL                    ((1 << 8) - 1)
  511 #define                 DMA_INTR_RX_BUS_ERROR           (1 << 7)
  512 #define                 DMA_INTR_RX_OVERFLOW            (1 << 6)
  513 #define                 DMA_INTR_RX_PKT_RCVD            (1 << 4)
  514 #define                 DMA_INTR_TX_BUS_ERROR           (1 << 3)
  515 #define                 DMA_INTR_TX_UNDERRUN            (1 << 1)
  516 #define                 DMA_INTR_TX_PKT_SENT            (1 << 0)
  517 
  518 #define AR71XX_SPI_BASE 0x1f000000
  519 #define         AR71XX_SPI_FS           0x00
  520 #define         AR71XX_SPI_CTRL         0x04
  521 #define                 SPI_CTRL_REMAP_DISABLE          (1 << 6)
  522 #define                 SPI_CTRL_CLOCK_DIVIDER_MASK     ((1 << 6) - 1)
  523 #define         AR71XX_SPI_IO_CTRL      0x08
  524 #define                 SPI_IO_CTRL_CS2                 (1 << 18)
  525 #define                 SPI_IO_CTRL_CS1                 (1 << 17)
  526 #define                 SPI_IO_CTRL_CS0                 (1 << 16)
  527 #define                 SPI_IO_CTRL_CSMASK              (7 << 16)
  528 #define                 SPI_IO_CTRL_CLK                 (1 << 8)
  529 #define                 SPI_IO_CTRL_DO                  1
  530 #define         AR71XX_SPI_RDS          0x0C
  531 
  532 #define ATH_READ_REG(reg) \
  533         *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1((reg)))
  534 /*
  535  * Note: Don't put a flush read here; some users (eg the AR724x PCI fixup code)
  536  * requires write-only space to certain registers.  Doing the read afterwards
  537  * causes things to break.
  538  */
  539 #define ATH_WRITE_REG(reg, val) \
  540       *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1((reg))) = (val)
  541 
  542 static inline void
  543 ar71xx_ddr_flush(uint32_t reg)
  544 { 
  545         ATH_WRITE_REG(reg, 1);
  546         while ((ATH_READ_REG(reg) & 0x1))
  547                 ;
  548         ATH_WRITE_REG(reg, 1);
  549         while ((ATH_READ_REG(reg) & 0x1))
  550                 ;
  551 } 
  552 
  553 static inline void
  554 ar71xx_write_pll(uint32_t cfg_reg, uint32_t pll_reg, uint32_t pll, uint32_t pll_reg_shift)
  555 {
  556         uint32_t sec_cfg;
  557 
  558         /* set PLL registers */
  559         sec_cfg = ATH_READ_REG(cfg_reg);
  560         sec_cfg &= ~(3 << pll_reg_shift);
  561         sec_cfg |= (2 << pll_reg_shift);
  562 
  563         ATH_WRITE_REG(cfg_reg, sec_cfg);
  564         DELAY(100);
  565 
  566         ATH_WRITE_REG(pll_reg, pll);
  567         sec_cfg |= (3 << pll_reg_shift);
  568         ATH_WRITE_REG(cfg_reg, sec_cfg);
  569         DELAY(100);
  570 
  571         sec_cfg &= ~(3 << pll_reg_shift);
  572         ATH_WRITE_REG(cfg_reg, sec_cfg);
  573         DELAY(100);
  574 }
  575 
  576 #endif /* _AR71XX_REG_H_ */

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