The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/mips/atheros/ar724x_chip.c

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    1 /*-
    2  * Copyright (c) 2010 Adrian Chadd
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  */
   26 
   27 #include <sys/cdefs.h>
   28 __FBSDID("$FreeBSD: releng/10.1/sys/mips/atheros/ar724x_chip.c 253508 2013-07-21 03:52:52Z adrian $");
   29 
   30 #include "opt_ddb.h"
   31 
   32 #include <sys/param.h>
   33 #include <sys/conf.h>
   34 #include <sys/kernel.h>
   35 #include <sys/systm.h>
   36 #include <sys/bus.h>
   37 #include <sys/cons.h>
   38 #include <sys/kdb.h>
   39 #include <sys/reboot.h>
   40 
   41 #include <vm/vm.h>
   42 #include <vm/vm_page.h>
   43 
   44 #include <net/ethernet.h>
   45 
   46 #include <machine/clock.h>
   47 #include <machine/cpu.h>
   48 #include <machine/cpuregs.h>
   49 #include <machine/hwfunc.h>
   50 #include <machine/md_var.h>
   51 #include <machine/trap.h>
   52 #include <machine/vmparam.h>
   53 
   54 #include <mips/atheros/ar71xxreg.h>
   55 #include <mips/atheros/ar724xreg.h>
   56 
   57 #include <mips/atheros/ar71xx_cpudef.h>
   58 #include <mips/atheros/ar71xx_setup.h>
   59 #include <mips/atheros/ar71xx_chip.h>
   60 #include <mips/atheros/ar724x_chip.h>
   61 
   62 #include <mips/sentry5/s5reg.h>
   63 
   64 static void
   65 ar724x_chip_detect_mem_size(void)
   66 {
   67 }
   68 
   69 static void
   70 ar724x_chip_detect_sys_frequency(void)
   71 {
   72         uint32_t pll;
   73         uint32_t freq;
   74         uint32_t div;
   75 
   76         u_ar71xx_refclk = AR724X_BASE_FREQ;
   77 
   78         pll = ATH_READ_REG(AR724X_PLL_REG_CPU_CONFIG);
   79 
   80         div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);
   81         freq = div * AR724X_BASE_FREQ;
   82 
   83         div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
   84         freq *= div;
   85 
   86         u_ar71xx_cpu_freq = freq;
   87 
   88         div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
   89         u_ar71xx_ddr_freq = freq / div;
   90 
   91         div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
   92         u_ar71xx_ahb_freq = u_ar71xx_cpu_freq / div;
   93         u_ar71xx_wdt_freq = u_ar71xx_cpu_freq / div;
   94         u_ar71xx_uart_freq = u_ar71xx_cpu_freq / div;
   95 }
   96 
   97 static void
   98 ar724x_chip_device_stop(uint32_t mask)
   99 {
  100         uint32_t mask_inv, reg;
  101 
  102         mask_inv = mask & AR724X_RESET_MODULE_USB_OHCI_DLL;
  103         reg = ATH_READ_REG(AR724X_RESET_REG_RESET_MODULE);
  104         reg |= mask;
  105         reg &= ~mask_inv;
  106         ATH_WRITE_REG(AR724X_RESET_REG_RESET_MODULE, reg);
  107 }
  108 
  109 static void
  110 ar724x_chip_device_start(uint32_t mask)
  111 {
  112         uint32_t mask_inv, reg;
  113 
  114         mask_inv = mask & AR724X_RESET_MODULE_USB_OHCI_DLL;
  115         reg = ATH_READ_REG(AR724X_RESET_REG_RESET_MODULE);
  116         reg &= ~mask;
  117         reg |= mask_inv;
  118         ATH_WRITE_REG(AR724X_RESET_REG_RESET_MODULE, reg);
  119 }
  120 
  121 static int
  122 ar724x_chip_device_stopped(uint32_t mask)
  123 {
  124         uint32_t reg;
  125 
  126         reg = ATH_READ_REG(AR724X_RESET_REG_RESET_MODULE);
  127         return ((reg & mask) == mask);
  128 }
  129 
  130 static void
  131 ar724x_chip_set_mii_speed(uint32_t unit, uint32_t speed)
  132 {
  133 
  134         /* XXX TODO */
  135         return;
  136 }
  137 
  138 /*
  139  * XXX TODO: set the PLL for arge0 only on AR7242.
  140  * The PLL/clock requirements are different.
  141  *
  142  * Otherwise, it's a NULL function for AR7240, AR7241 and
  143  * AR7242 arge1.
  144  */
  145 static void
  146 ar724x_chip_set_pll_ge(int unit, int speed, uint32_t pll)
  147 {
  148 
  149         switch (unit) {
  150         case 0:
  151                 /* XXX TODO */
  152                 break;
  153         case 1:
  154                 /* XXX TODO */
  155                 break;
  156         default:
  157                 printf("%s: invalid PLL set for arge unit: %d\n",
  158                     __func__, unit);
  159                 return;
  160         }
  161 }
  162 
  163 static void
  164 ar724x_chip_ddr_flush_ge(int unit)
  165 {
  166 
  167         switch (unit) {
  168         case 0:
  169                 ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0);
  170                 break;
  171         case 1:
  172                 ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1);
  173                 break;
  174         default:
  175                 printf("%s: invalid DDR flush for arge unit: %d\n",
  176                     __func__, unit);
  177                 return;
  178         }
  179 }
  180 
  181 static void
  182 ar724x_chip_ddr_flush_ip2(void)
  183 {
  184 
  185         ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_PCIE);
  186 }
  187 
  188 static uint32_t
  189 ar724x_chip_get_eth_pll(unsigned int mac, int speed)
  190 {
  191 
  192         return (0);
  193 }
  194 
  195 static void
  196 ar724x_chip_init_usb_peripheral(void)
  197 {
  198 
  199         switch (ar71xx_soc) {
  200         case AR71XX_SOC_AR7240:
  201                 ar71xx_device_stop(AR724X_RESET_MODULE_USB_OHCI_DLL |
  202                     AR724X_RESET_USB_HOST);
  203                 DELAY(1000);
  204 
  205                 ar71xx_device_start(AR724X_RESET_MODULE_USB_OHCI_DLL |
  206                     AR724X_RESET_USB_HOST);
  207                 DELAY(1000);
  208 
  209                 /*
  210                  * WAR for HW bug. Here it adjusts the duration
  211                  * between two SOFS.
  212                  */
  213                 ATH_WRITE_REG(AR71XX_USB_CTRL_FLADJ,
  214                     (3 << USB_CTRL_FLADJ_A0_SHIFT));
  215 
  216                 break;
  217 
  218         case AR71XX_SOC_AR7241:
  219         case AR71XX_SOC_AR7242:
  220                 ar71xx_device_start(AR724X_RESET_MODULE_USB_OHCI_DLL);
  221                 DELAY(100);
  222 
  223                 ar71xx_device_start(AR724X_RESET_USB_HOST);
  224                 DELAY(100);
  225 
  226                 ar71xx_device_start(AR724X_RESET_USB_PHY);
  227                 DELAY(100);
  228 
  229                 break;
  230 
  231         default:
  232                 break;
  233         }
  234 }
  235 
  236 struct ar71xx_cpu_def ar724x_chip_def = {
  237         &ar724x_chip_detect_mem_size,
  238         &ar724x_chip_detect_sys_frequency,
  239         &ar724x_chip_device_stop,
  240         &ar724x_chip_device_start,
  241         &ar724x_chip_device_stopped,
  242         &ar724x_chip_set_pll_ge,
  243         &ar724x_chip_set_mii_speed,
  244         &ar71xx_chip_set_mii_if,
  245         &ar724x_chip_ddr_flush_ge,
  246         &ar724x_chip_get_eth_pll,
  247         &ar724x_chip_ddr_flush_ip2,
  248         &ar724x_chip_init_usb_peripheral
  249 };

Cache object: f63cc3ff4533b66839e44c702decd3b7


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