1 /*-
2 * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo@FreeBSD.org>
3 * Copyright (c) 2011, Luiz Otavio O Souza.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice unmodified, this list of conditions, and the following
11 * disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD: releng/9.0/sys/mips/atheros/ar724x_pci.c 221307 2011-05-01 23:32:37Z adrian $");
31
32 #include <sys/param.h>
33 #include <sys/systm.h>
34
35 #include <sys/bus.h>
36 #include <sys/interrupt.h>
37 #include <sys/malloc.h>
38 #include <sys/kernel.h>
39 #include <sys/module.h>
40 #include <sys/rman.h>
41
42 #include <vm/vm.h>
43 #include <vm/pmap.h>
44 #include <vm/vm_extern.h>
45
46 #include <machine/bus.h>
47 #include <machine/cpu.h>
48 #include <machine/intr_machdep.h>
49 #include <machine/pmap.h>
50
51 #include <dev/pci/pcivar.h>
52 #include <dev/pci/pcireg.h>
53
54 #include <dev/pci/pcib_private.h>
55 #include "pcib_if.h"
56
57 #include <mips/atheros/ar71xxreg.h>
58 #include <mips/atheros/ar724xreg.h>
59 #include <mips/atheros/ar71xx_setup.h>
60 #include <mips/atheros/ar71xx_pci_bus_space.h>
61
62 #include <mips/atheros/ar71xx_cpudef.h>
63
64 #undef AR724X_PCI_DEBUG
65 #ifdef AR724X_PCI_DEBUG
66 #define dprintf printf
67 #else
68 #define dprintf(x, arg...)
69 #endif
70
71 struct ar71xx_pci_softc {
72 device_t sc_dev;
73
74 int sc_busno;
75 struct rman sc_mem_rman;
76 struct rman sc_irq_rman;
77
78 struct intr_event *sc_eventstab[AR71XX_PCI_NIRQS];
79 mips_intrcnt_t sc_intr_counter[AR71XX_PCI_NIRQS];
80 struct resource *sc_irq;
81 void *sc_ih;
82 };
83
84 static int ar724x_pci_setup_intr(device_t, device_t, struct resource *, int,
85 driver_filter_t *, driver_intr_t *, void *, void **);
86 static int ar724x_pci_teardown_intr(device_t, device_t, struct resource *,
87 void *);
88 static int ar724x_pci_intr(void *);
89
90 static void
91 ar724x_pci_write(uint32_t reg, uint32_t offset, uint32_t data, int bytes)
92 {
93 uint32_t val, mask, shift;
94
95 /* Register access is 32-bit aligned */
96 shift = 8 * (offset & (bytes % 4));
97 if (bytes % 4)
98 mask = (1 << (bytes * 8)) - 1;
99 else
100 mask = 0xffffffff;
101
102 val = ATH_READ_REG(reg + (offset & ~3));
103 val &= ~(mask << shift);
104 val |= ((data & mask) << shift);
105 ATH_WRITE_REG(reg + (offset & ~3), val);
106
107 dprintf("%s: %#x/%#x addr=%#x, data=%#x(%#x), bytes=%d\n", __func__,
108 reg, reg + (offset & ~3), offset, data, val, bytes);
109 }
110
111 static uint32_t
112 ar724x_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func,
113 u_int reg, int bytes)
114 {
115 uint32_t data, shift, mask;
116
117 /* Register access is 32-bit aligned */
118 shift = (reg & 3) * 8;
119 if (shift)
120 mask = (1 << shift) - 1;
121 else
122 mask = 0xffffffff;
123
124 dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot,
125 func, reg, bytes);
126
127 if ((bus == 0) && (slot == 0) && (func == 0))
128 data = ATH_READ_REG(AR724X_PCI_CFG_BASE + (reg & ~3));
129 else
130 data = -1;
131
132 /* Get request bytes from 32-bit word */
133 data = (data >> shift) & mask;
134
135 dprintf("%s: read 0x%x\n", __func__, data);
136
137 return (data);
138 }
139
140 static void
141 ar724x_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func,
142 u_int reg, uint32_t data, int bytes)
143 {
144
145 dprintf("%s: tag (%x, %x, %x) reg %d(%d): %x\n", __func__, bus, slot,
146 func, reg, bytes, data);
147
148 if ((bus != 0) || (slot != 0) || (func != 0))
149 return;
150
151 /*
152 * WAR for BAR issue on AR7240 - We are unable to access the PCI device
153 * space if we set the BAR with proper base address.
154 */
155 if (reg == PCIR_BAR(0) && bytes == 4 && ar71xx_soc == AR71XX_SOC_AR7240)
156 ar724x_pci_write(AR724X_PCI_CFG_BASE, reg, 0xffff, bytes);
157 else
158 ar724x_pci_write(AR724X_PCI_CFG_BASE, reg, data, bytes);
159 }
160
161 static void
162 ar724x_pci_mask_irq(void *source)
163 {
164 uint32_t reg;
165 unsigned int irq = (unsigned int)source;
166
167 /* XXX - Only one interrupt ? Only one device ? */
168 if (irq != AR71XX_PCI_IRQ_START)
169 return;
170
171 /* Update the interrupt mask reg */
172 reg = ATH_READ_REG(AR724X_PCI_INTR_MASK);
173 ATH_WRITE_REG(AR724X_PCI_INTR_MASK,
174 reg & ~AR724X_PCI_INTR_DEV0);
175
176 /* Clear any pending interrupt */
177 reg = ATH_READ_REG(AR724X_PCI_INTR_STATUS);
178 ATH_WRITE_REG(AR724X_PCI_INTR_STATUS,
179 reg | AR724X_PCI_INTR_DEV0);
180 }
181
182 static void
183 ar724x_pci_unmask_irq(void *source)
184 {
185 uint32_t reg;
186 unsigned int irq = (unsigned int)source;
187
188 /* XXX */
189 if (irq != AR71XX_PCI_IRQ_START)
190 return;
191
192 /* Update the interrupt mask reg */
193 reg = ATH_READ_REG(AR724X_PCI_INTR_MASK);
194 ATH_WRITE_REG(AR724X_PCI_INTR_MASK,
195 reg | AR724X_PCI_INTR_DEV0);
196 }
197
198 static int
199 ar724x_pci_setup(device_t dev)
200 {
201 uint32_t reg;
202
203 /* setup COMMAND register */
204 reg = PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | PCIM_CMD_SERRESPEN |
205 PCIM_CMD_BACKTOBACK | PCIM_CMD_PERRESPEN | PCIM_CMD_MWRICEN;
206
207 ar724x_pci_write(AR724X_PCI_CRP_BASE, PCIR_COMMAND, reg, 2);
208 ar724x_pci_write(AR724X_PCI_CRP_BASE, 0x20, 0x1ff01000, 4);
209 ar724x_pci_write(AR724X_PCI_CRP_BASE, 0x24, 0x1ff01000, 4);
210
211 reg = ATH_READ_REG(AR724X_PCI_RESET);
212 if (reg != 0x7) {
213 DELAY(100000);
214 ATH_WRITE_REG(AR724X_PCI_RESET, 0);
215 DELAY(100);
216 ATH_WRITE_REG(AR724X_PCI_RESET, 4);
217 DELAY(100000);
218 }
219
220 if (ar71xx_soc == AR71XX_SOC_AR7240)
221 reg = AR724X_PCI_APP_LTSSM_ENABLE;
222 else
223 reg = 0x1ffc1;
224 ATH_WRITE_REG(AR724X_PCI_APP, reg);
225 /* Flush write */
226 (void) ATH_READ_REG(AR724X_PCI_APP);
227
228 DELAY(1000);
229
230 reg = ATH_READ_REG(AR724X_PCI_RESET);
231 if ((reg & AR724X_PCI_RESET_LINK_UP) == 0) {
232 device_printf(dev, "no PCIe controller found\n");
233 return (ENXIO);
234 }
235
236 if (ar71xx_soc == AR71XX_SOC_AR7241 ||
237 ar71xx_soc == AR71XX_SOC_AR7242) {
238 reg = ATH_READ_REG(AR724X_PCI_APP);
239 reg |= (1 << 16);
240 ATH_WRITE_REG(AR724X_PCI_APP, reg);
241 }
242
243 return (0);
244 }
245
246 #define AR5416_EEPROM_MAGIC 0xa55a
247
248 /*
249 * XXX - This should not be here ! And this looks like Atheros (if_ath) only.
250 */
251 static void
252 ar724x_load_eeprom_data(device_t dev)
253 {
254 uint32_t bar0, hint, reg, val;
255 uint16_t *data = NULL;
256
257 /* Search for a hint of eeprom data offset */
258 if (resource_int_value(device_get_name(dev),
259 device_get_unit(dev), "eepromdata", &hint) != 0)
260 return;
261
262 device_printf(dev, "Loading the eeprom fixup data from %#x\n", hint);
263 data = (uint16_t *)MIPS_PHYS_TO_KSEG1(hint);
264
265 if (*data != AR5416_EEPROM_MAGIC) {
266 device_printf(dev, "Invalid calibration data from %#x\n", hint);
267 return;
268 }
269
270 /* Save bar(0) address - just to flush bar(0) (SoC WAR) ? */
271 bar0 = ar724x_pci_read_config(dev, 0, 0, 0, PCIR_BAR(0), 4);
272
273 val = ar724x_pci_read_config(dev, 0, 0, 0, PCIR_COMMAND, 2);
274 val |= (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN);
275 ar724x_pci_write_config(dev, 0, 0, 0, PCIR_COMMAND, val, 2);
276
277 /* set pointer to first reg address */
278 data += 3;
279 while (*data != 0xffff) {
280 reg = *data++;
281 val = *data++;
282 val |= (*data++) << 16;
283
284 /* Write eeprom fixup data to device memory */
285 ATH_WRITE_REG(AR71XX_PCI_MEM_BASE + reg, val);
286 DELAY(100);
287 }
288
289 val = ar724x_pci_read_config(dev, 0, 0, 0, PCIR_COMMAND, 2);
290 val &= ~(PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN);
291 ar724x_pci_write_config(dev, 0, 0, 0, PCIR_COMMAND, val, 2);
292
293 /* Write the saved bar(0) address */
294 ar724x_pci_write_config(dev, 0, 0, 0, PCIR_BAR(0), bar0, 4);
295 }
296
297 #undef AR5416_EEPROM_MAGIC
298
299 static int
300 ar724x_pci_probe(device_t dev)
301 {
302
303 return (0);
304 }
305
306 static int
307 ar724x_pci_attach(device_t dev)
308 {
309 struct ar71xx_pci_softc *sc = device_get_softc(dev);
310 int busno = 0;
311 int rid = 0;
312
313 sc->sc_mem_rman.rm_type = RMAN_ARRAY;
314 sc->sc_mem_rman.rm_descr = "ar724x PCI memory window";
315 if (rman_init(&sc->sc_mem_rman) != 0 ||
316 rman_manage_region(&sc->sc_mem_rman, AR71XX_PCI_MEM_BASE,
317 AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1) != 0) {
318 panic("ar724x_pci_attach: failed to set up I/O rman");
319 }
320
321 sc->sc_irq_rman.rm_type = RMAN_ARRAY;
322 sc->sc_irq_rman.rm_descr = "ar724x PCI IRQs";
323 if (rman_init(&sc->sc_irq_rman) != 0 ||
324 rman_manage_region(&sc->sc_irq_rman, AR71XX_PCI_IRQ_START,
325 AR71XX_PCI_IRQ_END) != 0)
326 panic("ar724x_pci_attach: failed to set up IRQ rman");
327
328 /* Disable interrupts */
329 ATH_WRITE_REG(AR724X_PCI_INTR_STATUS, 0);
330 ATH_WRITE_REG(AR724X_PCI_INTR_MASK, 0);
331
332 /* Hook up our interrupt handler. */
333 if ((sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
334 RF_SHAREABLE | RF_ACTIVE)) == NULL) {
335 device_printf(dev, "unable to allocate IRQ resource\n");
336 return (ENXIO);
337 }
338
339 if ((bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_MISC,
340 ar724x_pci_intr, NULL, sc, &sc->sc_ih))) {
341 device_printf(dev,
342 "WARNING: unable to register interrupt handler\n");
343 return (ENXIO);
344 }
345
346 /* Reset PCIe core and PCIe PHY */
347 ar71xx_device_stop(AR724X_RESET_PCIE);
348 ar71xx_device_stop(AR724X_RESET_PCIE_PHY);
349 ar71xx_device_stop(AR724X_RESET_PCIE_PHY_SERIAL);
350 DELAY(100);
351
352 ar71xx_device_start(AR724X_RESET_PCIE_PHY_SERIAL);
353 DELAY(100);
354 ar71xx_device_start(AR724X_RESET_PCIE_PHY);
355 ar71xx_device_start(AR724X_RESET_PCIE);
356
357 if (ar724x_pci_setup(dev))
358 return (ENXIO);
359
360 /* XXX - Load eeprom fixup data */
361 ar724x_load_eeprom_data(dev);
362
363 /* Fixup internal PCI bridge */
364 ar724x_pci_write_config(dev, 0, 0, 0, PCIR_COMMAND,
365 PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN
366 | PCIM_CMD_SERRESPEN | PCIM_CMD_BACKTOBACK
367 | PCIM_CMD_PERRESPEN | PCIM_CMD_MWRICEN, 2);
368
369 device_add_child(dev, "pci", busno);
370 return (bus_generic_attach(dev));
371 }
372
373 static int
374 ar724x_pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
375 {
376 struct ar71xx_pci_softc *sc = device_get_softc(dev);
377
378 switch (which) {
379 case PCIB_IVAR_DOMAIN:
380 *result = 0;
381 return (0);
382 case PCIB_IVAR_BUS:
383 *result = sc->sc_busno;
384 return (0);
385 }
386
387 return (ENOENT);
388 }
389
390 static int
391 ar724x_pci_write_ivar(device_t dev, device_t child, int which, uintptr_t result)
392 {
393 struct ar71xx_pci_softc * sc = device_get_softc(dev);
394
395 switch (which) {
396 case PCIB_IVAR_BUS:
397 sc->sc_busno = result;
398 return (0);
399 }
400
401 return (ENOENT);
402 }
403
404 static struct resource *
405 ar724x_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
406 u_long start, u_long end, u_long count, u_int flags)
407 {
408 struct ar71xx_pci_softc *sc = device_get_softc(bus);
409 struct resource *rv;
410 struct rman *rm;
411
412 switch (type) {
413 case SYS_RES_IRQ:
414 rm = &sc->sc_irq_rman;
415 break;
416 case SYS_RES_MEMORY:
417 rm = &sc->sc_mem_rman;
418 break;
419 default:
420 return (NULL);
421 }
422
423 rv = rman_reserve_resource(rm, start, end, count, flags, child);
424
425 if (rv == NULL)
426 return (NULL);
427
428 rman_set_rid(rv, *rid);
429
430 if (flags & RF_ACTIVE) {
431 if (bus_activate_resource(child, type, *rid, rv)) {
432 rman_release_resource(rv);
433 return (NULL);
434 }
435 }
436
437
438 return (rv);
439 }
440
441 static int
442 ar724x_pci_activate_resource(device_t bus, device_t child, int type, int rid,
443 struct resource *r)
444 {
445 int res = (BUS_ACTIVATE_RESOURCE(device_get_parent(bus),
446 child, type, rid, r));
447
448 if (!res) {
449 switch(type) {
450 case SYS_RES_MEMORY:
451 case SYS_RES_IOPORT:
452
453 rman_set_bustag(r, ar71xx_bus_space_pcimem);
454 break;
455 }
456 }
457
458 return (res);
459 }
460
461 static int
462 ar724x_pci_setup_intr(device_t bus, device_t child, struct resource *ires,
463 int flags, driver_filter_t *filt, driver_intr_t *handler,
464 void *arg, void **cookiep)
465 {
466 struct ar71xx_pci_softc *sc = device_get_softc(bus);
467 struct intr_event *event;
468 int irq, error;
469
470 irq = rman_get_start(ires);
471 if (irq > AR71XX_PCI_IRQ_END)
472 panic("%s: bad irq %d", __func__, irq);
473
474 event = sc->sc_eventstab[irq];
475 if (event == NULL) {
476 error = intr_event_create(&event, (void *)irq, 0, irq,
477 ar724x_pci_mask_irq, ar724x_pci_unmask_irq, NULL, NULL,
478 "pci intr%d:", irq);
479
480 if (error == 0) {
481 sc->sc_eventstab[irq] = event;
482 sc->sc_intr_counter[irq] =
483 mips_intrcnt_create(event->ie_name);
484 }
485 else
486 return error;
487 }
488
489 intr_event_add_handler(event, device_get_nameunit(child), filt,
490 handler, arg, intr_priority(flags), flags, cookiep);
491 mips_intrcnt_setname(sc->sc_intr_counter[irq], event->ie_fullname);
492
493 ar724x_pci_unmask_irq((void*)irq);
494
495 return (0);
496 }
497
498 static int
499 ar724x_pci_teardown_intr(device_t dev, device_t child, struct resource *ires,
500 void *cookie)
501 {
502 struct ar71xx_pci_softc *sc = device_get_softc(dev);
503 int irq, result;
504
505 irq = rman_get_start(ires);
506 if (irq > AR71XX_PCI_IRQ_END)
507 panic("%s: bad irq %d", __func__, irq);
508
509 if (sc->sc_eventstab[irq] == NULL)
510 panic("Trying to teardown unoccupied IRQ");
511
512 ar724x_pci_mask_irq((void*)irq);
513
514 result = intr_event_remove_handler(cookie);
515 if (!result)
516 sc->sc_eventstab[irq] = NULL;
517
518 return (result);
519 }
520
521 static int
522 ar724x_pci_intr(void *arg)
523 {
524 struct ar71xx_pci_softc *sc = arg;
525 struct intr_event *event;
526 uint32_t reg, irq, mask;
527
528 ar71xx_device_ddr_flush_ip2();
529
530 reg = ATH_READ_REG(AR724X_PCI_INTR_STATUS);
531 mask = ATH_READ_REG(AR724X_PCI_INTR_MASK);
532 /*
533 * Handle only unmasked interrupts
534 */
535 reg &= mask;
536 if (reg & AR724X_PCI_INTR_DEV0) {
537
538 irq = AR71XX_PCI_IRQ_START;
539 event = sc->sc_eventstab[irq];
540 if (!event || TAILQ_EMPTY(&event->ie_handlers)) {
541 printf("Stray IRQ %d\n", irq);
542 return (FILTER_STRAY);
543 }
544
545 /* TODO: frame instead of NULL? */
546 intr_event_handle(event, NULL);
547 mips_intrcnt_inc(sc->sc_intr_counter[irq]);
548 }
549
550 return (FILTER_HANDLED);
551 }
552
553 static int
554 ar724x_pci_maxslots(device_t dev)
555 {
556
557 return (PCI_SLOTMAX);
558 }
559
560 static int
561 ar724x_pci_route_interrupt(device_t pcib, device_t device, int pin)
562 {
563
564 return (pci_get_slot(device));
565 }
566
567 static device_method_t ar724x_pci_methods[] = {
568 /* Device interface */
569 DEVMETHOD(device_probe, ar724x_pci_probe),
570 DEVMETHOD(device_attach, ar724x_pci_attach),
571 DEVMETHOD(device_shutdown, bus_generic_shutdown),
572 DEVMETHOD(device_suspend, bus_generic_suspend),
573 DEVMETHOD(device_resume, bus_generic_resume),
574
575 /* Bus interface */
576 DEVMETHOD(bus_print_child, bus_generic_print_child),
577 DEVMETHOD(bus_read_ivar, ar724x_pci_read_ivar),
578 DEVMETHOD(bus_write_ivar, ar724x_pci_write_ivar),
579 DEVMETHOD(bus_alloc_resource, ar724x_pci_alloc_resource),
580 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
581 DEVMETHOD(bus_activate_resource, ar724x_pci_activate_resource),
582 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
583 DEVMETHOD(bus_setup_intr, ar724x_pci_setup_intr),
584 DEVMETHOD(bus_teardown_intr, ar724x_pci_teardown_intr),
585
586 /* pcib interface */
587 DEVMETHOD(pcib_maxslots, ar724x_pci_maxslots),
588 DEVMETHOD(pcib_read_config, ar724x_pci_read_config),
589 DEVMETHOD(pcib_write_config, ar724x_pci_write_config),
590 DEVMETHOD(pcib_route_interrupt, ar724x_pci_route_interrupt),
591
592 {0, 0}
593 };
594
595 static driver_t ar724x_pci_driver = {
596 "pcib",
597 ar724x_pci_methods,
598 sizeof(struct ar71xx_pci_softc),
599 };
600
601 static devclass_t ar724x_pci_devclass;
602
603 DRIVER_MODULE(ar724x_pci, nexus, ar724x_pci_driver, ar724x_pci_devclass, 0, 0);
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