The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/mips/atheros/ar724xreg.h

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
    3  *
    4  * Copyright (c) 2010 Adrian Chadd
    5  * All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  *
   16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   26  * SUCH DAMAGE.
   27  */
   28 
   29 /* $FreeBSD: stable/12/sys/mips/atheros/ar724xreg.h 326259 2017-11-27 15:07:26Z pfg $ */
   30 
   31 #ifndef __AR72XX_REG_H__
   32 #define __AR72XX_REG_H__
   33 
   34 #define AR724X_PLL_REG_CPU_CONFIG       AR71XX_PLL_CPU_BASE + 0x00
   35 #define AR724X_PLL_REG_PCIE_CONFIG      AR71XX_PLL_CPU_BASE + 0x18
   36 
   37 #define AR724X_PLL_DIV_SHIFT            0
   38 #define AR724X_PLL_DIV_MASK             0x3ff
   39 #define AR724X_PLL_REF_DIV_SHIFT        10
   40 #define AR724X_PLL_REF_DIV_MASK         0xf
   41 #define AR724X_AHB_DIV_SHIFT            19
   42 #define AR724X_AHB_DIV_MASK             0x1
   43 #define AR724X_DDR_DIV_SHIFT            22
   44 #define AR724X_DDR_DIV_MASK             0x3
   45 
   46 #define AR724X_PLL_VAL_1000             0x00110000
   47 #define AR724X_PLL_VAL_100              0x00001099
   48 #define AR724X_PLL_VAL_10               0x00991099
   49 
   50 #define AR724X_BASE_FREQ                5000000
   51 
   52 #define AR724X_DDR_REG_FLUSH_GE0        (AR71XX_DDR_CONFIG + 0x7c)
   53 #define AR724X_DDR_REG_FLUSH_GE1        (AR71XX_DDR_CONFIG + 0x80)
   54 #define AR724X_DDR_REG_FLUSH_USB        (AR71XX_DDR_CONFIG + 0x84)
   55 #define AR724X_DDR_REG_FLUSH_PCIE       (AR71XX_DDR_CONFIG + 0x88)
   56 
   57 #define AR724X_RESET_REG_RESET_MODULE   AR71XX_RST_BLOCK_BASE + 0x1c
   58 #define AR724X_RESET_USB_HOST                   (1 << 5)
   59 #define AR724X_RESET_USB_PHY                    (1 << 4)
   60 #define AR724X_RESET_MODULE_USB_OHCI_DLL        (1 << 3)
   61 
   62 #define AR724X_RESET_GE1_MDIO                   (1 << 23)
   63 #define AR724X_RESET_GE0_MDIO                   (1 << 22)
   64 #define AR724X_RESET_PCIE_PHY_SERIAL            (1 << 10)
   65 #define AR724X_RESET_PCIE_PHY                   (1 << 7)
   66 #define AR724X_RESET_PCIE                       (1 << 6)
   67 #define AR724X_RESET_USB_HOST                   (1 << 5)
   68 #define AR724X_RESET_USB_PHY                    (1 << 4)
   69 #define AR724X_RESET_USBSUS_OVERRIDE            (1 << 3)
   70 
   71 /* XXX so USB requires different init code? -adrian */
   72 #define AR7240_OHCI_BASE                0x1b000000
   73 #define AR7240_OHCI_SIZE                0x01000000
   74 
   75 #define AR724X_PCI_CRP_BASE             (AR71XX_APB_BASE + 0x000C0000)
   76 #define AR724X_PCI_CRP_SIZE             0x100
   77 #define AR724X_PCI_CFG_BASE             0x14000000
   78 #define AR724X_PCI_CFG_SIZE             0x1000
   79 
   80 #define AR724X_PCI_CTRL_BASE            (AR71XX_APB_BASE + 0x000F0000)
   81 #define AR724X_PCI_CTRL_SIZE            0x100
   82 
   83 /* PCI config registers - AR724X_PCI_CTRL_BASE */
   84 #define AR724X_PCI_APP                  0x180f0000
   85 #define AR724X_PCI_APP_LTSSM_ENABLE     (1 << 0)
   86 #define AR724X_PCI_RESET                0x180f0018
   87 #define AR724X_PCI_RESET_LINK_UP        (1 << 0)
   88 #define AR724X_PCI_INTR_STATUS          0x180f004c
   89 #define AR724X_PCI_INTR_MASK            0x180f0050
   90 #define AR724X_PCI_INTR_DEV0            (1 << 14)
   91 
   92 #define AR724X_GPIO_FUNC_GE0_MII_CLK_EN         (1 << 19)
   93 #define AR724X_GPIO_FUNC_SPI_EN                 (1 << 18)
   94 #define AR724X_GPIO_FUNC_SPI_CS_EN2             (1 << 14)
   95 #define AR724X_GPIO_FUNC_SPI_CS_EN1             (1 << 13)
   96 #define AR724X_GPIO_FUNC_CLK_OBS5_EN            (1 << 12)
   97 #define AR724X_GPIO_FUNC_CLK_OBS4_EN            (1 << 11)
   98 #define AR724X_GPIO_FUNC_CLK_OBS3_EN            (1 << 10)
   99 #define AR724X_GPIO_FUNC_CLK_OBS2_EN            (1 << 9)
  100 #define AR724X_GPIO_FUNC_CLK_OBS1_EN            (1 << 8)
  101 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN     (1 << 7)
  102 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN     (1 << 6)
  103 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN     (1 << 5)
  104 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN     (1 << 4)
  105 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN     (1 << 3)
  106 #define AR724X_GPIO_FUNC_UART_RTS_CTS_EN        (1 << 2)
  107 #define AR724X_GPIO_FUNC_UART_EN                (1 << 1)
  108 #define AR724X_GPIO_FUNC_JTAG_DISABLE           (1 << 0)
  109 
  110 #endif

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