1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2010 Adrian Chadd
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD: releng/12.0/sys/mips/atheros/ar91xx_chip.c 326259 2017-11-27 15:07:26Z pfg $");
31
32 #include "opt_ddb.h"
33
34 #include <sys/param.h>
35 #include <sys/conf.h>
36 #include <sys/kernel.h>
37 #include <sys/systm.h>
38 #include <sys/bus.h>
39 #include <sys/cons.h>
40 #include <sys/kdb.h>
41 #include <sys/reboot.h>
42
43 #include <vm/vm.h>
44 #include <vm/vm_page.h>
45
46 #include <net/ethernet.h>
47
48 #include <machine/clock.h>
49 #include <machine/cpu.h>
50 #include <machine/cpuregs.h>
51 #include <machine/hwfunc.h>
52 #include <machine/md_var.h>
53 #include <machine/trap.h>
54 #include <machine/vmparam.h>
55
56 #include <mips/atheros/ar71xxreg.h>
57 #include <mips/atheros/ar71xx_cpudef.h>
58 #include <mips/atheros/ar71xx_chip.h>
59 #include <mips/atheros/ar91xxreg.h>
60 #include <mips/atheros/ar91xx_chip.h>
61
62 static void
63 ar91xx_chip_detect_mem_size(void)
64 {
65 }
66
67 static void
68 ar91xx_chip_detect_sys_frequency(void)
69 {
70 uint32_t pll;
71 uint32_t freq;
72 uint32_t div;
73
74 u_ar71xx_mdio_freq = u_ar71xx_refclk = AR91XX_BASE_FREQ;
75
76 pll = ATH_READ_REG(AR91XX_PLL_REG_CPU_CONFIG);
77
78 div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK);
79 freq = div * AR91XX_BASE_FREQ;
80 u_ar71xx_cpu_freq = freq;
81
82 div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1;
83 u_ar71xx_ddr_freq = freq / div;
84
85 div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2;
86 u_ar71xx_ahb_freq = u_ar71xx_cpu_freq / div;
87 u_ar71xx_uart_freq = u_ar71xx_cpu_freq / div;
88 u_ar71xx_wdt_freq = u_ar71xx_cpu_freq / div;
89 }
90
91 static void
92 ar91xx_chip_device_stop(uint32_t mask)
93 {
94 uint32_t reg;
95
96 reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE);
97 ATH_WRITE_REG(AR91XX_RESET_REG_RESET_MODULE, reg | mask);
98 }
99
100 static void
101 ar91xx_chip_device_start(uint32_t mask)
102 {
103 uint32_t reg;
104
105 reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE);
106 ATH_WRITE_REG(AR91XX_RESET_REG_RESET_MODULE, reg & ~mask);
107 }
108
109 static int
110 ar91xx_chip_device_stopped(uint32_t mask)
111 {
112 uint32_t reg;
113
114 reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE);
115 return ((reg & mask) == mask);
116 }
117
118 static void
119 ar91xx_chip_set_pll_ge(int unit, int speed, uint32_t pll)
120 {
121
122 switch (unit) {
123 case 0:
124 ar71xx_write_pll(AR91XX_PLL_REG_ETH_CONFIG,
125 AR91XX_PLL_REG_ETH0_INT_CLOCK, pll,
126 AR91XX_ETH0_PLL_SHIFT);
127 break;
128 case 1:
129 ar71xx_write_pll(AR91XX_PLL_REG_ETH_CONFIG,
130 AR91XX_PLL_REG_ETH1_INT_CLOCK, pll,
131 AR91XX_ETH1_PLL_SHIFT);
132 break;
133 default:
134 printf("%s: invalid PLL set for arge unit: %d\n",
135 __func__, unit);
136 return;
137 }
138 }
139
140 static void
141 ar91xx_chip_ddr_flush(ar71xx_flush_ddr_id_t id)
142 {
143
144 switch (id) {
145 case AR71XX_CPU_DDR_FLUSH_GE0:
146 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0);
147 break;
148 case AR71XX_CPU_DDR_FLUSH_GE1:
149 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1);
150 break;
151 case AR71XX_CPU_DDR_FLUSH_USB:
152 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_USB);
153 break;
154 case AR71XX_CPU_DDR_FLUSH_WMAC:
155 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_WMAC);
156 break;
157 default:
158 printf("%s: invalid DDR flush id (%d)\n", __func__, id);
159 break;
160 }
161 }
162
163 static uint32_t
164 ar91xx_chip_get_eth_pll(unsigned int mac, int speed)
165 {
166 uint32_t pll;
167
168 switch(speed) {
169 case 10:
170 pll = AR91XX_PLL_VAL_10;
171 break;
172 case 100:
173 pll = AR91XX_PLL_VAL_100;
174 break;
175 case 1000:
176 pll = AR91XX_PLL_VAL_1000;
177 break;
178 default:
179 printf("%s%d: invalid speed %d\n", __func__, mac, speed);
180 pll = 0;
181 }
182
183 return (pll);
184 }
185
186 static void
187 ar91xx_chip_init_usb_peripheral(void)
188 {
189
190 ar71xx_device_stop(AR91XX_RST_RESET_MODULE_USBSUS_OVERRIDE);
191 DELAY(100);
192
193 ar71xx_device_start(RST_RESET_USB_HOST);
194 DELAY(100);
195
196 ar71xx_device_start(RST_RESET_USB_PHY);
197 DELAY(100);
198
199 /* Wireless */
200 ar71xx_device_stop(AR91XX_RST_RESET_MODULE_AMBA2WMAC);
201 DELAY(1000);
202
203 ar71xx_device_start(AR91XX_RST_RESET_MODULE_AMBA2WMAC);
204 DELAY(1000);
205 }
206
207 struct ar71xx_cpu_def ar91xx_chip_def = {
208 &ar91xx_chip_detect_mem_size,
209 &ar91xx_chip_detect_sys_frequency,
210 &ar91xx_chip_device_stop,
211 &ar91xx_chip_device_start,
212 &ar91xx_chip_device_stopped,
213 &ar91xx_chip_set_pll_ge,
214 &ar71xx_chip_set_mii_speed,
215 &ar71xx_chip_set_mii_if,
216 &ar91xx_chip_get_eth_pll,
217 &ar91xx_chip_ddr_flush,
218 &ar91xx_chip_init_usb_peripheral,
219 };
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