ar933x_chip.c

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    1 /*-
    2  * Copyright (c) 2012 Adrian Chadd <adrian@FreeBSD.org>
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  */
   26 
   27 #include <sys/cdefs.h>
   28 __FBSDID("$FreeBSD: releng/10.4/sys/mips/atheros/ar933x_chip.c 255764 2013-09-21 19:42:37Z adrian $");
   29 
   30 #include "opt_ddb.h"
   31 
   32 #include <sys/param.h>
   33 #include <sys/conf.h>
   34 #include <sys/kernel.h>
   35 #include <sys/systm.h>
   36 #include <sys/bus.h>
   37 #include <sys/cons.h>
   38 #include <sys/kdb.h>
   39 #include <sys/reboot.h>
   40 
   41 #include <vm/vm.h>
   42 #include <vm/vm_page.h>
   43 
   44 #include <net/ethernet.h>
   45 
   46 #include <machine/clock.h>
   47 #include <machine/cpu.h>
   48 #include <machine/cpuregs.h>
   49 #include <machine/hwfunc.h>
   50 #include <machine/md_var.h>
   51 #include <machine/trap.h>
   52 #include <machine/vmparam.h>
   53 
   54 #include <mips/atheros/ar71xxreg.h>
   55 #include <mips/atheros/ar933xreg.h>
   56 
   57 #include <mips/atheros/ar71xx_cpudef.h>
   58 #include <mips/atheros/ar71xx_setup.h>
   59 
   60 #include <mips/atheros/ar71xx_chip.h>
   61 #include <mips/atheros/ar933x_chip.h>
   62 
   63 static void
   64 ar933x_chip_detect_mem_size(void)
   65 {
   66 }
   67 
   68 static void
   69 ar933x_chip_detect_sys_frequency(void)
   70 {
   71         uint32_t clock_ctrl;
   72         uint32_t cpu_config;
   73         uint32_t freq;
   74         uint32_t t;
   75 
   76         t = ATH_READ_REG(AR933X_RESET_REG_BOOTSTRAP);
   77         if (t & AR933X_BOOTSTRAP_REF_CLK_40)
   78                 u_ar71xx_refclk = (40 * 1000 * 1000);
   79         else
   80                 u_ar71xx_refclk = (25 * 1000 * 1000);
   81 
   82         clock_ctrl = ATH_READ_REG(AR933X_PLL_CLOCK_CTRL_REG);
   83         if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
   84                 u_ar71xx_cpu_freq = u_ar71xx_refclk;
   85                 u_ar71xx_ahb_freq = u_ar71xx_refclk;
   86                 u_ar71xx_ddr_freq = u_ar71xx_refclk;
   87         } else {
   88                 cpu_config = ATH_READ_REG(AR933X_PLL_CPU_CONFIG_REG);
   89 
   90                 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
   91                     AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
   92                 freq = u_ar71xx_refclk / t;
   93 
   94                 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
   95                     AR933X_PLL_CPU_CONFIG_NINT_MASK;
   96                 freq *= t;
   97 
   98                 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
   99                     AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
  100                 if (t == 0)
  101                         t = 1;
  102 
  103                 freq >>= t;
  104 
  105                 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
  106                      AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
  107                 u_ar71xx_cpu_freq = freq / t;
  108 
  109                 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
  110                       AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
  111                 u_ar71xx_ddr_freq = freq / t;
  112 
  113                 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
  114                      AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
  115                 u_ar71xx_ahb_freq = freq / t;
  116         }
  117 
  118         /* On the AR933x, the UART frequency is the reference clock,
  119          * not the AHB bus clock.
  120          */
  121         u_ar71xx_uart_freq = u_ar71xx_refclk;
  122 
  123         /*
  124          * XXX check what the watchdog frequency should be?
  125          */
  126         u_ar71xx_wdt_freq = u_ar71xx_ahb_freq;
  127 }
  128 
  129 static void
  130 ar933x_chip_device_stop(uint32_t mask)
  131 {
  132         uint32_t reg;
  133 
  134         reg = ATH_READ_REG(AR933X_RESET_REG_RESET_MODULE);
  135         ATH_WRITE_REG(AR933X_RESET_REG_RESET_MODULE, reg | mask);
  136 }
  137 
  138 static void
  139 ar933x_chip_device_start(uint32_t mask)
  140 {
  141         uint32_t reg;
  142 
  143         reg = ATH_READ_REG(AR933X_RESET_REG_RESET_MODULE);
  144         ATH_WRITE_REG(AR933X_RESET_REG_RESET_MODULE, reg & ~mask);
  145 }
  146 
  147 static int
  148 ar933x_chip_device_stopped(uint32_t mask)
  149 {
  150         uint32_t reg;
  151 
  152         reg = ATH_READ_REG(AR933X_RESET_REG_RESET_MODULE);
  153         return ((reg & mask) == mask);
  154 }
  155 
  156 static void
  157 ar933x_chip_set_mii_speed(uint32_t unit, uint32_t speed)
  158 {
  159 
  160         /* XXX TODO */
  161         return;
  162 }
  163 
  164 /*
  165  * XXX TODO !!
  166  */
  167 static void
  168 ar933x_chip_set_pll_ge(int unit, int speed, uint32_t pll)
  169 {
  170 
  171         switch (unit) {
  172         case 0:
  173                 /* XXX TODO */
  174                 break;
  175         case 1:
  176                 /* XXX TODO */
  177                 break;
  178         default:
  179                 printf("%s: invalid PLL set for arge unit: %d\n",
  180                     __func__, unit);
  181                 return;
  182         }
  183 }
  184 
  185 static void
  186 ar933x_chip_ddr_flush_ge(int unit)
  187 {
  188 
  189         switch (unit) {
  190         case 0:
  191                 ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE0);
  192                 break;
  193         case 1:
  194                 ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE1);
  195                 break;
  196         default:
  197                 printf("%s: invalid DDR flush for arge unit: %d\n",
  198                     __func__, unit);
  199                 return;
  200         }
  201 }
  202 
  203 static void
  204 ar933x_chip_ddr_flush_ip2(void)
  205 {
  206 
  207         ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_WMAC);
  208 }
  209 
  210 static uint32_t
  211 ar933x_chip_get_eth_pll(unsigned int mac, int speed)
  212 {
  213         uint32_t pll;
  214 
  215         switch (speed) {
  216         case 10:
  217                 pll = AR933X_PLL_VAL_10;
  218                 break;
  219         case 100:
  220                 pll = AR933X_PLL_VAL_100;
  221                 break;
  222         case 1000:
  223                 pll = AR933X_PLL_VAL_1000;
  224                 break;
  225         default:
  226                 printf("%s%d: invalid speed %d\n", __func__, mac, speed);
  227                 pll = 0;
  228         }
  229         return (pll);
  230 }
  231 
  232 static void
  233 ar933x_chip_init_usb_peripheral(void)
  234 {
  235         ar71xx_device_stop(AR933X_RESET_USBSUS_OVERRIDE);
  236         DELAY(100);
  237 
  238         ar71xx_device_start(AR933X_RESET_USB_HOST);
  239         DELAY(100);
  240 
  241         ar71xx_device_start(AR933X_RESET_USB_PHY);
  242         DELAY(100);
  243 }
  244 
  245 struct ar71xx_cpu_def ar933x_chip_def = {
  246         &ar933x_chip_detect_mem_size,
  247         &ar933x_chip_detect_sys_frequency,
  248         &ar933x_chip_device_stop,
  249         &ar933x_chip_device_start,
  250         &ar933x_chip_device_stopped,
  251         &ar933x_chip_set_pll_ge,
  252         &ar933x_chip_set_mii_speed,
  253         &ar71xx_chip_set_mii_if,
  254         &ar933x_chip_ddr_flush_ge,
  255         &ar933x_chip_get_eth_pll,
  256         &ar933x_chip_ddr_flush_ip2,
  257         &ar933x_chip_init_usb_peripheral
  258 };

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sys/mips/atheros/ar933x_chip.c