The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/mips/atheros/ar933xreg.h

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
    3  *
    4  * Copyright (c) 2012 Adrian Chadd <adrian@FreeBSD.org>
    5  * All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  *
   16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   26  * SUCH DAMAGE.
   27  *
   28  * $FreeBSD: stable/12/sys/mips/atheros/ar933xreg.h 326259 2017-11-27 15:07:26Z pfg $
   29  */
   30 
   31 #ifndef __AR93XX_REG_H__
   32 #define __AR93XX_REG_H__
   33 
   34 #define REV_ID_MAJOR_AR9330             0x0110
   35 #define REV_ID_MAJOR_AR9331             0x1110
   36 
   37 #define AR933X_REV_ID_REVISION_MASK     0x3
   38 
   39 #define AR933X_GPIO_COUNT               30
   40 
   41 #define AR933X_UART_BASE        (AR71XX_APB_BASE + 0x00020000)
   42 #define AR933X_UART_SIZE        0x14
   43 
   44 #define AR933X_GMAC_BASE        (AR71XX_APB_BASE + 0x00070000)
   45 #define AR933X_GMAC_SIZE        0x04
   46 
   47 #define AR933X_GMAC_REG_ETH_CFG         (AR933X_GMAC_BASE + 0x00)
   48 
   49 #define AR933X_ETH_CFG_RGMII_GE0        (1 << 0)
   50 #define AR933X_ETH_CFG_MII_GE0          (1 << 1)
   51 #define AR933X_ETH_CFG_GMII_GE0         (1 << 2)
   52 #define AR933X_ETH_CFG_MII_GE0_MASTER   (1 << 3)
   53 #define AR933X_ETH_CFG_MII_GE0_SLAVE    (1 << 4)
   54 #define AR933X_ETH_CFG_MII_GE0_ERR_EN   (1 << 5)
   55 #define AR933X_ETH_CFG_SW_PHY_SWAP      (1 << 7)
   56 #define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP (1 << 8)
   57 #define AR933X_ETH_CFG_RMII_GE0         (1 << 9)
   58 #define AR933X_ETH_CFG_RMII_GE0_SPD_10          0
   59 #define AR933X_ETH_CFG_RMII_GE0_SPD_100         (1 << 10)
   60 
   61 #define AR933X_WMAC_BASE        (AR71XX_APB_BASE + 0x00100000)
   62 #define AR933X_WMAC_SIZE        0x20000
   63 #define AR933X_EHCI_BASE        0x1b000000
   64 #define AR933X_EHCI_SIZE        0x1000
   65 
   66 #define AR933X_DDR_REG_FLUSH_GE0        (AR71XX_APB_BASE + 0x7c)
   67 #define AR933X_DDR_REG_FLUSH_GE1        (AR71XX_APB_BASE + 0x80)
   68 #define AR933X_DDR_REG_FLUSH_USB        (AR71XX_APB_BASE + 0x84)
   69 #define AR933X_DDR_REG_FLUSH_WMAC       (AR71XX_APB_BASE + 0x88)
   70 
   71 #define AR933X_PLL_CPU_CONFIG_REG       (AR71XX_PLL_CPU_BASE + 0x00)
   72 #define AR933X_PLL_CLOCK_CTRL_REG       (AR71XX_PLL_CPU_BASE + 0x08)
   73 
   74 #define AR933X_PLL_CPU_CONFIG_NINT_SHIFT        10
   75 #define AR933X_PLL_CPU_CONFIG_NINT_MASK         0x3f
   76 #define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT      16
   77 #define AR933X_PLL_CPU_CONFIG_REFDIV_MASK       0x1f
   78 #define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT      23
   79 #define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK       0x7
   80 
   81 #define AR933X_PLL_CLOCK_CTRL_BYPASS            (1 << 2)
   82 #define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT     5
   83 #define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK      0x3
   84 #define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT     10
   85 #define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK      0x3
   86 #define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT     15
   87 #define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK      0x7
   88 
   89 #define AR933X_RESET_REG_RESET_MODULE           (AR71XX_RST_BLOCK_BASE + 0x1c)
   90 #define AR933X_RESET_REG_BOOTSTRAP              (AR71XX_RST_BLOCK_BASE + 0xac)
   91 #define AR933X_RESET_WMAC                       (1 << 11)
   92 #define AR933X_RESET_USB_HOST                   (1 << 5)
   93 #define AR933X_RESET_USB_PHY                    (1 << 4)
   94 #define AR933X_RESET_USBSUS_OVERRIDE            (1 << 3)
   95 
   96 #define AR933X_BOOTSTRAP_REF_CLK_40             (1 << 0)
   97 
   98 #define AR933X_PLL_VAL_1000                     0x00110000
   99 #define AR933X_PLL_VAL_100                      0x00001099
  100 #define AR933X_PLL_VAL_10                       0x00991099
  101 
  102 #endif  /* __AR93XX_REG_H__ */

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